IDT5V993A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
Rating
Max.
Unit
Supply Voltage to Ground
–0.5 to +7
V
1
REF
VCCQ
FS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VI
DC Input Voltage
–0.5 to VCC+0.5
–0.5 to +5.5
0.66
V
V
2
TEST
REF Input Voltage
1
2F
3
Maximum Power Dissipation (TA = 85°C)
Storage Temperature Range
W
°C
2F0
3F0
3F1
4
TSTG
–65 to +150
GND/sOE
1F1
5
NOTE:
VCCQ/PE
VCCN
4Q1
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
1F0
7
SO28-9
VCCN
1Q0
8
4Q0
9
GND
3Q1
1Q1
10
11
12
13
14
GND
GND
2Q0
3Q0
CAPACITANCE (T = 25 C, f = 1MHz, V = 0V)
°
A
IN
VCCN
FB
Parameter
Description
Typ.
Max.
Unit
2Q1
CIN
Input Capacitance
4
6
pF
NOTE:
QSOP
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
TOP VIEW
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
Feedback Input
FB
IN
TEST (1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
GND/ sOE (1)
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used
as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
VCCQ/PE
nF[1:0]
FS
IN
3-level inputs for selecting 1 of 9 skew taps or frequency functions.
IN
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
nQ[1:0]
VCCN
VCCQ
GND
OUT
PWR
PWR
PWR
Three output banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
NOTE:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks.
Skew selections remain in effect unless nF[1:0] = LL.
PROGRAMMABLESKEW
Output skew with respect to the REF input is adjustable to compensate to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
for PCB trace delays, backplane propagation delays or to accommodate are used, they are intended for but not restricted to hard-wiring. Undriven
requirements for special timing relationships between clocked compo- 3-level inputs default to the MID level. Where programmable skew is
nents. Skew is selectable as a multiple of a time unit tU which is of the not a requirement, the control pins can be left open for the zero skew
order of a nanosecond (see PLL Programmable Skew Range and Resolution default setting. The Control Summary Table shows how to select specific
Table). There are nine skew configurations available for each output skew taps by using the nF1:0 control pins.
pair. These configurations are chosen by the nF1:0 control pins. In order
2
