IDT5V9352
3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER
INDUSTRIALTEMPERATURERANGE
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK
DRIVER ZERO DELAY BUFFER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCT 28, 2014
FEATURES:
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
dividecircuitryallowsforoutputfrequencyratiosof1:1, 2:1, 3:1, and3:2:1.
The output frequency relationship is controlled by the fSEL frequency
control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL
compatibleinputs
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V VCC
• Spread Spectrum Compatible
BecauseitisbasedonPLLcircuitry, the5V9352requiresastabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the PLL_EN to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package
• Use replacement part: 87952AYILF
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
preciselyalign, inbothfrequencyandphase. The5V9352operatesat2.5V
and 3.3V.
FUNCTIONALBLOCKDIAGRAM
BANK A
QA0
CCLK
1
1
0
1
0
6
4
2
2
REFCLK
FBIN
REF
FB
QA1
QA2
VCO
0
PLL
QA3
QA4
PLL_En
VCO_SEL
fSELA
BANK B
QB0
QB1
QB2
QB3
1
0
fSELB
fSELC
BANK C
1
QC0
QC1
0
MR/OE
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2013
1
c
2003 Integrated Device Technology, Inc.
DSC 5973/19
