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5V9910A-5SOGI

型号：

5V9910A-5SOGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

6 页

PDF大小：

93 K

下载PDF手册
3.3V LOW SKEW  
IDT5V9910A  
PLL CLOCK DRIVER  
TURBOCLOCK™ JR.  
FEATURES:  
DESCRIPTION:  
The IDT5V9910A is a high fanout phase locked-loop clock driver  
intendedforhighperformancecomputinganddata-communicationsappli-  
cations. Ithas eightzerodelayLVTTLoutputs.  
When the GND/sOE pin is held low, all the outputs are synchronously  
enabled.However,ifGND/sOE is heldhigh,allthe outputs exceptQ2 and  
Q3 are synchronouslydisabled.  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput. WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF.  
TheFBsignaliscomparedwiththeinputREFsignalatthephasedetector  
inordertodrive the VCO.Phase differences cause the VCOofthe PLLto  
adjust upwards or downwards accordingly.  
Aninternalloopfiltermoderates the response ofthe VCOtothe phase  
detector.Theloopfiltertransferfunctionhasbeenchosentoprovideminimal  
jitter(orfrequencyvariation)whilestillprovidingaccurateresponsestoinput  
frequencychanges.  
• Eight zero delay outputs  
• <250ps of output to output skew  
• Selectable positive or negative edge synchronization  
• Synchronous output enable  
• Output frequency: 15MHz to 85MHz  
• 3 skew grades:  
IDT5V9910A-2: tSKEW0<250ps  
IDT5V9910A-5: tSKEW0<500ps  
IDT5V9910A-7: tSKEW0<750ps  
• 3-level inputs for PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Available in SOIC package  
FUNCTIONALBLOCKDIAGRAM  
VCCQ/PE  
GND/sOE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
FB  
PLL  
REF  
FS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5847/1  
IDT5V9910A  
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Description  
Supply Voltage to Ground  
DC Input Voltage  
Max  
–0.5 to +7  
–0.5 to VCC+0.5  
–0.5 to +5.5  
530  
Unit  
V
VI  
V
REF  
VCCQ  
FS  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND  
TEST  
NC  
REF Input Voltage  
V
2
Maximum Power Dissipation (TA = 85°C)  
Storage Temperature  
mW  
° C  
3
TSTG  
–65 to +150  
NC  
4
GND/sOE  
VCCN  
Q7  
NOTE:  
5
V
CCQ/PE  
VCCN  
Q0  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute-  
maximum-rated conditions for extended periods may affect device reliability.  
6
Q6  
7
Q1  
8
GND  
Q5  
GND  
Q2  
9
10  
11  
12  
Q4  
Q3  
VCCN  
FB  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
V
CCN  
Parameter Description  
Typ. Max.  
Unit  
CIN  
NOTE:  
InputCapacitance  
5
7
pF  
SOIC  
TOP VIEW  
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not  
production tested.  
PINDESCRIPTION  
Pin Name  
Type  
Description  
REF  
IN  
ReferenceClockInput  
FeedbackInput  
FB  
IN  
TEST(1)  
GND/ sOE(1)  
IN  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the  
feedbacksignaltomaintainphaselock. SetGND/sOELOWfornormaloperation.  
VCCQ/PE  
FS(2)  
IN  
IN  
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthe  
referenceclock.  
Frequencyrangeselect:  
FS = GND: 15 to 35MHz  
FS = MID (or open): 25 to 60MHz  
FS = VCC: 40 to 85MHz  
Eightclockoutput  
Q0 - Q7  
VCCN  
OUT  
PWR  
PWR  
PWR  
Powersupplyforoutputbuffers  
Powersupplyforphaselockedloopandotherinternalcircuitry  
Ground  
VCCQ  
GND  
NOTES:  
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.  
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional  
lock time before all data sheet limits are achieved.  
2
IDT5V9910A  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.  
RECOMMENDEDOPERATINGRANGE  
IDT5V9910A-5,-7  
(Industrial)  
IDT5V9910A-2  
(Commercial)  
Symbol  
VCC  
Description  
Min.  
Max.  
Min.  
Max.  
3.6  
Unit  
V
Power Supply Voltage  
AmbientOperatingTemperature  
3
3.6  
3
0
TA  
-40  
+85  
+70  
° C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
—
Unit  
V
VIH  
Input HIGH Voltage  
2
—
VIL  
InputLOWVoltage  
0.8  
V
VIHH  
VIMM  
VILL  
IIN  
Input HIGH Voltage(1)  
InputMIDVoltage(1)  
InputLOWVoltage(1)  
InputLeakageCurrent  
(REF, FB Inputs Only)  
VCC−0.6  
VCC/2−0.3  
—
—
V
3-Level Inputs Only  
VCC/2+0.3  
0.6  
V
3-Level Inputs Only  
V
VIN = VCC or GND  
—
±5  
µ A  
VCC = Max.  
VIN = VCC  
HIGH Level  
MID Level  
LOW Level  
—
—
—
—
—
2.4  
—
±200  
±50  
I3  
3-Level Input DC Current (TEST, FS)  
VIN = VCC/2  
µ A  
VIN = GND  
±200  
±100  
±100  
—
IPU  
IPD  
Input Pull-Up Current (VCCQ/PE)  
Input Pull-Down Current (GND/sOE)  
OutputHIGHVoltage  
VCC = Max., VIN = GND  
VCC = Max., VIN = VCC  
VCC = Min., IOH = −12mA  
VCC = Min., IOL = 12mA  
µ A  
µ A  
V
VOH  
VOL  
OutputLOWVoltage  
0.55  
V
NOTE:  
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and  
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
POWERSUPPLYCHARACTERISTICS  
Symbol  
Parameter  
TestConditions(1)  
VCC = Max., TEST = MID, REF = LOW,  
GND/sOE = LOW, All outputs unloaded  
VCC = Max., VIN = 3V  
Typ.(2)  
Max.  
Unit  
ICCQ  
QuiescentPowerSupplyCurrent  
8
25  
mA  
∆ICC  
ICCD  
ITOT  
Power Supply Current per Input HIGH  
Dynamic Power Supply Current per Output  
TotalPowerSupplyCurrent  
1
30  
90  
—
—
—
µA  
VCC = Max., CL = 0pF  
55  
34  
42  
76  
µA/MHz  
VCC = 3.3V, FREF = 25MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 66MHz, CL = 160pF(1)  
mA  
NOTE:  
1. For eight outputs, each loaded with 20pF.  
3
IDT5V9910A  
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
INPUTTIMINGREQUIREMENTS  
Symbol  
tR,tF  
tPWC  
DH  
Description(1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
3
Max.  
10  
Unit  
ns/V  
ns  
—
90  
10  
%
REF  
Referenceclockinput  
15  
85  
MHz  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
IDT5V9910A-2  
IDT5V9910A-5  
IDT5V9910A-7  
Symbol Parameter  
Min.  
15  
Typ.  
—
—
—
—
—
0.1  
—
0
Max.  
35  
Min.  
15  
25  
40  
3
Typ.  
—
Max.  
35  
Min.  
Typ.  
—
—
—
—
—
0.3  
—
0
Max.  
Unit  
FS = LOW  
FS = MED  
FS = HIGH  
15  
25  
35  
60  
FREF  
REFFrequencyRange  
25  
60  
—
60  
MHz  
40  
85  
—
85  
40  
85  
(8)  
tRPWH  
tRPWL  
REF Pulse Width HIGH  
3
—
—
—
3
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ps  
(8)  
REF Pulse Width LOW  
3
—
3
—
—
3
—
(1,3,4)  
tSKEW0 ZeroOutputSkew(AllOutputs)  
—
0.25  
0.75  
0.25  
1.2  
1.2  
1.2  
0.5  
25  
—
—
0.25  
—
0.5  
1.25  
0.5  
1.2  
1.5  
1.5  
0.5  
25  
—
0.75  
1.65  
0.7  
1.2  
2.5  
2.5  
0.5  
25  
(1,2,5)  
tDEV  
tPD  
Device-to-Device Skew  
—
—
(1,7)  
(1)  
REFInputtoFBPropagationDelay  
−0.25  
−1.2  
0.15  
0.15  
—
−0.5  
−1.2  
0.15  
0.15  
—
0
0
−0.7  
−1.2  
0.15  
0.15  
—
tODCV  
Output Duty Cycle Variation from 50%  
OutputRiseTime(1)  
0
0
tORISE  
1
1
1.5  
1.5  
—
—
—
tOFALL OutputFallTime(1)  
1
1
tLOCK  
tJR  
PLLLockTime(1,6)  
Cycle-to-CycleOutputJitter(1)  
—
—
—
—
—
—
RMS  
—
—
—
Peak-to-Peak  
—
200  
—
200  
—
200  
NOTES:  
1. All timing and jitter tolerances apply for FNOM > 25MHz.  
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.  
3. tSKEW is the skew between all outlets. See AC TEST LOADS.  
4. For IDT5V9910A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.  
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is  
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.  
8. Refer to INPUT TIMING REQUIREMENTS for more detail.  
4
IDT5V9910A  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.  
AC TEST LOADS AND WAVEFORMS  
≤ 1ns  
≤ 1ns  
VCC  
3.0V  
2.0V  
Vth =1.5V  
0.8V  
150Ω  
0V  
Output  
LVTTL Input Test Waveform  
150Ω  
20pF  
tOFALL  
tORISE  
Test Load  
2.0V  
0.8V  
LVTTL Output Waveform  
AC TIMING DIAGRAM  
tREF  
tRPWH  
tRPWL  
REF  
tPD  
tODCV  
tODCV  
FB  
tJR  
Q
tSKEW  
tSKEW  
OTHER Q  
NOTES:  
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to VCC/2.  
tSKEW:  
The skew between all outputs.  
tDEV:  
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
tODCV: The deviation of the output from a 50% duty cycle.  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter  
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
5
IDT5V9910A  
3.3VLOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ORDERINGINFORMATION  
XX  
Package Process  
XXXXX  
IDT  
Device Type  
X
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
Blank  
I
Small Outline IC (300-mil)  
SO  
3.3V Low Skew PLL Clock Driver TurboClock Jr.  
5V9910A-2  
5V9910A-5  
5V9910A-7  
CORPORATE HEADQUARTERS  
for SALES:  
for Tech Support:  
2975StenderWay  
Santa Clara, CA 95054  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
logichelp@idt.com  
(408) 654-6459  
www.idt.com  
6
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