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5V993A-7QGI8

型号：

5V993A-7QGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

8 页

PDF大小：

111 K

下载PDF手册
3.3V PROGRAMMABLE  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™  
IDT5V993A  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V993Ais a highfanout3.3VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
theREFinputsignal.TheIDT5V993Ahassixprogrammableskewoutputs  
andtwozeroskewoutputs.Skewiscontrolledby3-levelinputsignalsthat  
may be hard-wired to appropriate HIGH-MID-LOW levels.  
• 3 pairs of programmable skew outputs  
• Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Output frequency: 3.75MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
Whenthe GND/sOE pinis heldlow,allthe outputs are synchronously  
enabled.However,ifGND/sOEisheldhigh,alltheoutputsexcept3Q0and  
3Q1 are synchronously disabled.  
• 3 skew grades:  
IDT5V993A-2: tSKEW0<250ps  
IDT5V993A-5: tSKEW0<500ps  
IDT5V993A-7: tSKEW0<750ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF. BothdeviceshaveLVTTLoutputswith12mAbalanceddriveoutputs.  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Available in QSOP package  
FUNCTIONALBLOCKDIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
3
1F1:0  
2F1:0  
3F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
4Q0  
4Q1  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5408/1  
IDT5V993A  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Description  
Supply Voltage to Ground  
DC Input Voltage  
Max  
–0.5 to +7  
–0.5 to VCC+0.5  
–0.5 to +5.5  
0.66  
Unit  
V
REF  
1
28  
27  
26  
25  
24  
23  
GND  
VI  
V
V
CCQ  
2
TEST  
REF Input Voltage  
V
2F  
1
FS  
3
4
5
6
Maximum Power Dissipation (TA = 85°C)  
Storage Temperature  
W
° C  
3F0  
3F  
2F0  
TSTG  
–65 to +150  
GND/sOE  
1F1  
1
VCCQ/PE  
NOTE:  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute-  
maximum-rated conditions for extended periods may affect device reliability.  
VCCN  
4Q1  
7
SO28-9  
22  
21  
1F0  
VCCN  
8
4Q0  
9
20  
19  
18  
17  
16  
15  
1Q  
1Q  
0
1
GND  
10  
3Q1  
11  
12  
13  
14  
GND  
GND  
3Q  
0
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
VCCN  
FB  
2Q  
2Q  
0
1
Parameter Description  
Typ. Max.  
Unit  
CIN  
NOTE:  
InputCapacitance  
4
6
pF  
QSOP  
TOP VIEW  
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not  
production tested.  
PINDESCRIPTION  
Pin Name  
Type  
Description  
REF  
IN  
ReferenceClockInput  
FeedbackInput  
FB  
IN  
TEST(1)  
IN  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control  
SummaryTable)remainineffect. SetLOWfornormaloperation.  
GND/ sOE(1)  
IN  
IN  
Synchronous OutputEnable. WhenHIGH, itstops clockoutputs (except3Q0 and3Q1)ina LOWstate -3Q0 and3Q1maybe usedas  
thefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandGND/sOEisHIGH,thenF[1:0]pinsactasoutputdisable  
controls for individual banks when nF[1:0]= LL. Set GND/sOE LOW for normal operation.  
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthe  
referenceclock.  
VCCQ/PE  
nF[1:0]  
FS  
IN  
3-levelinputsforselecting1of9skewtapsorfrequencyfunctions  
IN  
Selectsappropriateoscillatorcirciotbasedonanticipatedfrequencyrange. (SeePLLProgrammableSkewRange.)  
Threeoutputbanksoftwooutputswithprogrammableskew(1Q:3Q),and4Qoutputhasfixedzeroskewoutputs.  
Powersupplyforoutputbuffers  
nQ[1:0]  
VCCN  
VCCQ  
GND  
OUT  
PWR  
PWR  
PWR  
Powersupplyforphaselockedloopandotherinternalcircuitry  
Ground  
NOTE:  
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.  
PROGRAMMABLESKEW  
Output skew with respect to the REF input is adjustable to compensate to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)  
for PCB trace delays, backplane propagation delays or to accommodate are used, they are intended for but not restricted to hard-wiring. Undriven  
requirements for special timing relationships between clocked compo- 3-level inputs default to the MID level. Where programmable skew is  
nents. Skew is selectable as a multiple of a time unit tU which is of the not a requirement, the control pins can be left open for the zero skew  
order of a nanosecond (see PLL Programmable Skew Range and Resolution default setting. The Control Summary Table shows how to select specific  
Table). There are nine skew configurations available for each output skew taps by using the nF1:0 control pins.  
pair. These configurations are chosen by the nF1:0 control pins. In order  
2
IDT5V993A  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
EXTERNALFEEDBACK  
By providing external feedback, the IDT5V993A gives users flexibility  
An internal loop filter moderates the response of the VCO to the  
with regard to skew adjustment. The FB signal is compared with the phase detector. The loop filter transfer function has been chosen to  
input REF signal at the phase detector in order to drive the VCO. Phase provide minimal jitter (or frequency variation) while still providing accu-  
differences cause the VCO of the PLL to adjust upwards or downwards rate responses to input frequency changes.  
accordingly.  
PLLPROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE  
FS = LOW  
1/(44 x FNOM)  
15 to 35MHz  
FS = MID  
1/(26 x FNOM)  
25 to 60MHz  
FS = HIGH  
1/(16 x FNOM)  
40 to 85 MHz  
Comments  
TimingUnitCalculation(tU)  
VCOFrequencyRange(FNOM)(1,2)  
SkewAdjustmentRange(3)  
MaxAdjustment:  
±9.09ns  
±49°  
±9.23ns  
±83°  
±9.38ns  
±135°  
ns  
PhaseDegrees  
% of Cycle Time  
±14%  
tU =1.52ns  
tU =0.91ns  
tU =0.76ns  
—
±23%  
±37%  
—
Example 1, FNOM = 15MHz  
Example 2, FNOM = 25MHz  
Example 3, FNOM = 30MHz  
Example 4, FNOM = 40MHz  
Example 5, FNOM = 50MHz  
Example 6, FNOM = 80MHz  
—
tU =1.54ns  
tU =1.28ns  
tU =0.96ns  
tU =0.77ns  
—
—
—
tU =1.56ns  
tU =1.25ns  
tU =0.78ns  
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on  
input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the  
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected  
to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided  
output as the FB input.  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example  
if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range  
applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.  
CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS  
nF1:0  
Skew (Pair #1, #2)  
Skew (Pair #3)  
Divide by 2  
–6tU  
(1)  
LL  
–4tU  
–3tU  
LM  
LH  
–2tU  
–4tU  
ML  
–1tU  
–2tU  
MM  
MH  
HL  
ZeroSkew  
1tU  
ZeroSkew  
2tU  
2tU  
4tU  
HM  
HH  
3tU  
6tU  
4tU  
Divide by 4  
NOTE:  
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.  
3
IDT5V993A  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
RECOMMENDEDOPERATINGRANGE  
IDT5V993A-5,-7  
(Industrial)  
IDT5V993A-2  
(Commercial)  
Symbol  
VCC  
Description  
Min.  
Max.  
3.6  
Min.  
Max.  
3.6  
Unit  
V
Power Supply Voltage  
AmbientOperatingTemperature  
3
3
0
TA  
-40  
+85  
+70  
° C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
—
Unit  
V
VIH  
Input HIGH Voltage  
2
—
VIL  
InputLOWVoltage  
0.8  
V
VIHH  
VIMM  
VILL  
IIN  
Input HIGH Voltage(1)  
InputMIDVoltage(1)  
InputLOWVoltage(1)  
InputLeakageCurrent  
(REF, FB Inputs Only)  
VCC−0.6  
VCC/2−0.3  
—
—
V
3-Level Inputs Only  
VCC/2+0.3  
0.6  
V
3-Level Inputs Only  
V
VIN = VCC or GND  
—
±5  
µ A  
VCC = Max.  
VIN = VCC  
HIGH Level  
MID Level  
LOW Level  
—
—
—
—
—
2.4  
—
±200  
±50  
I3  
3-Level Input DC Current (TEST, FS)  
VIN = VCC/2  
µ A  
VIN = GND  
±200  
±100  
±100  
—
IPU  
IPD  
Input Pull-Up Current (VCCQ/PE)  
Input Pull-Down Current (GND/sOE)  
OutputHIGHVoltage  
VCC = Max., VIN = GND  
VCC = Max., VIN = VCC  
VCC = Min., IOH = −12mA  
VCC = Min., IOL = 12mA  
µ A  
µ A  
V
VOH  
VOL  
OutputLOWVoltage  
0.55  
V
NOTE:  
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and  
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
POWERSUPPLYCHARACTERISTICS  
Symbol  
Parameter  
TestConditions(1)  
VCC = Max., TEST = MID, REF = LOW,  
VCC/PE = LOW, GND/sOE = LOW,  
Alloutputsunloaded  
Typ.(2)  
Max.  
Unit  
ICCQ  
QuiescentPowerSupplyCurrent  
8
25  
mA  
∆ICC  
ICCD  
ITOT  
Power Supply Current per Input HIGH  
Dynamic Power Supply Current per Output  
TotalPowerSupplyCurrent  
VCC = Max., VIN = 3V  
1
30  
90  
—
—
—
µA  
VCC = Max., CL = 0pF  
55  
29  
42  
76  
µA/MHz  
VCC = 3.3V, FREF = 20MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 66MHz, CL = 160pF(1)  
mA  
NOTE:  
1. For eight outputs, each loaded with 20pF.  
4
IDT5V993A  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
INPUTTIMINGREQUIREMENTS  
Symbol  
tR,tF  
tPWC  
DH  
Description(1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
Max.  
10  
Unit  
ns/V  
ns  
3
—
90  
10  
%
REF  
ReferenceClockInput  
3.75  
85  
MHz  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
IDT5V993A-2  
IDT5V993A-5  
IDT5V993A-7  
Typ.  
Symbol Parameter  
Min.  
Typ.  
Max.  
Min.  
Typ.  
Max.  
Min.  
Max.  
Unit  
FNOM  
tRPWH  
tRPWL  
tU  
VCO Frequency Range  
SeePLLProgrammableSkewRangeandResolutionTable  
(11)  
REF Pulse Width HIGH  
3
3
—
—
—
—
3
3
—
—
—
—
3
3
—
—
—
—
ns  
ns  
(11)  
REF Pulse Width LOW  
ProgrammableSkewTimeUnit  
SeeControlSummaryTable  
(1,2,3)  
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)  
tSKEW0 ZeroOutputSkew(AllOutputs)(1,4)  
tSKEW1 OutputSkew  
—
—
—
0.05  
0.1  
0.2  
0.25  
0.5  
—
—
—
0.1  
0.25  
0.6  
0.25  
0.5  
—
—
—
0.1  
0.3  
0.6  
0.25  
0.75  
1
ns  
ns  
ns  
0.25  
0.7  
(Rise-Rise,Fall-Fall,SameClassOutputs)(1,6)  
tSKEW2 OutputSkew  
(Rise-Fall,Divided-Divided)  
tSKEW3 OutputSkew  
(Rise-Rise,Fall-Fall,DifferentClassOutputs)(1,6)  
tSKEW4 OutputSkew  
(Rise-Fall,Nominal-Divided)  
—
—
—
0.3  
0.25  
0.5  
1.2  
0.5  
0.9  
—
—
—
0.5  
0.5  
0.5  
1.2  
0.7  
1
—
—
—
1
1.5  
1.2  
1.7  
ns  
ns  
ns  
(1,6)  
0.7  
1.2  
(1,2)  
(1,2,7)  
tDEV  
tPD  
Device-to-Device Skew  
REFInputtoFBPropagationDelay  
Output Duty Cycle Variation from 50%  
—
−0.25  
−1.2  
—
—
0
0.75  
0.25  
1.2  
2
—
−0.5  
−1.2  
—
—
0
1.25  
0.5  
1.2  
2.5  
3
—
−0.7  
−1.2  
—
—
0
1.65  
0.7  
1.2  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ps  
(1,9)  
(1)  
(1,10)  
tODCV  
tPWH  
tPWL  
tORISE  
0
0
0
Output HIGH Time Deviation from 50%  
—
—
1
—
—
1
—
—
1.5  
1.5  
—
—
—
(1,11)  
OutputLOWTimeDeviationfrom50%  
OutputRiseTime(1)  
—
1.5  
1.2  
1.2  
0.5  
25  
—
—
3.5  
2.5  
2.5  
0.5  
25  
0.15  
0.15  
—
0.15  
0.15  
—
1.8  
1.8  
0.5  
25  
0.15  
0.15  
—
tOFALL OutputFallTime(1)  
1
1
tLOCK  
tJR  
PLLLockTime(1,8)  
—
—
—
—
—
—
Cycle-to-CycleOutputJitter(1)  
RMS  
—
—
—
Peak-to-Peak  
—
200  
—
200  
—
200  
NOTES:  
1. All timing and jitter tolerances apply for FNOM > 25MHz.  
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified  
load.  
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
4. tSKEW0 is the skew between outputs when they are selected for 0tU.  
5. For IDT5V993A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.  
6. There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).  
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is  
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.  
10. Measured at 2V.  
11. Measured at 0.8V.  
5
IDT5V993A  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
AC TEST LOADS AND WAVEFORMS  
VCC  
150Ω  
Output  
150Ω  
20pF  
t
t
OFALL  
ORISE  
2.0V  
tPWH  
0.8V  
tPWL  
LVTTL Output Waveform  
≤1ns  
≤ 1ns  
3.0V  
2.0V  
Vth = 1.5V  
0.8V  
0V  
LVTTL Input Test Waveform  
6
IDT5V993A  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
AC TIMING DIAGRAM  
tREF  
tRPWL  
RPWH  
t
REF  
FB  
Q
PD  
ODCV  
ODCV  
t
t
t
tJR  
SKEWPR  
t
SKEWPR  
t
SKEW0, 1  
t
tSKEW0, 1  
OTHER Q  
tSKEW3, 4  
SKEW3  
SKEW2  
tSKEW3  
t
t
REF DIVIDED BY 2  
SKEW1, 3, 4  
t
REF DIVIDED BY 4  
NOTES:  
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the  
negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.  
Skew:  
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated  
with 75Ω to VCC/2.  
tSKEWPR:  
tSKEW0:  
tDEV:  
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
The skew between outputs when they are selected for 0tU  
.
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.  
tODCV:  
tPWH is measured at 2V.  
tPWL is measured at 0.8V.  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
7
IDT5V993A  
3.3VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ORDERINGINFORMATION  
XXXXX  
XX  
X
IDT  
Package Process  
Device Type  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
Blank  
I
Q
Quarter-Size Small outline Package (SO28-9)  
3.3V Programmable Skew PLL Clock Driver TurboClock  
5V993A-2  
5V993A-5  
5V993A-7  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
for Tech Support:  
logichelp@idt.com  
(408) 654-6459  
www.idt.com  
8
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 		5V925BQGI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQGI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925QGI [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V925QGI8 [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V926APGGI [ TSSOP-16, Tube ] 6 页

IDT

 		5V926APGGI8 [ TSSOP-16, Reel ] 6 页

IDT

 		5V926APGI [ Clock Generator, 160MHz, PDSO16, TSSOP-16 ] 6 页

IDT

 		5V927PGGI8 [ TSSOP-16, Reel ] 6 页

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