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VTX1100

PacMON VTX1100

8+1-port HomePNA PACKET CONCENTRATOR

1 Features

§

8 1/10Mbps Serial ports direct interface with § Supports both Full/Half duplex ports

Home PNA PHY or 8 10/100Mbps RMII

ports

Ideal for MDU (Multiple Dwelling Unit)

application with Home PNA PHY

§

Full wirespeed layer 2 switching on all ports

Ability to support WinSock2.0 and

Windows98 & Windows2000 smart

applications

§

1 10/100Mbps auto-negotiating MII/serial § Transmit delay control capabilities

port (port 8) that can be used as uplink port

Up to 8 port-based VLANs can be configured

from EEPROM

•

Provides maximum delay guarantee

(<1ms)(Last bit in to first bit out)

Supports mixed voice-data networks

•

Internal 1k MAC address table

§

Support Concentrator mode

•

Auto address learning

Auto address aging

Ports 0 & 1 can be trunked to provide a

2x1/10Mbps link to another switch or server

Utilizes a single low-cost external SSRAM

for buffer memory

§

Leading edge QoS capabilities provided

based on 802.1p and IP TOS/DS field

§

•

2 queues per output port

Packet scheduling based on Weighted

Round-Robin (WRR)

Weighted Random Early Detection/Drop

(WRED) to drop packets during traffic

congestion

•

256k bytes or 512k bytes (1 chip)

§

External I²C EEPROM for power-up

configuration

Support external parallel port for

configuration updates

Optimized pin-out for easy board layout

Packaged in a 208 PQFP

•

§

•

2 levels of packet drop provided

System Block Diagram

10Mbps

Serial

Interface

S

R

A

M

10/100

MII

VTX1100

Switch Chip

1-Port MII 10/100

S

R

A

M

CPU

VTX1100

Switch Chip

1-Port MII 10/100

8-port 10MB Serial

8-port 10/100MB RMII

VTX1100

10/100

MII

10/100MB

RMII

Interface

To WAN

Port

1MB

Serial

Interface

10/100

RMII

PHY

10/100

RMII

PHY

Home

PNA

PHY

Home

PNA

PHY

64+1 Port Switch

MDU System

8+1 Port Switch

Line Card

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System Block Diagram

10/100

MII

S

R

A

10/100

MII

VTX1100

Switch Chip

1-Port MII 10/100

8-port 10MB Serial

VTX1100

Switch Chip

1-Port MII 10/100

8-port 10MB Serial

10/100

RMII

S

R

A

PAL

XF2080

M

XF2020

Routing Switch

4-16 10/100 Ports

or

Switch

24 10/100 Ports

+

10MB

Serial

Interface

10MB

Serial

Interface

2 G UPlinks

8-48 10MB ports

Home

PNA

PHY

Home

PNA

PHY

Home

PNA

PHY

Home

PNA

PHY

Line Card

High Port Density

MDU System

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2 Description

The Packet Monster (PacMON) VTX1100 is a fully integrated 8-port Ethernet packet concentrator

designed to support Home Networking. It is ideal for Multiple Dwelling Units (MDU) application.

PacMON VTX1100 provides features, normally not associated with plug-and-play technology,

without requiring an external processor to facilitate their utilization.

PacMON VTX1100 begin operating immediately at power-up, learning addresses automatically, and

forwarding packets at full wire-speed to any of its eight output ports or the uplink expansion port. At

power-up, VTX1100 configures itself from the EEPROM, and can then provide port trunking, port-

based VLANs, and Quality of Service (QoS) capabilities, usually associated only with managed

switches.

The proprietary built-in intelligence of the VTX1100 allows it to recognize and offer packet

prioritization QoS. Packets are prioritized based on their layer 2 VLAN priority tag or layer 3 Type-

Of-Service/ Differentiated Services (TOS/DS) field. This priority can be defined as transmit and/or

drop priority.

The PacMON VTX1100 can be used to create an 8-port unmanaged switch with one WAN router port

by adding a CPU (ARM or MPC 850) connected to the additional MII port (port 8). The only external

components needed for a low cost MDU system are the Home PNA physical layer transceivers and a

single SSRAM per VTX1100.

Operating at 50Mhz internally, and with a 50Mhz interface to the external SSRAM, the VTX1100

sustains full wire-speed switching on all nine ports. When the system supports 8 ports of 1M Home

PNA PHY with the 10M Serial uplink, the system clock can be operated to 20Mhz and still achieve

full wire speed switching on all nine ports.

The chip is packaged in a small 208 pin Plastic Quad Flat-Pak (PQFP) package.

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3 PacMON VTX1100 Block Diagram

I ²C Interface

Registers

Mgmt

Xface

MDIO

Xface

Switch

Control

Memory

1k

Search Engine

SRAM

SSRAM

Frame Engine

Frame

32

Memory

Buffer

Interface

Memory

Eight

1/10 Serial

or

Expansion

Port MAC

10/100 RMII

MACs

7 wire Serial

interface

MII/Serial Port

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4 Functional Operation

The PacMON VTX1100 was designed to provide a cost-effective layer 2 switching solution, using

technology from the XF2080 family to offer a highly integrated product for the unmanaged, DiffServ

ready, Ethernet switching market.

Eight 1/10 Media Access Controllers (MAC) provide the protocol interface into the VTX1100. These

MACs perform the required packet checks to ensure that each packet provided to the Frame Engine

meets all the IEEE 802.1 standards. Data packets longer than 1518 (1522 with VLAN tag) bytes

and shorter than 64 bytes are dropped, and VTX1100 has been designed to support minimum inter-

frame gaps between incoming packets.

The Frame Engine (FE) is the primary packet buffering and forwarding engine within the VTX1100.

As such, the FE controls the storage of packets in and out of the external frame buffer memory,

keeps track of frame buffer availability, and schedules output packet transmissions. While packet

data is being buffered, the FE extracts the necessary information from each packet header and sends

it to the Search Engine for processing. Search results returned to the FE ensue the scheduling of

packet transmission and prioritization. When a packet is chosen for transmission, the FE reads the

packet from external buffer memory and places it in the output FIFO of the output port.

5 Address Learning and Aging

The PacMON VTX1100 is able to begin address learning and packet forwarding shortly after power-

up has been completed. The Search Engine examines the contents of its internal Switch Database

Memory for each valid packet received on an input port.

Unknown source and destination MAC addresses are detected when the Search Engine does not find

a match within its database. These unknown source MAC addresses are learned by creating a new

entry in the switch database memory, and storing the necessary resulting information in that

location. Subsequent searches to a learned destination MAC address will return the new contents of

that MAC Control Table (MCT) entry.

After each source address search the MCT entry aging flag is updated. MCT entries that have not

been accessed during a user configurable time period (2 to 67,108 seconds) will be removed. This

aging time period can be configured using the 16-bit value stored in the registers MAC Address

Aging Time Low and High (MATL[7:0], MATH[7:0]). The aging period is defined by the following

equation:

{MATH[7:0]&MATL[7:0]} x 1024ms = Tage

The aging of all MCT entries is checked once during each time period. If the MCT entry has not been

utilized before the end of the next time period, it will be deleted.

Note that when the system clock operates at 20Mhz, the aging period will be increased, compared

with 50Mhz of system clock. One should adjust the MATH and MATHL content variable accordingly.

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6 Quality of Service

The PacMON VTX1100 utilizes Vertex Networks’ CoSMOS architecture that provides a new level of

Quality of Service (QoS) capability to unmanaged switch applications. Similar in operation to the

QoS capabilities of the XF2080 chipset members, VTX1100 provides two transmit queues per output

port.

The Frame Engine manages the output transmission queues for all the VTX1100 ports. Once the

destination address search is complete, and the switch decision is passed back to the FE, the packet

is inserted into the appropriate output queue. The packet entry into the high or low priority queue is

controlled by either the VLAN tag information or the Type of Service/Differentiated Service

(TOS/DS) field in the IP header. Either of these priority fields can be used to select the transmission

priority, and the mapping of the priority field values into either the high or low priority queue can be

configured using the VTX1100 configuration registers.

If the system uses the TOS/DS field to prioritize packets, there are two choices regarding which bits

of the TOS/DS field are used. Bits [0:2] of the TOS byte (known as the IP precedence field) or bits

[3:5] of the TOS byte (known as the DRT field) can be used to map the transmission queue priority.

Either bits, [0:2] or [3:5], can also be used as a packet drop precedence, by using bits 6 and 7 of the

FCB Buffer Low Threshold register (FCBST).

VTX1100 utilizes Weighted Round Robin (WRR) and Weighted Random Early Detection/Drop

(WRED) to schedule packets for transmission. To enable VTX1100’s QoS capabilities requires the

use of an external EEPROM to change the default register configurations and turn on QoS.

Weighted Round Robin is an efficient method to ensure that each of the transmission queues gets at

least a minimum service level. With two output transmission queues, VTX1100 will transmit “X”

packets from the high priority queue before transmitting “Y” packets from the low priority queue.

VTX1100 allows the designer to set the high priority weight to a value between 0 and 16. The low

priority weight is fixed at the value 1. If the high priority weight is set to the value 4, then it will

transmit 4 high priority packets before transmitting each low priority packet.

VTX1100 also uses a proprietary mechanism to ensure the timely delivery of high priority packets.

When the latency of high priority packets reaches a threshold, it will override the WRR weights and

transmit only high priority packets until the high priority packet delays are below the threshold.

This threshold limit is set at less than 1ms (last bit in and first bit out).

The QoS capabilities of the VTX1100 are enabled by loading the appropriate values into the

configuration registers. QoS for packet transmission is enabled by performing the following four

steps:

1. Select the TOS/DS or VLAN Priority Tag field as the control for IP packet transmission.

The selection is made using bit 7 of the Flooding Control (FCR[7]) register.

-

FCR[7]=0, use VLAN Priority Tag field to map the transmission priority if this Tag

field exists.

-

FCR[7]=1, use TOS/DS field for IP packet transmission priority mapping.

2. Select which TOS/DS field to use as the control for packet transmission priority if the

TOS/DS field was selected in step 1. The selection is made using bit 6 of the FCB Buffer

Low Threshold (FCBST[6]) register.

-

FCBST[6]=0, use DTR subfield to map the transmission priority.

FCBST[6]=1, use IP precedence subfield¹to map the transmission priority.

¹IP precedence and DTR subfields are referred to as TOS/DS[0:2] and TOS/DS[3:5] in the IP TOS/DS

byte.

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3. Set the transmission queue weight for the high priority queue in the Transmission

Scheduling Control (AXSC[3:0]) register.

4. Set the priority mappings from the TOS/DS or VLAN Priority Tag field to the high or low

priority output queue. The selection is made using the VLAN Priority Map (AVPM) and

TOS Priority Map (TOSPML) registers.

Note that, for half duplex operation, the priority queues²must be enabled using bit 7 in the

Transmission Scheduling Control (AXSC[7]) register to utilize the QoS function.

When QoS is enabled, VTX1100 will utilize WRR to schedule packet transmission, and will use

Weighted Random Early Detection/Drop (WRED) to drop random packets in order to handle buffer

memory congestion. In this method, only certain packet flows are slowed down while the remaining

see no impact from the network traffic congestion.

Weighted Random Early Detection/Drop (WRED) is a method of handling traffic congestion in the

absence of flow control mechanisms. When flow control is enabled, all devices that are connected to

a switch node that is exercising flow control are effectively unable to transmit, including nodes that

are not directly responsible for the congestion problem. This inability to transmit during flow control

periods would play havoc with voice packets, or other high priority packet flows, and therefore flow

control is not recommended for networks that mix voice and data traffic.

WRED allows traffic to continue flowing into ports on a switch, and randomly drops packets with

different probabilities based upon each packet’s priority markings. As the switch congestion

increases, the probability of dropping an input packet increases, and as congestion decreases, the

probability of dropping an input packet decreases. In this manner, only traffic flows that have had

packets dropped will be affected by the congestion. Other traffic flows will see no effect.

The following table summarizes the WRED operation of the VTX1100. It lists the buffer thresholds

at which each drop probability takes effect.

WRED Threshold

Hi Priority Low Priority

Level 0 total buffer space available is < LPBT buffer

Drop Percentage

Hi Drop Priority Low Drop Priority

50%

75%

100%

0%

25%

50%

Level 1

Level 2

24 buffers

None

72 buffers

84 buffers

The WRED packet drop capabilities of COSMOS 2 are enabled by performing the following three

steps:

1. Select the TOS/DS or VLAN Tag field as the control for packet dropping. The selection is

made using bit 7 of the Flooding Control (FCR[7]) register.

-

FCR[7]=0, use VLAN Priority Tag field to map the drop priority if this Tag field

exists.

-

FCR[7]=1, use ToS/DS field for IP packet transmission priority mapping.

2. Select which TOS/DS Tag field to use for packet dropping provided that the TOS/DS field

was selected in step 1. The selection is made using bit 7 of the FCB Buffer Low

Threshold (FCBST[7]) register.

-

FCBST[7]=0, use DTR subfield to map the drop priority.

FCBST[7]=1, use IP precedence subfield to map the drop priority.

3. Set the drop mappings from the TOS/DS or VLAN Tag field to the high or low drop

priority output flag. The selection is made using the VLAN Drop Map (AVDM) and TOS

Discard Map (TOSDML) registers.

²In Half Duplex mode, the QoS functions are disabled by default.

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Note that to utilize the QoS function of the VTX1100, flow control has to be disabled.

7 Buffer Management

VTX1100 stores each input packet into the external frame buffer memory while determining the

destination the packet is to be forwarded to. The total number of packets that can be stored in the

frame buffer memory depends upon the size of the external SSRAM that is utilized. For a 256k byte

SSRAM VTX1100 can buffer 170 packets. For a 512K byte SSRAM VTX1100 can buffer 340 packets.

In order to provide good Quality of Service characteristics, VTX1100 must allocate the available

buffer space to low and high priority unicast and multicast traffic. This can be accomplished using

the external EEPROM to load the appropriate values into VTX1100 configuration registers. To

allow the designer to set the minimum number of buffers provided for low drop priority unicast

traffic, use the Low Drop Priority Buffer Threshold (LPBT[7:0]) register. To set the maximum

number of buffers allocated for all multicast packets, use the Multicast Buffer Control (MBCR[7:0])

register.

During operation VTX1100 will continuously monitor the amount of frame buffer memory that is

available, and when the unused buffer space falls below a designer configurable threshold, VTX1100

will begin to drop incoming packets (WRED). This threshold is set using the FCB Buffer Low

Threshold (FCBST[5:0]) register.

8 Virtual LANs

VTX1100 provides the designer the ability to define a single port-based Virtual LAN (VLAN) for each

of the eight ports. This VLAN is individually defined for each port using the Port Control Registers

(ECR1Px[6:4]). Bits [6:4] allow the designer to define a VLAN ID (value between 0 – 7) for each port.

When packets arrive at an input of VTX1100, the search engine will determine the VLAN ID for that

port, and then determine which of the other ports also are members of that VLAN by matching their

assigned VLAN Id values. The packet will then be transmitted to each port with the same VLAN ID

as the source port.

9 Concentration Mode

VTX1100 supports a Concentration Mode, where each of the 0-7 port is only allowed to directly

communicate with the uplink port 8. This mode ensures that data from any of ports 0-7 cannot be

directly seen by any other port. This feature is used in MDU applications to provide data privacy to

subscribers.

To use this mode, a CONC (concentration) bit in each ECR1 register of ports 0-8 must be enabled,

i.e., ECR1 [7]=1, and ports 0-7 must each be set on a separate VLAN. Note that, in concentration

mode, the VLAN of port 8 will be ignored.

A more flexible concentration mode can be set up. For this mode, ports 0 –7 are partitioned into

several groups, sharing the same VLAN ID. This will allow traffic within the same group to freely

communicate with each other, while continuing to communicate outside the group in concentration

mode.

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10 Port Trunking

Port trunking allows the designer to configure the VTX1100, such that ports 0 and 1 are defined as a

logical port. This provides a 20Mb/s link to a switch or server using two 10Mb/s ports in parallel.

Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the

source MAC address of all packets received from the trunk are checked against the MCT database to

ensure that they have a port ID of 0 or 1. Packets that have a port ID other than 0 and 1 will effect

the VTX1100 to learn the new MAC address for this port change.

On transmission, the selected trunk port is determined by hashing the source and destination MAC

addresses. This provides a one-to-one mapping between the trunk port and the MAC addresses.

Subsequent packets with the same MAC addresses will always utilize the same trunk port.

VTX1100 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, via

the ports link signal, VTX1100 will switch all traffic destined to the failed port over to the remaining

port in the trunk. Thus maintaining the trunk link, albeit at a lower effective bandwidth.

11 Port Mirroring

The port mirroring function is only supported in RMII mode. Using the 4 port mirroring control pins

provides the ability to enable or disable port mirroring, select which of the remaining 7 ports is to be

mirrored, and whether the received or transmitted data is being mirrored. The control for this

function is shown in the following table.

Mirrored Port

Port 0 RCV

Port 0 XMT

Port 1 RCV

Port 1 XMT

Port 2 RCV

Port 2 XMT

Port 3 RCV

Port 3 XMT

Port 4 RCV

Port 4 XMT

Port 5 RCV

Port 5 XMT

Port 6 RCV

Port 6 XMT

Disabled

Mirror_Control [3]

Mirror_Control [2]

Mirror_Control [1]

Mirror_Control [0]

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0/1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

When enabled, port mirroring will allow the user to monitor traffic going through the switch on

output Port 7. If the port mirroring control pins, Mirror_Control[3:0], are left floating, VTX1100 will

operate with the port mirroring function disabled. When port mirroring is enabled, the user must

configure Port 7 to operate in the same mode as the port it is mirroring (autoneg, duplex, speed, flow

control).

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12 Power Saving Mode in MAC

The power saving mode is activated only in RMII mode. VTX1100 was designed to be power efficient.

When the internal RMII MAC sections detect that the external port in not receiving or transmitting

packets, it will shut down and conserve power. When new packet data is loaded into the output

transmit FIFO of a MAC in power saving mode, the MAC will return to life and begin operating

immediately.

When the MAC is in power saving mode and new packet data is received on the RMII interface, the

MAC will return to life and receive data normally into the receive FIFO. This wake up occurs when

the MAC sees the CRS_DV signal asserted.

Using this method, the switch will turn off all MAC sections during periods when there is no network

activity (at night for example), and save power. For large networks this power savings can be

significant. To achieve the maximum power efficiency, the designer should use a physical layer

transceiver that utilizes “Wake-On-LAN” technology.

13 EEPROM I²C Interface

A simple 2 wire serial interface is provided to allow the configuration of the VTX1100 via an external

EEPROM. VTX1100 utilizes a 1K bit EEPROM with an I²C interface.

14 Management Interface

VTX1100 uses a standard parallel port interface to provide external CPU access to the internal

registers. This parallel interface consists of 3 pins: DATA0; STROBE; and ACK. The DATA0 pin

provides the address and data content input to VTX1100, while the ACK pin provides the

corresponding output to the external CPU. The STROBE pin is provided as the clock for both serial

data streams. Any of its internal registers can be modified through this parallel port interface.

Write Command

STROBE-

2 Extra clocks after last

transfer

DATA

A2 A3

A6

D0 D1 D2 D3 D4 D5 D6 D7

DATA

A0 A1

START

A4 A5

W

ADDRESS

COMMAND

Read Command

STROBE-

DATA

R

A0 A1

A5 A6

A2 A3 A4

ADDRESS

START

COMMAND

D0 D1

DATA

D4

D7

D5 D6

ACK-

D2 D3

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Each management interface transfer consists of four parts:

1. A START pulse – occurs when DATA is sampled high when STROBE is rising

followed by

DATA being sampled low when STROBE falls.

2. Register Address strobed into DATA0 pin by the high level of the STROBE pin.

3. Either a Read or Write Command (see waveforms above).

4. Data to be written provided on DATA0, or data to be read back provided on ACK.

Any command can be aborted in the middle by sending an ABORT pulse to VTX1100. An ABORT

pulse occurs when DATA is sampled low and STROBE is rising, then DATA is sampled high when

STROBE falls.

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15 Configuration Register Definitions

VTX1100 registers can be accessed via the parallel interface and/or the I²C interface. Some registers

are only accessible through the parallel interface. The access method for each register is listed in the

individual register definitions. Each register is 8-bit wide.

15.1 GCR - GLOBAL CONTROL REGISTER

§

Access: parallel interface, Write Only

Address: h30

Bit [0]

Bit [1]

Bit [2]

Bit [3]

Store configuration

Store configuration and reset

Start BIST

(Default = 0)

Reset system

15.2 DCR0 - DEVICE STATUS AND SIGNATURE REGISTER

§

Access: parallel interface, Read Only

Address: h31

Bit 0

Busy writing configuration from I2C

Bit 1

Busy reading configuration from I2C

BIST in progress

RAM Error

Bit 2

Bit 3

Bit [5:4]

Bit [7:6]

Reserved

Revision

15.3 DA – DA REGISTER

§

Access: parallel interface, Read Only

Address: h36

Always returns 8-bit value hDA. Indicates

the parallel port connection is good.

(Default DA)

15.4 MBCR – MULTICAST BUFFER CONTROL REGISTER (ADDRESS H00)

§

Access: parallel interface and I²C, Read/Write

Address: h00

Bit [7:0]

MAX_CNT_LMT

Maximum Number of Multicast

Frames allowed

(Default = 1F)

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15.5 FCBST – FCB BUFFER LOW THRESHOLD

§

Access: parallel interface and I²C, Read/Write

Address: h01

Bit [5:0]

BUF_LOW_TH

Buffer Low Threshold – number of

FCB left before triggering WRED.

Use IP precedence field (TOS[0:2]) for

Priority

Use IP precedence field (TOS[0:2]) for

Drop

(Default = 1F)

(Default = 0)

Bit 6

Bit 7

Note that, for Bit 6 and 7, Default=0 means to use DTR filed (TOS[3:5])

15.6 LPBT – LOW DROP PRIORITY BUFFER THRESHOLD

§

Access: parallel interface and I²C, Read/Write

Address: h02

Bit [7:0]:

LOW_PRI_CNT:

Number of frame buffers

(Default 3F)

reserved for low dropping traffic.

15.7 FCR – FLOODING CONTROL REGISTER

Access: parallel interface and I²C, Read/Write

Address: h03

Bit [3:0]

Bit [6:4]

U2MR

Unicast to Multicast Rate

(Default = 8)

(Default = 000)

TimeBase: 000 = 100us

001 = 200us

011 = 800us

101 = 3.2ms

111 = 100us

010 = 400us

100 = 1.6ms

110 = 6.4ms

Bit [7]

USE_TOS

Pick TOS over VLAN Priority for

IP Packet.

(Default = 0)

(Default 00)

15.8 AVTCL – VLAN TYPE CODE REGISTER LOW

§

Access: parallel interface and I²C, Read/Write

Address: h04

Bit [7:0]

VLANType_LOW

Lower 8 bits of VLAN type code.

15.9 AVTCH – VLAN TYPE CODE REGISTER HIGH

§

Access: parallel interface and I²C, Read/Write

Address: h05

Bit [7:0]

VLANType_HIGH

Upper 8 bits of the VLAN type code (Default 81)

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15.10 AVPM – VLAN PRIORITY MAP

§

Access: parallel interface and I²C, Read/Write

Address: h06

Map VLAN tag into 2 transmit queues. (0 = low priority, 1 = high priority)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Mapped priority of tag value 0

Mapped priority of tag value 1

Mapped priority of tag value 2

Mapped priority of tag value 3

Mapped priority of tag value 4

Mapped priority of tag value 5

Mapped priority of tag value 6

Mapped priority of tag value 7

(Default 0)

15.11 AVDM – VLAN DISCARD MAP

§

Access: parallel interface and I²C, Read/Write

Address: h07

Map VLAN tag into frame discard when low priority buffer usage is above threshold

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Frame discard for tag value 0

Frame discard for tag value 1

Frame discard for tag value 2

Frame discard for tag value 3

Frame discard for tag value 4

Frame discard for tag value 5

Frame discard for tag value 6

Frame discard for tag value 7

(Default 0)

15.12 TOSPML – TOS/DS PRIORITY MAP LOW

§

Access: parallel interface and I²C, Read/Write

Address: h08

Map TOS field in IP packet into 2 transmit queues (0 = low priority, 1 = high priority)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Mapped priority when TOS is 0

Mapped priority when TOS is 1³

Mapped priority when TOS is 2

Mapped priority when TOS is 3

Mapped priority when TOS is 4

Mapped priority when TOS is 5

Mapped priority when TOS is 6

Mapped priority when TOS is 7

(Default 0)

³TOS=1 means TOS[0:2]=”001’

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15.13 TOSDML – TOS/DS DISCARD MAP

§

Access: parallel interface and I²C, Read/Write

Address: h0A

Map TOS into frame discard when low priority buffer usage is above threshold

Bit 0

Bit1

Frame discard when TOS is 0

Frame discard when TOS is 1

Frame discard when TOS is 2

Frame discard when TOS is 3

Frame discard when TOS is 4

Frame discard when TOS is 5

Frame discard when TOS is 6

Frame discard when TOS is 7

(Default 0)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

15.14 AXSC – TRANSMISSION SCHEDULING CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h0B

Bit [3:0]:

Transmission Queue Service Weight (Default F)

for high priority queue.

Bit [4]

Bit [5]

Bit [6]:

Reserved

Global Flow Control

(Default 0,

enable)

Bit [7]:

Half Duplex Priority Enable

(Default 0)

15.15 MII_OP0 – MII REGISTER OPTION 0

§

Access by parallel interface and I²C, Read/Write

Address: h0C

To provide a non-standard address for the Phy Status Register. When low and

high Address bytes are 0, VTX1100 will use the standard address.

Bit [7:0]

Low order address byte

(Default 00)

(Default 25)

15.16 MII_OP1 – MII REGISTER OPTION 1

§

Access: parallel interface and I²C, Read/Write

Address: h0D

Bit [7:0]

High order address byte

§

15.17 AGETIME_LOW – MAC ADDRESS AGING TIMER LOW

§

Access: parallel interface and I²C, Read/Write

Address: h0E

Bit [7:0]

Low byte of the MAC address aging

timer.

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15.18 AGETIME_HIGH – MAC ADDRESS AGING TIMER HIGH

§

Access: parallel interface and I²C, Read/Write

Address: h0F

Bit [7:0]

High byte of the MAC address aging (Default 01)

timer.

The aging time is based on the

following equation:

The default

setting provides

{AGETIME_TIME,AGETIME_LOW} a 300 second

X 1024ms

aging time at

SCLK=50Mhz .

15.19 ECR1P0 – PORT 0 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h10

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

15.20 ECR1P1 – PORT 1 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h11

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

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15.21 ECR1P2 – PORT 2 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h12

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

15.22 ECR1P3 – PORT 3 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h13

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

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15.23 ECR1P4 – PORT 4 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h14

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

15.24 ECR1P5 – PORT 5 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h15

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

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15.25 ECR1P6 – PORT 6 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h16

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

15.26 ECR1P7 – PORT 7 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h17

Bit [3:0]

RMII Port Mode

Only for RMII mode,

Serial Mode DON’T CARE

1 – Flow Control Off

(Default 0000)

Bit [0]

0 – Flow Control On

Bit [1]

Bit [2]

Bit [3]

1 – Half Duplex

0 – Full Duplex

1 – 10Mbps

0 – 100Mbps

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

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15.27 ECR1P8 – PORT 8 CONTROL REGISTER

§

Access: parallel interface and I²C, Read/Write

Address: h18

Bit [3:0]

Bit [3]

Port Mode

(Default 0000)

1 – Force configuration based on Bit[2:0]

0 – Auto and advertise based on Bit[2:0]

Bit [2]

Bit [1]

Bit [0]

1 – 10Mbps

0 – 100Mbps

1 – Half Duplex

0 – Full Duplex

1 – Flow Control Off

0 – Flow Control On

Bit [6:4]

Bit [7]

PVID

CONC:

Port based VLAN ID

Enable Concentration Mode

(Default 000)

(Default 0)

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16 VTX1100 Pin Descriptions

Note:

#

I

Active low signal

Input signal

S

O

Input signal with Schmitt-Trigger

Output signal

OD

I/O

SL

D

Open-Drain driver

Input & Output signal

Slew Rate Controlled

Pulldown

U

Pullup

5

5V Tolerance

Pin No(s).

Symbol

Type

Name & Functions

Databus to Frame Buffer Memory

Frame Buffer Memory Interface

201,200,199,197,196, L_D[31:0]

195,193,192,191,190,

188,187,186,185,183,

182,181,179,178,177,

176,174,173,172,170,

169,168,167,165,164,

163,161

I/O, U, SL

203, 151,158,160,

L_A[18:2]

I/O, U, SL

Address pins for buffer memory

10,9,8,6,5,4,2,1,208,

206,205,204, 150,

153

155

156

157

L_CLK

L_WE#

L_OE#

O

Frame Buffer Memory Clock

O, SL

O

Frame Buffer Memory Write Enable

Frame Buffer Memory Output Enable

L_ADSC#

O, SL

MII Management Interface

120

122

M_MDC

M_MDIO

O

MII Management Data Clock

MII Management Data I/O

I/O, U

I2C Interface (Serial EEPROM Interface)

123

124

SCL

SDA

O, U, 5

I2C Data Clock

I/O, U, OD, 5 I2C Data I/O

Parallel Port Management Interface

127

128

129

STROBE

DATA0

ACK

I, U, S, 5

I, U, 5

Data Pin

O, U, OD, 5

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Pin No(s).

Symbol

Type

Name & Functions

Port 0 Serial Interface

23

M0_RXD

I, U

I, D

O

Port 0 Receive Data

Port 0 Receive Clock

24

M0_RXCLK

M0_CRS_DV

M0_TXD

22

Port 0 Carrier Sense and Data Valid

Port 0 Transmit Data

20

21

M0_TXCLK

M0_TXEN

M0_CLS

I

Port 0 Transmit Clock

19

O

Port 0 Transmit Enable

12

I, U

I,U

I, U

Port 0 Collision Detection

Port 0 Link Status

13

M0_LINK

14

M0_DUPLEX

Port 0 Full-Duplex Select (half-duplex = 0)

Port 1 Serial Interface

30

M1_RXD

I, U

I, D

O

Port 1 Receive Data

31

M1_RXCLK

M1_CRS_DV

M1_TXD

Port 1 Receive Clock

29

Port 1 Carrier Sense and Data Valid

Port 1 Transmit Data

27

28

M1_TXCLK

M1_TXEN

M1_CLS

I

Port 1 Transmit Clock

26

O

Port 1 Transmit Enable

Port 1 Collision Detection

Port 1 Link Status

15

I, U

16

M1_LINK

M1_DUPLEX

17

Port 0 Full-Duplex Select (half-duplex = 0)

Port 2 Serial Interface

37

M2_RXD

I, U

I, D

O

Port 2 Receive Data

38

M2_RXCLK

M2_CRS_DV

M2_TXD

Port 2 Receive Clock

36

Port 2 Carrier Sense and Data Valid

Port 2 Transmit Data

34

35

M2_TXCLK

M2_TXEN

M2_CLS

I

Port 2 Transmit Clock

33

O

Port 2 Transmit Enable

Port 2 Collision Detection

Port 2 Link Status

47

I, U

48

M2_LINK

M2_DUPLEX

49

Port 2 Full-Duplex Select (half-duplex = 0)

Port 3 Serial Interface

44

45

43

41

42

40

50

51

52

M3_RXD

I, U

I, D

O

Port 3 Receive Data

M3_RXCLK

M3_CRS_DV

M3_TXD

Port 3 Receive Clock

Port 3 Carrier Sense and Data Valid

Port 3 Transmit Data

M3_TXCLK

M3_TXEN

M3_CLS

I

Port 3 Transmit Clock

O

Port 3 Transmit Enable

Port 3 Collision Detection

Port 3 Link Status

I, U

M3_LINK

M3_DUPLEX

Port 3 Full-Duplex Select (half-duplex = 0)

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Pin No(s).

Symbol

M4_RXD

Type

Name & Functions

Port 4 Serial Interface

64

I, U

I, D

O

Port 4 Receive Data

Port 4 Receive Clock

65

M4_RXCLK

M4_CRS_DV

M4_TXD

63

Port 4 Carrier Sense and Data Valid

Port 4 Transmit Data

61

62

M4_TXCLK

M4_TXEN

M4_CLS

I

Port 4 Transmit Clock

60

O

Port 4 Transmit Enable

53

I, U

Port 4 Collision Detection

Port 4 Link Status

54

M4_LINK

55

M4_DUPLEX

Port 4 Full-Duplex Select (half-duplex = 0)

Port 5 Serial Interface

71

M5_RXD

I, U

I, D

O

Port 5 Receive Data

72

M5_RXCLK

M5_CRS_DV

M5_TXD

Port 5 Receive Clock

70

Port 5 Carrier Sense and Data Valid

Port 5 Transmit Data

68

69

M5_TXCLK

M5_TXEN

M5_CLS

I

Port 5 Transmit Clock

67

O

Port 5 Transmit Enable

Port 5 Collision Detection

Port 5 Link Status

56

I, U

57

M5_LINK

M5_DUPLEX

58

Port 5 Full-Duplex Select (half-duplex = 0)

Port 6 Serial Interface

78

M6_RXD

I, U

I, D

O

Port 6 Receive Data

79

M6_RXCLK

M6_CRS_DV

M6_TXD

Port 6 Receive Clock

77

Port 6 Carrier Sense and Data Valid

Port 6 Transmit Data

75

76

M6_TXCLK

M6_TXEN

M6_CLS

I

Port 6 Transmit Clock

74

O

Port 6 Transmit Enable

Port 6 Collision Detection

Port 6 Link Status

88

I, U

89

M6_LINK

M6_DUPLEX

90

Port 6 Full-Duplex Select (half-duplex = 0)

Port 7 Serial Interface

85

86

84

82

83

81

91

92

93

M7_RXD

I, U

I, D

O

Port 7 Receive Data

M7_RXCLK

M7_CRS_DV

M7_TXD

Port 7 Receive Clock

Port 7 Carrier Sense and Data Valid

Port 7 Transmit Data

M7_TXCLK

M7_TXEN

M7_CLS

I

Port 7 Transmit Clock

O

Port 7 Transmit Enable

Port 7 Collision Detection

Port 7 Link Status

I, U

M7_LINK

M7_DUPLEX

Port 7 Full-Duplex Select (half-duplex = 0)

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Pin No(s).

Symbol

Type

Name & Functions

Port 0 RMII Interface

24,23

M0_RXD[1:0]

M0_CRS_DV

M0_TXD[1:0]

M0_TXEN

I, U

I, D

O

Port 0 Receive Data

22

Port 0 Carrier Sense and Data Valid

Port 0 Transmit Data

21,20

19

O

Port 0 Transmit Enable

Port 1 RMII Interface

31,30

M1_RXD[1:0]

M1_CRS_DV

M1_TXD[1:0]

M1_TXEN

I, U

I, D

O

Port 1 Receive Data

29

Port 1 Carrier Sense and Data Valid

Port 1 Transmit Data

28,27

26

O

Port 1 Transmit Enable

Port 2 RMII Interface

38,37

M2_RXD[1:0]

M2_CRS_DV

M2_TXD[1:0]

M2_TXEN

I, U

I, D

O

Port 2 Receive Data

36

Port 2 Carrier Sense and Data Valid

Port 2 Transmit Data

35,34

33

O

Port 2 Transmit Enable

Port 3 RMII Interface

45,44

M3_RXD[1:0]

M3_CRS_DV

M3_TXD[1:0]

M3_TXEN

I, U

I, D

O

Port 3 Receive Data

43

Port 3 Carrier Sense and Data Valid

Port 3 Transmit Data

42,41

40

O

Port 3 Transmit Enable

Port 4 RMII Interface

65,64

M4_RXD[1:0]

M4_CRS_DV

M4_TXD[1:0]

M4_TXEN

I, U

I, D

O

Port 4 Receive Data

63

Port 4 Carrier Sense and Data Valid

Port 4 Transmit Data

62,61

60

O

Port 4 Transmit Enable

Port 5 RMII Interface

72,71

M5_RXD[1:0]

M5_CRS_DV

M5_TXD[1:0]

M5_TXEN

I, U

I, D

O

Port 5 Receive Data

70

Port 5 Carrier Sense and Data Valid

Port 5 Transmit Data

69,68

67

O

Port 5 Transmit Enable

Port 6 RMII Interface

79,78

M6_RXD[1:0]

M6_CRS_DV

M6_TXD[1:0]

M6_TXEN

I, U

I, D

O

Port 6 Receive Data

77

Port 6 Carrier Sense and Data Valid

Port 6 Transmit Data

76,75

74

O

Port 6 Transmit Enable

Port 7 RMII Interface

86,85

84

M7_RXD[1:0]

M7_CRS_DV

M7_TXD[1:0]

M7_TXEN

I, U

I, D

O

Port 7 Receive Data

Port 7 Carrier Sense and Data Valid

Port 7 Transmit Data

83,82

81

O

Port 7 Transmit Enable

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Pin No(s).

Symbol

Type

Name & Functions

Port 8 MII Interface

105,104,103,102

M8_RXD[3:0]

M8_TXD[3:0]

M8_TXEN

I, U

O

Port 8 Receive Data

113,112,111,110

Port 8 Transmit Data

Port 8 Transmit Enable

Port 8 Receive Data Valid

Port 8 Receive Clock

109

97

O

M8_RXDV

I, D

I, U

100

107

114

116

115

98

M8_RXCLK

M8_TXCLK

M8_LINK

I/O, U Port 8 Transmit Clock

I, U Port 8 Link Status

I/O, U Port 8 Speed Select (100Mb = 1)

M8_SPEED

M8_DUPLEX

M8_COL

I, U

Port 8 Full-Duplex Select (half-duplex = 0)

Port 8 Collision Detect

118

M8_REFCLK

O, U

Port 8 Reference Clock

M8_REFCLK=1/2 M_CLK

Port 8 Serial Interface

102

100

97

S8_RXD

I, U

I, D

Port 8 Serial Receive Data

Port 8 Serial Receive Clock

S8_RXCLK

S8_CRS_DV

Port 8 Serial Carrier Sense and Data

Valid

110

107

109

98

S8_TXD

O

I

Port 8 Serial Transmit Data

Port 8 Serial Transmit Clock

Port 8 Serial Transmit Enable

Port 8 Serial Collision Detect

Port 8 Link Status

S8_TXCLK

S8_TXEN

S8_COL

O

I, U

114

115

S8_LINK

S8_DUPLEX

Port 8 Full-Duplex Select (half-duplex = 0)

Miscellaneous Control Pins

95

M_CLK

I

Reference Clock for Serial interface =

50Mhz±50ppm

148

SCLK

I

System Clock (50 Mhz)

Port Trunking Enable

126

TRUNK_EN

RESIN_

I, D

I, S

O

142

141

RESETOUT_

MIR_CTL[3:0]

146,145,144,143

I/O, U Port Mirroring Control

(only for RMII mode)

Test Pins

125

TEST#

NO Connect

139

TMODE

I/O, U Puts VTX1100 into test mode for ATE test

138,137,136,135

134,133,132,131

TSTOUT[7:4]

TSTOUT[3:0]

O

Test Outputs

I/O, U Test Outputs

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Pin No(s).

Symbol

Type

Name & Functions

Power Pins

3,39,73,96,130,159,184 VDD (Core)

Input +3.3 Volt DC Supply for Core Logic

(7 pins)

11,25,59,87,101,108,119 VDD

147,152,166,175,

Input +3.3 Volt DC Supply for I/O Pads (13 pins)

194, 202

18,46,80,106,140,171,

198

VSS (Core)

Input Ground for Core Logic (7 pins)

Input Ground for I/O Pads (13 pins)

7,32,66,94,99,117,121,1 VSS

49154,162,180,189,

207

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16.1 STRAP OPTIONS

The Strap options are relevant during the initial power-on period, when reset is asserted. During

reset, CoSMOS will examine the boot strap address pin to determine its value and modify the

internal configuration of the chip accordingly.

“1” means Pull UP

“0” means Pull Down with an external 1K Ohm

Default value is 1, (all boot strap pins have internal pull up resistor).

Pin No(s).

Symbol

Name & Functions

Boot Strap Pins

206 (L_A[5])

Memory size

EEPROM

1–Memory size = 256KB,

0 –Memory size = 512KB

1 – NO EEPROM Installed

0 – EEPROM Installed⁴

11 – 100Mbps

208 (L_A[6])

5,4 (L_A [10:9])

XLINK Speed

10 – 200Mbps

01 – 300Mbps

00 – 400Mbps (0—Pull down, 1—Pull up)

1 –MII Mode for port 8

0 –Serial mode for port 8

Link Polarity for serial interface

1 –Active Low

151 (L_A[17])

150 (L_A[2])

Port 8

MII/Serial

Link Polarity

FDX Polarity

Device ID

0 –Active High

204 (L_A[3])

Full/Half Duplex Polarity for serial interface

1 – Active Low

0 – Active High

2 (L_A[8])

Use in cascade mode only.

133 (TST[2])

SRAM Self Test For Board/System Manufacturing Test⁵

1 – Disable

0 – Enable

⁴– If the VTX1100 is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to

load its configuration from the EEPROM. If the EEPROM is blank or not preset, it will not boot up.

The parallel port can be used to program the EEPROM at any time.

⁵– During normal power-up CoSMOS 2 will run through an external SSRAM memory test to ensure

that there are no memory interface problems. If a problem is detected, the chip will stop functioning.

To facilitate board debug in the event that a system stops functioning, the DS108A can be put into a

continuous SSRAM self test mode to allow an operator to determine if there are stuck pins in the

memory interface (using network analyzer).

VERTEX NETWORKS, INC.

27

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

16.2 PIN REFERENCE TABLE

Pin Name

#

Pin Name

Pin #

Pin Name

Pin Pin Name Pin

#

L_A[7]

L_A[8]

1

2

M4_CLS

M4_LINK

53 M8_RXD[3]

54 VSS (CORE)

105 L_ADSC#

106 L_A[16]

157

158

VDD (CORE)

L_A[9]

L_A[10]

L_A[11]

VSS

L_A[12]

L_A[13]

L_A[14]

VDD

3

4

5

6

7

8

9

M4_DUPLEX

M5_CLS

M5_LINK

M5_DUPLEX

VDD

M4_TXEN

55 M8_TXCLK/S8_TXCLK

56 VDD

57 M8_TXEN/S8_TXEN

58 M8_TXD[0]/S8_TXD

59 M8_TXD[1]

60 M8_TXD[2]

61 M8_TXD[3]

107 VDD (CORE) 159

108 L_A[15]

109 L_D[0]

110 VSS

111 L_D[1]

112 L_D[2]

113 L_D[3]

114 VDD

160

161

162

163

164

165

166

167

168

169

170

M4_TXD/(M4_TXD[0])

10 M4_TXCLK/(M4_TXD[1]) 62 M8_LINK/S8_LINK

11 M4_CRS_DV

12 M4_RXD/(M4_RXD[0])

13 M4_RXCLK/(M4_RXD[1]) 65 VSS

14 VSS

15 M5_TXEN

63 M8_DUPLEX/S8_DUPLEX 115 L_D[4]

64 M8_SPEED

M0_CLS

116 L_D[5]

117 L_D[6]

118 L_D[7]

M0_LINK

M0_ DUPLEX

M1_CLS

66 M8_REFCLK

67 VDD

119 VSS (CORE) 171

M1_LINK

M1_DUPLEX

VSS (CORE)

M0_TXEN

M0_TXD/(M0_TXD[0])+

M0_TXCLK/(M0_TXD[1]) 21 VDD (CORE)

M0_CRS_DV

M0_RXD/(M0_RXD[0])

M0_RXCLK/(M0_RXD[1]) 24 M6_TXCLK/(M6_TXD[1]) 76 DATA0

16 M5_TXD/(M5_TXD[0])

17 M5_TXCLK/(M5_TXD[1]) 69 VSS

18 M5_CRS_DV

19 M5_RXD/(M5_RXD[0])

68 M_MDC

120 L_D[8]

121 L_D[9]

122 L_D[10]

123 VDD

124 L_D[11]

125 L_D[12]

126 L_D[13]

127 L_D[14]

128 VSS

172

173

174

175

176

177

178

179

180

181

182

183

70 M_MDIO

71 SCL

20 M5_RXCLK/(M5_RXD[1]) 72 SDA

73 TEST#

74 TRUNK_ENABLE

75 STROBE

22 M6_TXEN

23 M6_TXD/(M6_TXD[0])

VDD

M1_TXEN

M1_TXD/(M1_TXD[0])

25 M6_CRS_DV

26 M6_RXD/(M6_RXD[0])

27 M6_RXCLK/(M6_RXD[1]) 79 TSTOUT[0]

77 ACK

78 VDD (CORE)

129 L_D[15]

130 L_D[16]

131 L_D[17]

M1_TXCLK/(M1_TXD[1]) 28 VSS (CORE)

80 TSTOUT[1]

81 TSTOUT[2]

82 TSTOUT[3]

132 VDD (CORE) 184

M1_CRS_DV

29 M7_TXEN

133 L_D[18]

134 L_D[19]

135 L_D[20]

136 L_D[21]

137 VSS

185

186

187

188

189

190

191

192

193

194

195

196

197

M1_RXD/(M1_RXD[0])

30 M7_TXD/(M7_TXD[0])

M1_RXCLK/(M1_RXD[1]) 31 M7_TXCLK/(M7_TXD[1]) 83 TSTOUT[4]

VSS

32 M7_CRS_DV

84 TSTOUT[5]

85 TSTOUT[6]

M2_TXEN

33 M7_RXD/(M7_RXD[0])

M2_TXD/(M2_TXD[0])

34 M7_RXCLK/(M7_RXD[1]) 86 TSTOUT[7]

138 L_D[22]

139 L_D[23]

140 L_D[24]

141 L_D[25]

142 VDD

M2_TXCLK/(M2_TXD[1]) 35 VDD

87 T_MODE

88 VSS (CORE)

89 RSTOUT#

90 RSTIN#

91 (MIRROR_CONTROL[0]) 143 L_D[26]

92 (MIRROR_CONTROL[1]) 144 L_D[27]

93 (MIRROR_CONTROL[2]) 145 L_D[28]

M2_CRS_DV

M2_RXD/(M2_RXD[0])

36 M6_CLS

37 M6_LINK

M2_RXCLK/(M2_RXD[1]) 38 M6_DUPLEX

VDD (CORE)

39 M7_CLS

M3_TXEN

M3_TXD/(M3_TXD[0])

40 M7_LINK

41 M7_DUPLEX

M3_TXCLK/(M3_TXD[1]) 42 VSS

94 (MIRROR_CONTROL[3]) 146 VSS (CORE) 198

M3_CRS_DV

M3_RXD/(M3_RXD[0])

M3_RXCLK/(M3_RXD[1]) 45 M8_RXDV/S8_CRS_DV

VSS (CORE)

M2_CLS

M2_LINK

M2_ DUPLEX

M3_CLS

M3_LINK

43 M_CLK

44 VDD (CORE)

95 VDD

96 SCLK

97 VSS

98 L_A[2]

99 L_A[17]

100 VDD

101 L_CLK

102 VSS

147 L_D[29]

148 L_D[30]

149 L_D[31]

150 VDD

151 L_A[18]

152 L_A[3]

153 L_A[4]

154 L_A[5]

155 VSS

199

200

201

202

203

204

205

206

207

208

46 M8_COL/S8_COL

47 VSS

48 M8_RXCLK/S8_RXCLK

49 VDD

50 M8_RXD[0]/S8_RXD

51 M8_RXD[1]

103 L_WE#

104 L_OE#

M3_ DUPLEX

52 M8_RXD[2]

156 L_A[6]

+ : pins inside ( ) indicate for RMII pins for port 0-7.

VERTEX NETWORKS, INC.

28

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

16.3 VTX1100 PHYSICAL PINOUT

208

157

156

1

L_A[7]

L_OE#

L_A[8]

L_WE#

VDD (CORE)

VSS

L_A[9]

L_A[10]

L_A[11]

L_CLK

VDD

L_A[17]

L_A[2]

Pin 1 I.D.

Buffer Mem Interface

VSS

L_A[12]

VSS

L_A[13]

SCLK

L_A[14]

VDD

M0_CLS

M0_LINK

M0_DUPLEX

M1_CLS

MIR_CTL[3]

MIR_CTL[2]

MIR_CTL[1]

MIR_CTL[0]

RSTIN#

M1_LINK

M1_DUPLEX

VSS (CORE)

M0_TXEN

M0_TXD

M0_TXCLK

M0_CRS_DV

M0_RXD

M0_RXCLK

VDD

M1_TXEN

M1_TXD

M1_TXCLK

M1_CRS_DV

M1_RXD

M1_RXCLK

VSS

RSTOUT#

VSS (CORE)

T_MODE

TSTOUT[7]

TSTOUT[6]

TSTOUT[5]

TSTOUT[4]

TSTOUT[3]

TSTOUT[2]

TSTOUT[1]

TSTOUT[0]

VDD (VORE)

ACK

DATA0

STROBE

TRUNK_EN

TEST#

M2_TXEN

M2_TXD

SDA

SCL

M2_TXCLK

M2_CRS_DV

M2_RXD

M_MDIO

VSS

M_MDC

M2_RXCLK

VDD (CORE)

M3_TXEN

M3_TXD

M3_TXCLK

M3_CRS_DV

M3_RXD

M3_RXCLK

VSS (CORE)

M2_CLS

M2_LINK

M2_DUPLEX

M3_CLS

VDD

M8_REFCLK

VSS

M8_SPEED

M8_DUPLEX

M8_LINK

M8_TXD[3]

M8_TXD[2]

M8_TXD[1]

M8_TXD[0]

M8_TXEN

VDD

M8_TXCLK

VSS (CORE)

M8_RXD[3]

Serail Port Interfaces

M3_LINK

M3_DUPLEX

52

105

104

53

VERTEX NETWORKS, INC.

29

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

17 DC Electrical Characteristics

17.1 ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Operating Temperature

-65C to +150C

0C to +70C

Supply Voltage VDD with Respect to V_SS

+3.0 V to +3.6 V

Voltage on 5V Tolerant Input Pins

Voltage on Other Pins

-0.5 V to (VDD + 3.3 V)

-0.5 V to (VDD + 0.3 V)

Caution: Stresses above those listed may cause permanent device failure. Functionality at or above these limits is

not implied. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability.

17.2 DC ELECTRICAL CHARACTERISTICS

VDD = 3.0 V to 3.6 V (3.3v +/- 10%)

T_AMBIENT= 0 C to +70 C

PRELIMINARY

MIN TYP. MAX

66 80

SYMBOL PARAMETER DESCRIPTION

UNIT

f_osc

Frequency of Operation

50

MHz

mA

V

I_DD

V_OH

V_OL

Supply Current – @ 80 MHz (VDD =3.3 V)

Output High Voltage (CMOS)

Output Low Voltage (CMOS)

TBD

VDD - 0.5

0.5

V

V_IH-TTL

Input High Voltage (TTL 5V tolerant)

VDD x

70%

VDD +

2.0

V

V_IL-TTL

I_IH-5VT

Input Low Voltage (TTL 5V tolerant)

VDD x

30%

TBD

V

Input Leakage Current (0.1 V < V_IN< VDD)

(all pins except those with internal pull-

up/pull-down resistors)

mA

I_IL-5VT

I_LI

Output Leakage Current (0.1 V < V_OUT< VDD)

Input Leakage Current V_IH= VDD - 0.1 V

(pins with internal pull-down resistors)

Input Leakage Current V_IL= 0.1 V

(pins with internal pull-up resistors)

Input Capacitance

TBD

mA

I_LO

TBD

mA

C_IN

C_OUT

C_I/O

5

7

pF

Output Capacitance

I/O Capacitance

VERTEX NETWORKS, INC.

30

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

17.3 CLOCK FREQUENCY SPECIFICATIONS

Symbol

Parameter

(Hz)

Note:

C1

C2

C3

C4

C5

C6

SCLK – Core System Clock Input

M_CLK – RMII Port Clock

50M

25M

M8_REFCLK – MII Reference Clock

L_CLK – Frame Buffer Memory Clock

M_MDC – MII Management Data Clock

SCL – I²C Data Clock

55M L_CLK = SCLK

1.56M M_MDC=SCLK/32

50K SCL=M_CLK/1000

Suggestion Clock rate for various configurations:

Input

Output

M_CLK

(RMII)

Configuration

SCLK

M8_REF L_CLK

M_MDC

SCL

Port0-7 Port 8

10M RMII 10/100M 50M

MII

50M

--

=SCLK

=SCLK/32

50K

100M

RMII

100M

RMII

100M

RMII

100M

RMII

100M

RMII

Not

Used

10/100M 60M

MII

200M

MII

300M

MII

400M

MII

55M

--

25M

50M

75M

100M

66.66M 50M

75M

80M

50M

VERTEX NETWORKS, INC.

31

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

17.4 AC TIMING CHARACTERISTICS

17.4.1 FRAME BUFFER MEMORY INTERFACE:

L_CLK

L1

L2

L_D[31:0]

L_CLK

L_D[31:0]

L_A[18:2]

L3-max

L3-min

L4-max

L4-min

L6-max

L6-min

L_ADSC#

L8-max

L8-min

L_WE#

L_OE#

L9-max

L9-min

17.5 FRAME BUFFER MEMORY INTERFACE TIMING

50 MHz

Symbol

L1

Parameter

L_D[31:0] input set-up time

L_D[31:0] input hold time

L_D[31:0] output valid delay

L_A[18:2] output valid delay

L_ADSC# output valid delay

L_WE# output valid delay

L_OE# output valid delay

Min (ns) Max (ns)

Note:

5

0

L2

L3

1

8

C_L= 30pf

C_L= 50pf

C_L= 30pf

L4

L6

L8

L9

VERTEX NETWORKS, INC.

32

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

17.6 SERIAL TIMING REQUIREMENTS

50 MHZ

SYMBOL

M1

PARAMETER

Min (ns) Max (ns)

NOTE:

M_CLK

Reference Input

Clock

M2

M3

M4

M5

M6

M7

M[7:0]_RXD[1:0] Input Setup Time

M[7:0]_RXD[1:0] Input Hold Time

M[7:0]_CRS_DV Input Setup Time

M[7:0]_TXEN Output Delay Time

M[7:0]_TXD[1:0] Output Delay Time

M[7:0]_LINK Input Setup Time

4

1

4

1

11

C_L= 30 pF

17.7 RMII TIMING REQUIREMENTS

50 MHZ

SYMBOL

M1

PARAMETER

Min (ns) Max (ns)

NOTE:

M_CLK

Reference Input

Clock

M2

M3

M4

M5

M6

M7

M[7:0]_RXD[1:0] Input Setup Time

M[7:0]_RXD[1:0] Input Hold Time

M[7:0]_CRS_DV Input Setup Time

M[7:0]_TXEN Output Delay Time

M[7:0]_TXD[1:0] Output Delay Time

M[7:0]_LINK Input Setup Time

4

1

4

1

11

C_L= 30 pF

VERTEX NETWORKS, INC.

33

Ver 1.22

VTX1100

Advanced Datasheet

8 +1 -port HomePNA ETHERNET PACKET CONCENTRATOR

“Preparing Networks for Convergence”

November, 1999

18 Packaging

VTX1100 is packaged in a 208 pin PQFP (dimensions in mm).

30.6 ± 0.20

25.2 REF

208

157

156

1

Pin 1 I.D.

25.2

28.0

30.6

A

B

REF ± 0.20 ± 0.20

52

105

53

104

0.50

typ

0.20

-.03/+.07

D

28.0 ± 0.20

3.40

± 0.20

4.10

MAX.

C

0.25

MIN.

1.30 REF.

0.50/0.75

Ordering Information

Part Number

Description

Identification

Vertex Networks

Use

Revision

8-Port Ethernet Packet

Concentrator

VTX1100

C 0 P

TAV

rrr

Environmental – C = Commercial

I = Industrial

Revision - 001 = Rev.1

For latest revision, leave blank

Not used, leave as “0”

Package -

P= PQFP

VERTEX NETWORKS, INC.

34

Ver 1.22

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