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Weltrend Semiconductor, Inc.

WT61P4

Embedded Micro-Controller for Monitor

(Flash Memory Type)

Data Sheet

REV. 1.03

Aug 20, 2004

The information in this document is subject to change without notice.

2F, No. 24, Industry E. 9^thRD., Science-Based Industrial Park, Hsin-Chu, Taiwan

TEL:886-3-5780241 FAX:886-3-5794278.5770419

Email:support@weltrend.com.tw

WT61P4 v1.03

Monitor Controller

GENERAL DESCRIPTION

The WT61P4 is a microcontroller for digital controlled monitor with 1) 8051 compatible cpu, 2) 64K

bytes Flash memory, 3) 1024 bytes SRAM, 4) 16 PWMs, 5) SYNC signal processor, 6) 2 timers, 7)

DDC1/2B interface, 8) master/slave I²C interface, 9) 8-bit A/D converter, 10) watch-dog timer, 11) ISP,

12) power down mode 13)IR detect.

FEATURES

•

8-bit 8051 compatible CPU with 12/24MHz operating frequency

64K bytes flash memory, 1024 bytes SRAM (256 bytes internal + 768 bytes external)

12/24MHz crystal oscillator

16 channels PWM outputs (15 8-bit + 1 16-bit)

• Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control

and clamp pulse output

• Programmable free-running SYNC signal output & White video pattern (Horizontal frequency up to

250KHz with programmable H pulse width and V pulse width)

• Programmable H and V overflow interrupt for fast blanking

•

Two timers compatible to 8051

DMA DDC1/2B module for EDID1.3, EDID2.0 (A2/A3, A6/A7) and Enhance EDID (60/61)

Fast mode master/slave I²C interface (up to 400KHz)

8-bit A/D converter with 4 selectable inputs

Watchdog timer

Maximum 35 programmable I/O pins (PLCC package)

Two external interrupt request input

5/3.3 volt operate voltage supported

Low VDD reset supported

ISP function supported

Power down mode supported

IR detect

C compiler supported

ORDERING INFORMATION

Package Type

40-pin PDIP

Part Number

61P4-N400WT(3.3v/5v)

61P4-N401WT(3.3v)

61P4-K420WT(3.3v/5v)

61P4-K421WT(3.3v)

61P4-L440WT(3.3v/5v)

61P4-L441WT(3.3v/5v)

40-pin PDIP

42-pin Shrink PDIP

44-pin PLCC

Weltrend Semiconductor, Inc.

Page 2

WT61P4 v1.03

Monitor Controller

PIN ASSIGNMENT AND PACKAGE TYPE

VDD=3.3v/5v

VDD=3.3v

PD7/PWM2/VIN2

PE0/PWM0

NRES

1

2

3

4

5

6

7

8

9

40 VIN1

PD7/PWM2/VIN2

PE1/PWM1

PE0/PWM0

NRES

1

2

3

4

5

6

7

8

9

40 VIN1

39 HIN1

38 PD6/PWM3/HIN2

37 PD5/PWM4/P10

36 PD4/PWM5/P11

35 PD3/PWM6/P12

34 PD2/PWM7/P13

33 PD1/HOUT

38 PD6/PWM3/HIN2

37 PD5/PWM4/P10

36 PD4/PWM5/P11

35 PD3/PWM6/P12

34 PD2/PWM7/P13

33 PD1/HOUT

VDD3V

VDD5V

GND

VDD3V

GND

OSCO

OSCI

PB6/SDA2

32 PD0/VOUT

PB6/SDA2

32 PD0/VOUT

PB5/SCL2 10

PB4/PAT 11

31 PA7/PWM13/CLAMP

30 PA6/PWM12/1/2VO

29 PA5/PWM11/1/2HO

28 PA4/PWM10

27 PA3/PWM9

PB5/SCL2 10

PB4/PAT 11

31 PA7/PWM13/CLAMP

30 PA6/PWM12/1/2VO

29 PA5/PWM11/1/2HO

28 PA4/PWM10

27 PA3/PWM9

61P4_N400

61P4_N401

PB3/FDO/T0 12

PB2/FDI/T1 13

PB1/NIRQ2/IRIN 14

PB0/NIRQ1 15

PC7/SOGIN/P17 16

PC6/P16 17

PB3/FDO/T0 12

PB2/FDI/T1 13

PB1/NIRQ2/IRIN 14

PB0/NIRQ1 15

PC7/SOGIN/P17 16

PC6/P16 17

26 PA2/PWM8

25 PA1/SCL1/RXD

24 PA0/SDA1/TXD

23 PC0/AD0

25 PA1/SCL1/RXD

24 PA0/SDA1/TXD

23 PC0/AD0

PC5/P15 18

PC4/P14 19

22 PC1/AD1

PC4/P14 19

22 PC1/AD1

PC3/AD3 20

21 PC2/AD2

PC3/AD3 20

21 PC2/AD2

VDD=3.3v/5v

VDD=3.3v

PE2/PWM14

PE1/PWM1

PE0/PWM0

NRES

1

2

3

4

5

6

7

8

9

42 PD7/PWM2/VIN2

41 VIN1

PE3/PWM15

PE2/PWM14

PE1/PWM1

PE0/PWM0

NRES

1

2

3

4

5

6

7

8

9

42 PD7/PWM2/VIN2

41 VIN1

40 HIN1

39 PD6/PWM3/HIN2

38 PD5/PWM4/P10

37 PD4/PWM5/P11

36 PD3/PWM6/P12

35 PD2/PWM7/P13

34 PD1/HOUT

39 PD6/PWM3/HIN2

38 PD5/PWM4/P10

37 PD4/PWM5/P11

36 PD3/PWM6/P12

35 PD2/PWM7/P13

34 PD1/HOUT

VDD3V

VDD5V

GND

VDD3V

GND

OSCO

OSCI

PB6/SDA2 10

PB5/SCL2 11

PB4/PAT 12

33 PD0/VOUT

PB6/SDA2 10

PB5/SCL2 11

PB4/PAT 12

33 PD0/VOUT

61P4_K420

61P4_K421

32 PA7/PWM13/CLAMP

31 PA6/PWM12/1/2VO

30 PA5/PWM11/1/2HO

29 PA4/PWM10

28 PA3/PWM9

32 PA7/PWM13/CLAMP

31 PA6/PWM12/1/2VO

30 PA5/PWM11/1/2HO

29 PA4/PWM10

28 PA3/PWM9

PB3/FDO/T0 13

PB2/FDI/T1 14

PB1/NIRQ2/IRIN 15

PB0/NIRQ1 16

PC7/SOGIN/P17 17

PC6/P16 18

PB3/FDO/T0 13

PB2/FDI/T1 14

PB1/NIRQ2/IRIN 15

PB0/NIRQ1 16

PC7/SOGIN/P17 17

PC6/P16 18

27 PA2/PWM8

26 PA1/SCL1/RXD

25 PA0/SDA1/TXD

24 PC0/AD0

26 PA1/SCL1/RXD

25 PA0/SDA1/TXD

24 PC0/AD0

PC5/P15 19

PC4/P14 20

23 PC1/AD1

PC4/P14 20

23 PC1/AD1

PC3/AD3 21

22 PC2/AD2

PC3/AD3 21

22 PC2/AD2

VDD5V

GND

7

8

9

39 PD5/PWM4/P10

38 PD4/PWM5/P11

37 PD3/PWM6/P12

36 PD2/PWM7/P13

35 PD1/HOUT

NRES

VDD5V

NC1

7

8

9

39 PD3/PWM6/P12

38 PD2/PWM7/P13

37 PD1/HOUT

OSCO

VDD=3.3v/5v

OSCI 10

PB6/SDA2 11

GND 10

OSCO 11

36 PD0/VOUT

35 PA7/PWM13/CLAMP

34 PA6/PWM12/1/2VO

33 PA5/PWM11/1/2HO

32 PA4/PWM10

61P4_L440

(PLCC)

61P4_L441

(PLCC)

PB5/SCL2 12

34 PD0/VOUT

OSCI 12

PB4/PAT 13

33 PA7/PWM13/CLAMP

32 PA6/PWM12/1/2VO

31 PA5/PWM11/1/2HO

30 PA4/PWM10

PB6/SDA2 13

PB5/SCL2 14

PB4/PAT 15

PB3/FDO/T0 16

PB2/FDI/T1 17

PB3/FDO/T0 14

PB2/FDI/T1 15

PB1/NIRQ2/IRIN 16

PB0/NIRQ1 17

31 PA3/PWM9

30 PA2/PWM8

29 PA3/PWM9

29 PA1/SCL1/RXD

Weltrend Semiconductor, Inc.

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WT61P4 v1.03

Monitor Controller

PIN DESCRIPTION (5V-package)

Pin No.

Pin Name

I/O

Description

441 440 420 400

3

-

4

5

6

7

-

8

9

1

2

-

3

4

5

6

7

-

1

-

2

3

4

5

6

-

PE3/PWM15

I/O Port E3 or PWM15

I/O Port E2 or PWM14

P +3.3V power supply

I/O Port E1 or PWM1

I/O Port E0 or PWM0 (12 bits)

I/O Reset input

P +3.3V power supply

P +5V power supply

No Connection

PE2/PWM14

VDD3V

PE1/PWM1

PE0/PWM0

NRES

VDD3V

VDD5V

NC

-

2

3

4

5

-

10

11

12 10

8

9

7

8

9

6

7

8

9

GND

OSCO

OSCI

PB6/SDA2

P Ground

O 12Mhz or 24MHz oscillator output

12Mhz or 24MHz oscillator input

I

13 11 10

I/O Port B6 or IIC SDA

14 12 11 10 PB5/SCL2

15 13 12 11 PB4/PAT

16 14 13 12 PB3/FDO/T0

17 15 14 13 PB2/FDI/T1

18 16 15 14 PB1/NIRQ2/IRIN

19 17 16 15 PB0/NIRQ1

20 18 17 16 PC7/SOGIN/P17

21 19 18 17 PC6/P16

22 20 19 18 PC5/P15

23 21 20 19 PC4/P14

24 22 21 20 PC3/AD3

25 23 22 21 PC2/AD2

26 24 23 22 PC1/AD1

27 25 24 23 PC0/AD0

28 26 25 24 PA0/SDA1/TXD

29 27 26 25 PA1/SCL1/RXD

30 28 27 26 PA2/PWM8

31 29 28 27 PA3/PWM9

32 30 29 28 PA4/PWM10

I/O Port B5 or IIC SCL

I/O Port B4 or test pattern output

I/O Port B3 or frequency divider output

I/O Port B2 or frequency divider input

I/O Port B1 or External interrupt II request input or IR input

I/O Port B0 or External interrupt I request input

I/O Port C7 or Sync on Green input or 8031 P1.7

I/O Port C6 or 8031 P1.6

I/O Port C5 or 8031 P1.5

I/O Port C4 or 8031 P1.4

I/O Port C3 or ADC input 3

I/O Port C2 or ADC input 2

I/O Port C1 or ADC input 1

I/O Port C0 or ADC input 0

I/O Port A0 or DDC SDA pin or RS232C TXD

I/O Port A1 or DDC SCL pin or RS232C RXD

I/O Port A2 or PWM8

I/O Port A3 or PWM9

I/O Port A4 or PWM10

33 31 30 29 PA5/PWM11/(1/2HO) I/O Port A5 or PWM11 or 1/2 HOUT

34 32 31 30 PA6/PWM12/(1/2VO) I/O Port A6 or PWM12 or 1/2 VOUT

35 33 32 31 PA7/PWM13/CLAMP I/O Port A7 or PWM13 or CLAMP output

36 34 33 32 PD0/VOUT

37 35 34 33 PD1/HOUT

38 36 35 34 PD2/PWM7/P13

39 37 36 35 PD3/PWM6/P12

40 38 37 36 PD4/PWM5/P11

41 39 38 37 PD5/PWM4/P10

42 40 39 38 PD6/PWM3/HIN2

43 41 40 39 HIN1

I/O Port D0 or VSYNC output

I/O Port D1 or HSYNC output

I/O Port D2 or PWM7 or 8031 P1.3

I/O Port D3 or PWM6 or 8031 P1.2

I/O Port D4 or PWM5 or 8031 P1.1

I/O Port D5 or PWM4 or 8031 P1.0

I/O

I

Port D6 or PWM3 or HSYNC II Input

HSYNC I Input.

VSYNC I input.

44 42 41 40 VIN1

1

2

-

1

-

NC

No Connection

Port D7 or PWM2 or VSYNC II Input

No Connection

43 42

44

PD7/PWM2/VIN2

NC

I/O

-

Weltrend Semiconductor, Inc.

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WT61P4 v1.03

Monitor Controller

FUNCTIONAL DESCRIPTION

CPU

8-bit 8051 compatible CPU with 16-bit address bus and 8-bit data bus operates at 12/24MHz.

RAM

The 1024 bytes SRAM include:

128 bytes internal SRAM are from $0000H to $007FH (direct & indirect addressing)

128 bytes internal SRAM are from $0080H to $00FFH (indirect addressing)

384 bytes external SRAM are from $0080H to $01FFH

256 bytes external SRAM are from $0200H to $02FFH or from $0280H to $037FH share with DDC

(A2/A3 or A6/A7) EDID

128 bytes external SRAM are from $0300H to $037FH or from $0200H to $027FH or from $0280H to

$02FFH share with DDC (A0/A1) EDID

Flash Memory

64K bytes flash memory for program. Address is located from $0000h to $FFFFh.

Weltrend Semiconductor, Inc.

Page 5

WT61P4 v1.03

Monitor Controller

Memory Mapping

Program Memory

$FFFFH

Internal Memory

Data memory

$FFFFH

Reserved

$0380H

$037FH

DDC

128 bytes

RAM 3

ROM

$0300H

$02FFH

DDC

128 bytes

RAM 2

$0280H

$027FH

DDC

128 bytes

RAM 1

$0200H

$01FFH

384 bytes

RAM

$00FFH

Upper

128 bytes

RAM

SFR

Registers

$0080H

$007FH

$0080H

$007FH

Lower

128 bytes

RAM

Registers

$0000H

Weltrend Semiconductor, Inc.

Page 6

WT61P4 v1.03

Monitor Controller

System Reset

There are three reset sources of this controller. All reset signals will last 1.024ms. Fig.1 shows the

block diagram of reset logic.

NRES

LATCH

Watchdog Timer Reset

Low VDD Reset

CPU

R

VDD

Peripheral

Circuits

1.024ms

Timer

Fig. 1 Reset Signals

NRES

The NRES-Reset happens when there is a low level on the NRES pin.

Low VDD Reset

The Low-VDD-Reset is generated when VDD3V is below 2.7V either VDD=5v or VDD=3.3v. The reset

signal will last 1.024ms after the voltage is higher than 2.7V.

Watchdog Timer Reset

The Watchdog-Timer-Reset happens when the watchdog timer is time out. Please refer to the

watchdog timer section for more detail.

Weltrend Semiconductor, Inc.

Page 7

WT61P4 v1.03

Monitor Controller

I/O Port

I/O Port A

The PA0 and PA1 are general purpose IO shared with DDC interface and 8031 UART interface. They

are the IO port only when both ENDDC and REN are “0”. If the PA0OE is “1”, Pin PA0 is an open-drain

output port. If the PA0OE is “0”, Pin PA0 is an input port without internal pull-up resistor. The PA1 is

the same as the PA0. Fig. 2 shows the structure of PA0.

INTERNAL_DATA_BUS

DATA[0]

PA0OE

D

C

Q

PA0

WRITE_PA_CTRL

RESET

QN

R

DATA[0]

PA0O

D

C

Q

WRITE_PA_DATA

RESET

QN

R

READ_PA_DATA

DATA[0]

Fig.2 Structure of PA0 and PA1

The PA2 to PA7 are general purpose IO shared with PWM output and some special functions. When

the EPWMn is “0” and the special function is disabled, PAn is a general purpose I/O port. If the PAnOE

is “1”, the PAn is configured as an output port in a push-pull type which can source or sink 6mA. If the

PAnOE is “0”, the PAn is configured as an input port with internal pull-up resistor.

INTERNAL_DATA_BUS

DATA[2]

PA2OE

D

C

Q

WRITE_PA_CTRL

RESET

QN

R

PA2

DATA[2]

PA2O

D

C

Q

WRITE_PA_DATA

RESET

QN

R

READ_PA_DATA

DATA[2]

Fig.3 Structure of PA2

Weltrend Semiconductor, Inc.

Page 8

WT61P4 v1.03

Monitor Controller

Port A control and data register

Name

Addr R/W Initial Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PA_CTRL 0000h

W

R

W

00h

ffh

PA7OE PA6OE PA5OE PA4OE PA3OE PA2OE PA1OE PA0OE

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PA_DATA 0001h

Bit Name

Description

Port An Output Enable.

When it is set, PAn is configured as an output pin.

When it is cleared, PA2~PA7 are configured as the input pin with internal pull-up resistor.

PA0 and PA1 are configured as the input pin without internal pull-up resistor.

This bit controls the output level when the corresponding PAnOE bit is set.

PAnOE

PAn (W) When PAn=1, PAn pin outputs high level. (PA0 and PA1 are open-drain output)

When PAn=0, PAn pin outputs low level.

When PAnOE=1 (i.e. output port), the data of this bit is the same to PAn (W).

When PAnOE=0, this bit indicates the input level. “1” is high and “0” is low.

PAn (R)

I/O Port B

The PB0~PB6 are general purpose IO shared with some special functions. When the special function is

disabled, the PBn is a general purpose I/O port and is same as PA2. If it is configured as an output, it

could source/sink 6mA. If it is configured as an input, there is an internal pull-up resistor enabled.

Port B control and data register

Name

Addr R/W Initial Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PB_CTRL 0002h

W

R

W

00h

xfh

Xfh

--

PB6OE PB5OE PB4OE PB3OE PB2OE PB1OE PB0OE

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PB_DATA 0003h

Bit Name

Description

Port Bn Output Enable.

PBnOE When it is “1”, PBn is configured as an output pin.

When it is “0”, PBn is configured as an input pin with internal pull high

This bit controls the output level when the corresponding PBnOE bit is set.

PBn (W) When PBn=1, the PBn pin outputs high level.

When PBn=0, the PBn pin outputs low level.

When PBnOE=1 (i.e. output port), the data of this bit is the same to PBn (W).

When PBnOE=0, this bit indicates the input level. “1” is high and “0” is low.

PBn (R)

Weltrend Semiconductor, Inc.

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WT61P4 v1.03

Monitor Controller

I/O Port C

The PC0~PC7 are general purpose IO shared with some special functions. When the function is

disabled, the PCn is a general purpose I/O port and is the same as PA2. If it is configured as output, it

could source 6mA and sink 10mA. If it is configured as an input, it has an internal pull-up resistor.

Port C control and data register

Name

Addr R/W Initial Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PC_CTRL 0004h

W

R

W

00h PC7OE PC6OE PC5OE PC4OE PC3OE PC2OE PC1OE PC0OE

ffh

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PC_DATA 0005h

Bit Name

Description

Port Cn Output Enable.

PCnOE When it is “1”, PCn is configured as an output pin.

When it is “0”, PCn is configured as an input pin with internal pull-up resistor.

This bit controls the output level when the corresponding PCnOE bit is set.

PCn (W) When PCn=1, PCn pin outputs high level.

When PCn=0, PCn pin outputs low level.

When PCnOE=1 (i.e. output port), the data of this bit is the same as PCn (W).

When PCnOE=0, this bit indicates the input level. “1” is high and “0” is low.

PCn (R)

I/O Port E

The PE0~PE3 are the general purpose IO shared with PWM output. When the corresponding EPWMn

bit is “0”, it is a general I/O port and is the same as PA2. If it is configured as an output, it could

source/sink 6mA. If it is configured as an input, it has an internal pull-up resistor.

Port E control and data register

Name

Addr R/W Initial Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PE_CTRL 0008h

W

R

W

00h

xfh

--

PE3OE PE2OE PE1OE PE0OE

PE3

PE2

PE1

PE0

PE_DATA 0009h

Bit Name

Description

Port En Output Enable.

PEnOE When it is “1”, the PEn is configured as an output pin.

When it is “0”, the PEn is configured as an input pin with internal pull-up resistor.

This bit controls the output level when the corresponding PEnOE bit is set.

PEn (W) When PEn=1, PEn pin outputs high level.

When PEn=0, PEn pin outputs low level.

When PEnOE=1 (i.e. output port), the data of this bit is the same as PEn (W).

When PEnOE=0, this bit indicates the input level. “1” is high and “0” is low.

PEn (R)

Weltrend Semiconductor, Inc.

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WT61P4 v1.03

Monitor Controller

I/O Port D

The PD0~PD7 are the general purpose IO shared with some special functions. When the special

function is disabled, it is a general purpose I/O port. If it is configured as output, it could source/sink

6mA. If it is configured as input and PdnHE is “0”, it has an internal pull-up resistor. If the PDn is

configured as input and the PDnHE is “1”, it doesn’t have an internal pull-up resistor.

INTERNAL_DATA_BUS

DATA[0]

PD0HE

PD0OE

PD0O

D

C

Q

WRITE_PD_CTRL2

RESET

QN

R

D

C

Q

WRITE_PD_CTRL

RESET

QN

PD0

D

C

Q

WRITE_PD_DATA

RESET

QN

READ_PD_DATA

DATA[0]

Fig.4 Structure of PD0

Port D control and data register

Name

Addr R/W Initial Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PD_CTRL 0006h

W

R

W

00h PD7OE PD6OE PD5OE PD4OE PD3OE PD2OE PD1OE PD0OE

ffh

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PD_DATA 0007h

PD_CTRL2

000Ah

00h PD7HE PD6HE PD5HE PD4HE PD3HE PD2HE PD1HE PD0HE

Bit Name

Description

Port Dn Output Enable.

PDnOE When it is “1”, PDn is configured as an output pin.

When it is “0”, PDn is configured as an input pin with internal pull-up resistor.

This bit controls the output level when the corresponding PDnOE bit is set.

PDn (W) When PDn=1, PDn pin outputs high level.

When PDn=0, PDn pin outputs low level.

When PDnOE=1 (i.e. output port), the data of this bit is same as PDn (W).

When PDnOE=0, this bit indicates the input level. “1” is high and “0” is low.

PDn (R)

Configured the Port Dn pull-up resistor.

PDnHE When PDnHE =1, PDn pin without pull-up resistor.

When PDnHE =0, PDn pin with pull-up resistor.

Weltrend Semiconductor, Inc.

Page 11

WT61P4 v1.03

Monitor Controller

SYNC Processor

The functional block diagram of Sync Processor is shown in Fig.5. It contains H and V polarity detection

circuit, H and V frequency counter, composite sync signal separation circuit, free-running H and V sync

signal generator, video signal generation circuit for burn-in test and clamp pulse generator.

HCHG

H Period Counter

SOG HVIN2

SEPART

MUX

HIN

SOGIN

HIN2

H Freq Counter

EXTRHS

EXTRVS

MUX

ENFREE

MUX

H Polarity

Detect

Composite Signal

Separator

HVPASS

MUX

H Polarity Control

HINPOL

FREEHS

HOUT

CLAMP

VOUT

SEPART

MUX

Polarity

Change

Clamp Pulse

Generator

POLINT

HVIN2

MUX

ENFREE

MUX

HVPASS

MUX

VIN

V Polarity Control

VINPOL

VIN2

V Polarity

Detect

V Freq Counter

Free run SYNC

& Test Pattern

Generator

FREEVS

PAT

Fig.5 Block diagram of sync signal processor

Horizontal Frequency Counter

A 13-bit counter is used to measure horizontal frequency.

Name

Addr R/W Initial

Bit 7

HLVL HINPOL HCHG

HFH7 HFH6 HFH5

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

HFREQ_L 0010h

HFREQ_H 0011h

R

xxh

HFL4

HFH4

HFL3

HFH3

HFL2

HFH2

HFL1

HFH1

HFL0

HFH0

Bit Name

Description

HLVL

“1”: Indicates Hsync pin is high level.

“0”: Indicates Hsync pin is low level.

HINPOL “1”: Indicates Hsync input is positive polarity.

“0”: Indicates Hsync input is negative polarity.

HCHG

“1”: If the H period has been changed.

HFH7~ Indicates the Hsync frequency in kHz.

HFH0

HFL4~ When QUICK=”0”, HFL4 ~ HFL0 indicates the Hsync frequency in 31.25Hz unit.

HFL0 When QUICK=”1”, HFL4 ~ HFL1 indicates the Hsync frequency in 62.5Hz.

Weltrend Semiconductor, Inc.

Page 12

WT61P4 v1.03

Monitor Controller

Horizontal polarity detect

The horizontal polarity is detected by sampling HIN signal with a delay time after rising and falling edge

of HIN. When the 126kHz<HIN, sample level at 3.5us – 4.5us after HIN transition edge. When the

23kHz<HIN<126kHz, sample level at 5.5us – 6.5us after HIN transition edge. When the HIN<23khz,

sample level at 8.5us – 9.5us after HIN transition edge.

Horizontal frequency detect

User can choose 16ms or 32ms time interval to count pulse number of Hsync every 16.384ms or

32.768ms. For example, if QUICK bit is set, when a 16.384ms time frame begins, it resets the counter

and starts counting Hsync pulses till 16ms reached, then loads the counter value to HFREQ_H and

HFREQ_L registers. If the H frequency is over 192kHz, the H counter will stop counting.

The sync processor interrupt is generated every 16.384ms or 32.768ms for checking H frequency. This

interrupt will be cleared after reading the HFREQ_H register.

Hsync

Interrupt

Hfreq Counter

Enable

16/32 ms

16.384/32.768 ms

Hfreq Counter

clock

Fig.6 Horizontal Frequency Counter timing

Example of Hsync Frequency Calculation

QUICK=”0”

HFH6..0 HFL4..0 Max. Freq

QUICK=”1”

HFL4..0 Max. Freq Min. Freq

Min. Freq

HFH6..0

$40h

$51h

$00010b 64.0938KHz 64.0312KHz

$00011b 64.1250KHz 64.0625KHz

$10000b 81.5313KHz 81.4687KHz

$10001b 81.5625KHz 81.5000KHz

$10010b 81.5938KHz 81.5312KHz

$10011b 81.6250KHz 81.5625KHz

$40h

$0001xb 64.1250KHz 64.0000KHz

$1000xb 81.5625KHz 81.4375KHz

$1001xb 81.6250KHz 81.5000KHz

$51h

Weltrend Semiconductor, Inc.

Page 13

WT61P4 v1.03

Monitor Controller

Vertical Frequency Counter

A 13-bit counter is used to measure the time interval between two vertical sync pulses.

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

VFREQ_L 0012h

VFREQ_H 0013h

R

xxh

VF7

VLVL

VF6

VF5

VF4

VF12

VF3

VF11

VF2

VF10

VF1

VF9

VF0

VF8

VINPOL VOVF

Bit Name

Description

VLVL

“1”: Indicates Vsync pin is high level.

“0”: Indicates Vsync pin is low level.

VNPOL “1”: Indicates Vsync input is positive polarity. (SEPART in HV_CR1 also make it “1”)

“0”: Indicates Vsync input is negative polarity.

VOVF

“1”: Indicates V counter is overflowed. Vsync frequency is lower than 15.25Hz.

“0”: Vsync frequency is over 15.25Hz.

VF12 ~ VF0 Indicates the Vertical Total Time. Vertical frequency is [125000 / (counter value +1) ] Hz

Vertical polarity detect

Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN. If the level is low,

the polarity is positive (VINPOL=1). If the level is high, the polarity is negative (VINPOL=0). But if

SEPART bit is set, the VINPOL bit is “1” because the Vsync from composite signal separator is always

positive polarity.

Vertical frequency detect

It will be updated every vertical frame. The clock of this counter is 125kHz. So the frequency of Vsync is

[125000 / (counter value + 1)] Hz. When V frequency is lower than 15.25Hz, this counter stops counting

and set VOVF bit to “1”.

Vertical polarity is detected by sampling VIN level at 2.048ms after rising edge of VIN.

Example of Vsync frequency calculation

VF12..0 Max. Freq

Min. Freq

VF12..0

Max. Freq Min. Freq

$05BDh 85.15Hz

$05BEh 85.092Hz

$05BFh 85.034Hz

85.034Hz

84.976Hz

84.918Hz

75.03Hz

74.985Hz

74.94Hz

72.005Hz

71.963Hz

71.921Hz

$0783h

$0784h

$0785h

$0823h

$0824h

$0825h

$1FFDh

$1FFEh

$1FFFh

65.036Hz 64.969Hz

65.003Hz 64.935Hz

64.969Hz 64.901Hz

60.038Hz 59.981Hz

$0681h

$0682h

$0683h

75.12Hz

75.075Hz

75.03Hz

60.01Hz

59.952Hz

59.981Hz 59.923Hz

15.266Hz 15.262Hz

15.264Hz 15.260Hz

15.262Hz 15.258Hz

$06C7h 72.088Hz

$06C8h 72.046Hz

$06C9h 72.005Hz

Weltrend Semiconductor, Inc.

Page 14

WT61P4 v1.03

Monitor Controller

Hsync Period Counter

The H_PERD is an 8-bit counter to detect the cycle time of the Hsync input.

Name

H_PERD 0014h

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

R

xxh

HPRD7 HPRD6 HPRD5 HPRD4 HPRD3 HPRD2 HPRD1 HPRD0

This is an 8-bit counter that uses 6MHz clock to measure time interval between two H pulses. If the H

frequency is lower than 23437.5Hz, this counter will overflow and register H_PERD value is zero.

Hsync Counter In One Vsync Period

Enumerate the H pulses between two V pulses.

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

HF_VL 0015h

HF_VH 0016h

R

00h

x0h

HFV7

HFV6

HFV5

HFV4

HFV3

HFV11 HFV10

HFV2

HFV1

HFV9

HFV0

HFV8

The register can be used as H total.

Vsync overflow control register

The VFQ_OVF is used in blanking for Vertical frequency changed.

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

VFQ_OVF 0010h

W

FFh OVVF7 OVVF6 OVVF5 OVVF4 OVVF3 OVVF2 OVVF1 OVVF0

If the VIN frequency is lower than (7812.5Hz/OVVFn), the vertical frequency overflow flag of the

interrupt will be set.

VFQ_OVF reference table

VFQ_OVF Frequency VFQ_OVF Frequency VFQ_OVF Frequency VFQ_OVF Frequency

78.125 Hz

76.593 Hz

75.120 Hz

73.703 Hz

72.338 Hz

71.022 Hz

69.754 Hz

68.530 Hz

67.934 Hz

66.207 Hz

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

65.104 Hz

64.037 Hz

63.004 Hz

62.004 Hz

61.035 Hz

60.096 Hz

59.185 Hz

58.302 Hz

57.445 Hz

56.612 Hz

140

142

144

146

148

150

152

154

156

158

55.803 Hz

55.017 Hz

54.253 Hz

53.510 Hz

52.787 Hz

52.083 Hz

51.398 Hz

50.730 Hz

50.080 Hz

49.446 Hz

160

162

164

166

168

170

172

174

176

178

48.828 Hz

48.225 Hz

47.637 Hz

47.063 Hz

46.503 Hz

45.955 Hz

45.421 Hz

44.899 Hz

44.389 Hz

43.890 Hz

Weltrend Semiconductor, Inc.

Page 15

WT61P4 v1.03

Monitor Controller

Sync Processor Control Register

The HV_CR1 and HV_CR2 control the HOUT, VOUT and Clamp model.

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

HV_CR1 0011h

HV_CR2 0012h

W

00h ENHOUT ENVOUT HOPOL VOPOL QUICK SEPART ENFREE ENPAT

00h ENCLP CLPEG CLPPO CLPPW1 CLPPW0 SOG HVPASS BYPASS

Bit Name

Description

“1”: Enable HOUT.

“0”: Disable HOUT. Pin is configured as I/O port PD1.

“1”: Enable VOUT.

“0”: Disable VOUT. Pin is configured as I/O port PD0.

“1”: HOUT is positive polarity.

“0”: HOUT is negative polarity.

“1”: VOUT is positive polarity.

“0”: VOUT is negative polarity.

“1”: Select 16ms time interval to count H pulses every 16.384ms.

“0”: Select 32ms time interval to count H pulses every 32.768ms.

When H+V mode, the falling edge of extracted Vsync is synchronized with Hsync leading

edge.

“1”: Enable sync separator circuit and use the extracted Vsync signal as VOUT.

“0”: VOUT pin outputs Vsync from VIN pin

ENHOUT

ENVOUT

HOPOL

VOPOL

QUICK

SEPART

ENFREE Enable free-running sync signal output on HOUT and VOUT pins when this bit is set.

“1”: Enable self-test pattern output on PAT pin when this bit is set.

“0”: Disable test pattern output. Pin is configured as I/O port PB3.

ENPAT

“1”: Enable clamp pulse output on CLAMP pin.

“0”: Disable clamp pulse output. Pin is configured as I/O port PA7.

ENCLP

“1”: Clamp pulse follows HOUT signal’s rising edge.

“0”: Clamp pulse follows HOUT signal’s falling edge.

CLPEG

“1”: Clamp pulse is positive polarity.

“0”: Clamp pulse is negative polarity.

CLPPO

(CLPPW1,CLPPW0)=(0,0) : clamp pulse width=125ns – 208ns

CLPPW1 ~ (CLPPW1,CLPPW0)=(0,1) : clamp pulse width=208ns – 292ns

CLPPW2 (CLPPW1,CLPPW0)=(1,0) : clamp pulse width=458ns – 542ns

(CLPPW1,CLPPW0)=(1,1) : clamp pulse width=958ns – 1042ns

Select composite sync signal input source.

SOG

“1” : Composite sync signal comes from SOGIN pin.

“0” : Composite sync signal comes from HIN pin.

Select bypass HSYNC & VSYNC.

HVPASS “1” : HOUT = HIN & VOUT=VIN without polarity changed.

“0” : HOUT = HIN & VOUT=VIN with polarity changed.

Select bypass the composite signal separator or not.

BYPASS “1” : HOUT pin outputs sync signal bypass the composite signal separator.

“0” : HOUT pin outputs sync signal from the composite signal separator.

Weltrend Semiconductor, Inc.

Page 16

WT61P4 v1.03

Monitor Controller

Output Polarity Control

HOPOL and VOPOL bits control the polarities of HOUT and VOUT. When the bit is “1”, the output

polarity is positive. When the bit is “0”, the output polarity is negative.

HVPASS

HVPASS will deliver the Hsync and Vsync from HIN and VIN to HOUT and VOUT without polarity

changed.

Composite Sync Signal Separator

The composite sync signal separator can handle H+V and H exclusive-OR V signals. It will extract

Vsync signal from HIN or SOGIN input pin by filtering abnormal pulses. The output Vsync signal will be

widened about 4.5~5.5us. The output Hsync will be replaced by 2us pulse during Vsync pulse. Fig.7

shows the relationship of the extracted H and V sync signals.

If inserting the pseudo H pulses (Extracted HS signal) during Vsync pulse is not necessary, set

BYPASS bit can make HOUT pin output waveform the same as Hsync input (Note: polarity can be

controlled by HOPOL bit), set HVPASS can make HOUT pin output waveform fully the same to Hsync

input.

Hsync

Vsync

H+V

H V SERR

Bypass H pulse

Insert H pulse

Bypass H pulse

2us

Extracted HS

Extracted VS

Hsync

Vsync

H V EOR

Bypass H pulse

Insert H pulse

Bypass H pulse

2us

Extracted HS

Extracted VS

Fig.7 Timing relationship of composite SYNC signal separator

Weltrend Semiconductor, Inc.

Page 17

WT61P4 v1.03

Monitor Controller

Free-Run Frequency Control Registers

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

FRH_CR 0013h

FRHD_CR 0014h

FRHB_CR 0015h

FRV_CR 0016h

FRVD_CR 0017h

FRVB_CR 0018h

W

00h

FRH5

FRH4

FRH3

FRH2

FRH1

FRH0

00h FRHB4 FRHD6 FRHD5 FRHD4 FRHD3 FRHD2 FRHD1 FRHD0

00h FRHB3 FRHB2 FRHB1 FRHB0 FRHW3 FRHW2 FRHW1 FRHW0

00h

00h FRVD7 FRVD6 FRVD5 FRVD4 FRVD3 FRVD2 FRVD1 FRVD0

00h FRVB4 FRVB3 FRVB2 FRVB1 FRVB0 FRVW2 FRVW1 FRVW0

FRV7

FRV6

FRV5

FRV4

FRV3

FRV2

FRV1

FRV0

HOUT(VOUT)

PATTERN

FRHW(FRVW)

FRHB(FRVB)

FRHD(FRVD)

FRH(FRV)

Fig. 8 Free-running SYNC signal and test pattern timing

Bit Name

Description

FRH

The FRH defines the horizontal free run frequency as HF_FREE=750K/FRH_CR.

The FRHD defines the time from the horizontal blanking to the pattern end.

FRHD

FRHB

T

_FRHD=FRHD*0.667µs=H display+ H back porch+ H blanking

The FRHB defines the time from the horizontal blanking to the pattern start.

_FRHB=FRHB*0.333µs=H back porch+ H blanking

T

The FRHW defines the time for the horizontal blanking.

T_FRHW=FRHW*0.333µs=H blanking width

The FRV defines the vertical free run frequency as VF_FREE=HF_FREE/(FRV_CR*8)

FRHW

FRV

The FRVD defines the time from the vertical blanking to the vertical pattern end.

FRVD

T

_FRVD=HF_FREE/(FRVD*8)=V display+ V back porch+ V blanking

The FRVB defines the time from the vertical blanking to the pattern start.

_FRVD=HF_FREE/(FRVB*2)=V back porch+ V blanking

The FRVW defines the time for the vertical blanking.

_FRVW=HF_FREE/(FRVW*2)=V blanking width

FRVB

T

FRVW

T

H pulse & period = X + 83.3ns

V pulse & period = 2xn H + 1H

Weltrend Semiconductor, Inc.

Page 18

WT61P4 v1.03

Monitor Controller

FRH reference table

FRH

0

1

2

3

4

5

6

7

Frequency

FRH

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Frequency

46.88 kHz

44.12 kHz

41.67 kHz

39.47 kHz

37.5 kHz

35.71 kHz

34.09 kHz

32.6 kHz

31.25 kHz

30 kHz

28.85 kHz

27.78 kHz

26.79 kHz

25.86 kHz

25 kHz

FRH

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

Frequency

23.44 kHz

22.73 kHz

22.06 kHz

21.43 kHz

20.83 kHz

20.27 kHz

19.74 kHz

19.23 kHz

18.75 kHz

18.29 kHz

17.86 kHz

17.44 kHz

17.05 kHz

16.67 kHz

16.30 kHz

15.96 kHz

FRH

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Frequency

15.63 kHz

15.31 kHz

15 kHz

--

750 kHz

375 kHz

250 kHz

187.5 kHz

150 kHz

125 kHz

107.14 kHz

93.75 kHz

83.33 kHz

75 kHz

68.18 kHz

62.5 kHz

57.69 kHz

53.57 kHz

50 kHz

14.76 kHz

14.42 kHz

14.15 kHz

13.89 kHz

13.64 kHz

13.39 kHz

13.16 kHz

12.93 kHz

12.71 kHz

12.5 kHz

8

9

10

11

12

13

14

15

12.30 kHz

12.10 kHz

11.90 kHz

24.19 kHz

Clamp pulse

Clamp pulse is generated on either rising or falling edge of HOUT pin by setting the CLPEG bit. The

pulse width of clamp is defined by CLPPW bit. Output polarity is specified by CLPPO bit.

(CLPPW1, CLPPW0)=(0,0): clamp pulse width=125ns – 208ns

(CLPPW1, CLPPW0)=(0,1): clamp pulse width=208ns – 292ns

(CLPPW1, CLPPW0)=(1,0): clamp pulse width=458ns – 542ns

(CLPPW1, CLPPW0)=(1,1): clamp pulse width=958ns – 1042ns

HOUT

CLPPO=1

CLPEG=1

CLPPW

CLAMP

CLPPO=0

CLPEG=1

CLPPW

CLPPO=1

CLPEG=0

CLPPW

CLAMP

CLPPO=0

CLPEG=0

CLPPW

Fig. 9 Clamp pulse waveform

Weltrend Semiconductor, Inc.

Page 19

WT61P4 v1.03

Monitor Controller

H Period Interrupt Control

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

HPD_CHG 0019h

W

00h

EN_LMT HCNT2 HCNT1 HCNT0

Bit Name

Description

EN_LMT Enable H period change interrupt.

HCNT The range of the H_PERD changed.

1/2HIN, 1/2VIN control

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

1/2HV_CR 001Ah

W

00h ENH2D ENV2D HVEDG

HVIN2

Bit Name

Description

ENH2D Enable the 1/2 HIN output at the PA5 pin.

ENV2D

HVDEG

HVIN2

Enable the 1/2 VIN output at the PA6 pin.

HIN & VIN trigger edge control.

HVEDG=0: leading edge trigger

HVEDG=1: tailing edge trigger

The duty cycle of both the 1/2HIN and 1/2VIN output are 50%.

Select the 2^ndHIN & VIN as sync processor frequency source.

Weltrend Semiconductor, Inc.

Page 20

WT61P4 v1.03

Monitor Controller

Frequency Divide Function

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

FDM_CON 0040h

W

00h ENFDM FDMEG FDMPOL

FO1M

FO2D

FO3D

Bit Name

Description

“1”: the output is synchronized with rising edge of input.

ENFDM Enable the FDM input and output..

FDMEG

“0”: the output is synchronized with falling edge of input.

“1”: polarity inverted to input.

“0”: polarity same as input.

FDMPOL

FO1M

FO2D

FO3D

Output Frequency = 1x input frequency.

Output Frequency = (1/2) x input frequency.

Output Frequency = (1/3) x input frequency.

The frequency range of FDI is between 20khz and 180khz and the pulse width of (1/3) input frequency

& (1/2) input frequency is a input period (1T).

FDI

FO1M=1

FDMPOL=1

FDO

FO1M=1

FDMPOL=0

FO2D=1

FDMEG=1

FO2D=1

FDMEG=0

FDO

FO3D=1

FDMEG=1

FDMPOL=0

FO3D=1

FDMEG=0

FDMPOL=1

FDO

Fig. 10 FDI and FDO waveform

Weltrend Semiconductor, Inc.

Page 21

WT61P4 v1.03

Monitor Controller

DDC & Alignment I2C Interface

DDC Status Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DDC_STA1

DDC_STA2

0024h

0025h

R

01h ALGRDY

00h

BB

DDC2

FIRST

STOP ALGRW MATCH RXNAK1

IN_CMD WR_D3

Bit Name

Description

ALGRDY DDC_AR1 or DDC_AR2 ready. Write the DDC_AR1 will clear this flag.

BB

Bus busy.

“1”: DDC2 selected

“0”: DDC1 selected

DDC2

FIRST

STOP

Indicates the first byte (address) is received when this bit is set.

Indicates STOP condition is received when this bit is set.

Indicates the received R/W bit after 7-bit address.

ALGRW “1”: Read

“0”: Write

0: DDC_ADR1

1: DDC_ADR2

MATCH

RXNAK1 Received the NAK by DDC_AR1 or DDC_AR2.

DDC_ADR0, DDC_ADR1 or DDC_ADR2 have been received.

Written 0 to DDC2 will clear this flag.

IN_CMD

H/W DDC data has been updated.

Written 1 to CLR_WD3 then 0 to CLR_WD3 will clear this flag.

WR_D3

DDC Control Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DDC_CON1 0024h

DDC_CON2 0025h

W

00h ENDDC

80h RAMAS1 RAMAS0

DDC2

ENRAMA

TX

TXNAK1

ENRAMB

RAMBS

CLR_ADR CLR_WD WR_EN

3

Bit Name

Description

ENDDC Enable the H/W DDC function of DDC_AR0.

DDC2=0: DDC1 selected

DDC2=1: DDC2 selected

DDC2

“1”: Set transmit direction.

“0”: Set received direction.

TX

TXNAK1 Transmit NAK and IRQ may happen with DDC_AR1 and DDC_AR2.

RAMAS1=0, RAMAS0=0: 128bytes format H/W DDC from 0200h to 027Fh

ENRAMA RAMAS1=0, RAMAS0=1: 128bytes format H/W DDC from 0280h to 02FFh

RAMAS1=1, RAMAS0=0: 128bytes format H/W DDC from 0300H to 037FH (default)

RAMBS1=0: 256bytes format H/W DDC from 0200h to 02FFh (default)

RAMBS1=1: 256bytes format H/W DDC from 0280h to 037Fh

ENRAMB

CLR_ADR Reset all DDC address pointer to 0.

CLR_WD3 Clear the flag indicated that the H/W DDC data has been changed.

WR_EN Enable the H/W DDC_WRITE.

Weltrend Semiconductor, Inc.

Page 22

WT61P4 v1.03

Monitor Controller

DDC receive & transmit buffer register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DDC_RTX 0026h R/W FFh

DRX7

DRX6

DRX5

DRX4

DRX3

DRX2

DRX1

DRX0

DDC port control register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DDC_AAE 0027h

DDC_ABE 0028h

DDC_AR0 0029h

DDC_AR1 002Ah

DDC_AR2 002Bh

W

FFh ENADRA7 ENADRA6 ENADRA5 ENADRA4 ENADRA3 ENADRA2 ENADRA1 ENADRA0

00h ENADRB7 ENADRB6 ENADRB5 ENADRB4 ENADRB3 ENADRB2 ENADRB1 ENADRB0

X0h DAR07 DAR06 DAR05 DAR04

--

ENAR0

X0h DAR17 DAR16 DAR15 DAR14 DAR13 DAR12 DAR11 ENAR1

X0h DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 ENAR2

Bit Name

Description

Optional address as DDC_AR0 bit0~bit3. Also used as 128 bytes H/W DDC address

option.

DDC_AAE

DDC_ABE

DDC_AR0

Optional address as DDC_AR0 bit0~bit3. Also used as 256 bytes H/W DDC address

option.

The I²C slave address0 defines by user as DDC port. The bits from bit0 to bit3 are

defined by DDC_AAE and DDC_ABE. Refer to 24h and 25h for hardware DDC setting.

DDC_AR1 The I²C slave address1 defines by user and shares with DDC port.

DDC_AR2 The I²C slave address2 defines by user and shares with DDC port.

(1) DDC2 slave I, II write mode :

START

Pull low SCL

STOP

SCL

SDA

0

A

Slave Address

RX DATA 1

RX DATA 2

SDA ouput

ALGRDY

write 2AH

ALGRDY=1

BB=1

ALGRDY=1

BB=1

ALGRDY=1

BB=1

ALGRDY=1

BB=0

DDC2=1

FIRST=1

FIRST=0

STOP=0

STOP=1

ALGRW=0

MATCH=0,1

NXNAK1=0

ALGRW=0

MATCH=0,1

NXNAK1=0

ALGRW=0

MATCH=0,1

NXNAK1=0

ALGRW=0

MATCH=0,1

NXNAK1=0

(2) DDC2 slave I, II read mode :

START

Pull low SCL

STOP

SCL

SDA

1

A

N

Slave Address

TX DATA 1

TX DATA 2

SDA ouput

ALGRDY

TX DATA 1

write 2AH

set TX

ALGRDY=1

BB=1

ALGRDY=1

BB=1

ALGRDY=1

BB=1

ALGRDY=1

BB=0

DDC2=1

FIRST=1

FIRST=0

STOP=0

STOP=1

ALGRW=1

MATCH=0,1

NXNAK1=0

ALGRW=1

MATCH=0,1

NXNAK1=0

ALGRW=1

MATCH=0,1

NXNAK1=0

ALGRW=0

MATCH=0,1

NXNAK1=0

Weltrend Semiconductor, Inc.

Page 23

WT61P4 v1.03

Monitor Controller

START

DDC data =>

DDC SRAM

set ENDDC

slave 0 address =>

DDC_AR0

slave I address =>

DDC_AR1

slave II address =>

DDC_AR2

No

ALGRDY=1 ?

Yes

No

MATCH=0 ?

Yes

slave II address

subprogram

FIRST=1 ?

Yes

No

STOP=1 ?

Yes

No

ALGRW=1 ?

Yes

No

ALGRW=1 ?

slave I address

=>DDC_AR1

Yes

set TX

read DDC_RTX

sended data =>

DDC_RTX

No

RXNACK1=0 ?

Yes

slave I address

=>DDC_AR1

END

slave I address

=>DDC_AR1

sended data =>

DDC_RTX

slave I address

=>DDC_AR1

Weltrend Semiconductor, Inc.

Page 24

WT61P4 v1.03

Monitor Controller

Master/Slave I²C Interface

I²C interface Status Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_STA 0020h

R

22h

BB

SFIRST SSTOP

SRW RXNAK2 I2CRDY

Bit Name

Description

BB

“1”: Bus busy.

“0”: Bus idle. Both SDA2 and SCL2 pins keep in high level for 5us after STOP condition.

SFIRST This bit is set when received START and first byte in slave mode.

SSTOP This bit is set when received STOP condition in slave mode.

SRW

Received R/W bit in slave mode.

“1”: Read command is received.

“0”: Write command is received.

RXNAK2 “1”: NACK is received.

“0”: ACK is received.

I2CRDY This bit is set when a byte is received, transmitted or STOP condition is detected.

I²C interface Control Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_CON 0020h

W

02h

ENI2C MCLK1 MCLK0 MSTR MSTOP I2CRW TXNAK2 SLAVE

Bit Name

Description

“1”: Enable I2C interface.

“0”: Pin PB5 and pin PB4 are I/O port.

Select SCL clock in master mode

“00”: 400KHz

ENI2C

MCLK1, 0 “01”: 200KHz

“10”: 100KHz

“11”: 50KHz

MSTR

Output START condition in master mode when this bit is set.

MSTOP Output STOP condition in master mode when this bit is set.

“0”: Transmitter, “1”: Receiver in master mode.

I2CRW

“1”: Transmitter, “0”: Receiver in slave mode

(“0”: I2C write mode, “1”: I2C read mode.)

“1”: Output NACK.

“0”: Output ACK. It will pull low the SDA2 pin on acknowledge bit.

“1”: Slave mode.

TXNAK2

SLAVE

“0”: Master mode.

Weltrend Semiconductor, Inc.

Page 25

WT61P4 v1.03

Monitor Controller

I²C interface Transmit/Receive Buffer Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_TX 0021h

I2C_RX 0021h

W

R

xxh

MTX7

MRX7

MTX6

MRX6

MTX5

MRX5

MTX4

MRX4

MTX3

MRX3

MTX2

MRX2

MTX1

MRX1

MTX0

MRX0

I²C interface Address Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

I2C_ADR 0022h

W

X0h

SAR7

SAR6

SAR5

SAR4

SAR3

SAR2

SAR1 DLYHLD

Bit Name

Description

SAR7 ~ SAR1 7-bit address to be compared in slave mode.

DLYHLD Delay 1/2 SCL clock hold time.

Weltrend Semiconductor, Inc.

Page 26

WT61P4 v1.03

Monitor Controller

I²C Data Sequence

(1) Master write mode :

START

MSCL Pull low

STOP

SCL

SDA

0

A

Slave Address

TX DATA 1

TX DATA 2

internal MSDA

I2CRDY

TX DATA 1

write 22H

set MSTOP

set MSTR

BB=1

RXNAK2=0

I2CRDY=1

BB=1

RXNAK2=0

I2CRDY=1

BB=1

RXNAK2=0

I2CRDY=1

BB=1

(2) Master read mode :

START

MSCL Pull low

STOP

SCL

SDA

1

A

N

Slave Address

RX DATA 1

RX DATA 2

internal MSDA

I2CRDY

write 22H

^setMSTOP

set MSTR

set I2CRW

set TXNAK2

BB=1

RXNAK2=1

I2CRDY=1

BB=1

RXNAK2=0

I2CRDY=1

BB=1

RXNAK2=1

I2CRDY=1

BB=1

(3) Slave write mode :

START

MSCL Pull low

STOP

SCL

SDA

0

A

Slave Address

RX DATA 1

RX DATA 2

internal MSDA

I2CRDY

write 22H

BB=1

SFIRST=1

SSTOP=0

SRW=0

RXNAK2=0

I2CRDY=1

BB=1

SFIRST=0

SSTOP=0

SRW=0

RXNAK2=0

I2CRDY=1

BB=1

SFIRST=0

SSTOP=1

SRW=0

SFIRST=0

SSTOP=0

SRW=0

RXNAK2=0 RXNAK2=0

I2CRDY=1 I2CRDY=1

(4) Slave read mode :

START

MSCL Pull low

STOP

SCL

1

A

N

SDA

internal MSDA

I2CRDY

Slave Address

TX DATA 1

TX DATA 2

write 22H

^setI2CRW

BB=1

SFIRST=1

SSTOP=0

SRW=1

RXNAK2=0

I2CRDY=1

BB=1

SFIRST=0

SSTOP=0

SRW=1

RXNAK2=0

I2CRDY=1

BB=1

SFIRST=0

SSTOP=0

SRW=1

BB=1

SFIRST=0

SSTOP=1

SRW=1

RXNAK2=1 RXNAK2=1

I2CRDY=1 I2CRDY=1

Weltrend Semiconductor, Inc.

Page 27

WT61P4 v1.03

Monitor Controller

Master I2C Flow Chart

START

set ENMI2C

select I2C clock

(MCLK1,MCLK0)

No

BB=0?

Yes

No

time out ?

clear I2CRW &

TXNAK2

sended slave address

Yes

=>MI2C_RTX

set MSTR

hardware fail

No

I2CRDY=1?

Yes

No

RXNAK2=0?

Yes

set MSTOP

"XX"=>MI2C_ADR

sended data

=>MI2C_RTX

"XX"=>MI2C_ADR

READ mode

set I2CRW

W RITE mode

Yes

read last byte ?

No

Yes

I2CRDY=1?

set TXNAK2

"XX"=>MI2C_ADR

Yes

RXNAK2=0?

No No

I2CRDY=1?

Yes

I2CRDY=1?

Yes

send all bytes ?

read MI2C_RTX

set MSTOP

No

set MSTOP

"XX"=>MI2C_ADR

sended data

=>MI2C_RTX

"XX"=>MI2C_ADR

END

Weltrend Semiconductor, Inc.

Page 28

WT61P4 v1.03

Monitor Controller

Master I2C (reSTART mode) Flow Chart

START

set ENMI2C

select I2C clock

(MCLK1,MCLK0)

No

BB=0?

Yes

No

time out ?

clear I2CRW &

TXNAK2

sended slave address

Yes

=>MI2C_TX

set MSTR

hardware fail

No

I2CRDY=1?

Yes

No

RXNAK2=0?

Yes

sended data

=>MI2C_TX

"XX"=>MI2C_ADR

No

I2CRDY=1?

Yes

No

RXNAK2=0?

Yes

set I2CRW

sended slave address

=>MI2C_TX

set MSTR

Yes

read last byte ?

No

"XX"=>MI2C_ADR

set TXNAK2

"XX"=>MI2C_ADR

No

I2CRDY=1?

Yes

No No

I2CRDY=1?

Yes

RXNAK2=0?

Yes

No

read MI2C_RX

set MSTOP

"XX"=>MI2C_ADR

END

Weltrend Semiconductor, Inc.

Page 29

WT61P4 v1.03

Monitor Controller

Salve I2C Flow Chart

START

set ENMI2C

slave address

=>MI2C_ADR

set SLAVE

No

I2CRDY=1?

Yes

No

SFIRST=1?

Yes

No

SSTOP=1?

No

SRW=1?

Yes

No

SRW=1?

Yes

slave address

=>MI2C_ADR

Yes

set I2CRW

sended data =>

MI2C_RTX

read MI2C_RTX

No

RXNAK2=0?

END

Yes

sended data =>

MI2C_RTX

slave address

=>MI2C_ADR

Weltrend Semiconductor, Inc.

Page 30

WT61P4 v1.03

Monitor Controller

Interrupt Control

Interrupt flag register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

INT_FLG 002Ch

INT_FLG2 002Dh

R

00h IF_DDC IF_MI2C

00h IF_POL IF_OVV

IF_SYNC IF_IRQ2 IF_IRQ1 IF_VSO IF_VIN

IF_IR

IF_HCHG

These interrupt sources are connected to CPU8051 /INT1

Bit Name

Description

IF_DDC “1” indicate DDC interrupt has been triggered.

IF_MI2C “1” indicate I2C interrupt has been triggered.

IF_SYNC “1” indicate Hsync counter ready interrupt has been triggered.

IF_IRQ2 “1” indicate IRQ2 interrupt has been triggered.

IF_IRQ1 “1” indicate IRQ1 interrupt has been triggered.

IF_VSO “1” indicate Vsync output leading edge interrupt has been triggered.

IF_VIN

“1” indicate Vsync input leading edge interrupt has been triggered.

IF_POL “1” indicate Hsync or Vsync input polarity changed interrupt has been triggered.

IF_OVV “1” indicate Vsync input overflow interrupt has been triggered.

(Refer to Addr 10h VFQ_OVF Vsync overflow control register)

IF_HCHG “1” indicate Hsync input period changed interrupt has been triggered.

(Refer to Addr 19h H period interrupt control)

IF_IR

“1” indicate IR event interrupt has been triggered.

Interrupt enable register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

IE_SYNC

IE_IR

Bit 3

Bit 2

Bit 1

Bit 0

INT_EN 002Ch

INT_EN2 002Dh

W

00h IE_DDC IE_MI2C

00h IE_POL IE_OVV

IE_IRQ2 IE_IRQ1 IE_VSO IE_VIN

IE_HCHG

Bit Name

Description

IE_DDC Enable DDC interrupt when this bit is set.

IE_MI2C Enable I2C interrupt when this bit is set.

IE_SYNC Enable Hsync ready interrupt when this bit is set.

IE_IRQ2 Enable IRQ2 interrupt when this bit is set.

IE_IRQ1 Enable IRQ1 interrupt when this bit is set.

IE_VSO Enable VOUT interrupt when this bit is set.

IE_VIN

Enable VIN interrupt when this bit is set.

IE_POL Enable POLINT interrupt when this bit is set.

IE_OVV Enable V overflow interrupt when this bit is set.

IE_HCHG Enable HCHG interrupt when this bit is set.

IE_IR

Enable IR interrupt when this bit is set.

Weltrend Semiconductor, Inc.

Page 31

WT61P4 v1.03

Monitor Controller

Interrupt Source Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

INT_SRC 002Eh

R

00h POLINT OVVINT

SYNC

IRQ2

IRQ1

VSO

VIN

Bit Name

Description

POLINT “1”: Polarity Change

OVVINT “1”: Vsync input is lower than OVVFn

SYNC

IRQ2

IRQ1

VSO

VIN

“1”: Hsync detect counter is ready

“1”: IRQ2 has been triggered.

“1”: IRQ1 has been triggered.

“1”: Vsync output leading edge has been triggered.

“1”: Vsync input leading edge has been triggered.

Interrupt Control Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

CLR_IRQ2 CLR_IRQ1

IRQ_CON1 002Eh

IRQ_CON2 002FH

W

00h CLR_POL CLR_OV

00h

CLR_VSO CLR_VIN

IRQ1_EG

IRQ1_RF

IRQ2_EG

IRQ2_RF

Bit Name

Description

CLR_POL Set CLR_POL to clear polarity changed interrupt event.

CLR_OV Set CLR_OV to clear Vsync input overflow interrupt event.

CLR_IRQ2 Set CLR_IRQ2 to clear the IRQ2 interrupt event.

CLR_IRQ1 Set CLR_IRQ1 to clear the IRQ1 interrupt event.

CLR_VSO Clear VOUT interrupt when this bit is set.

CLR_VIN Clear Vsync input interrupt when this bit is set.

IRQ2_EG=0, IRQ2_RF=x, IRQ2 will be triggered by a low level over 1us.

IRQ2_EG=1, IRQ2_RF=0, IRQ2 will be triggered by a falling edge.

IRQ2_EG=1, IRQ2_RF=1, IRQ2 will be triggered by a rising edge.

IRQ1_EG=0, IRQ1_RF=x, IRQ1 will be triggered by a low level over 1us.

IRQ1_EG=1, IRQ1_RF=0, IRQ1 will be triggered by a falling edge.

IRQ1_EG=1, IRQ1_RF=1, IRQ1 will be triggered by a rising edge.

IRQ2_EG&

IRQ2_RF

IRQ1_EG&

IRQ1_RF

Weltrend Semiconductor, Inc.

Page 32

WT61P4 v1.03

Monitor Controller

Interrupt Control and Clear

DDC interface interrupt

Interrupt Condition

Clear Interrupt

Receive one byte in DDC2 mode.

Transmit data buffer is empty in DDC2 mode.

Received a STOP condition in DDC2 mode.

Write address to DDC_AR1 (Addr 2Ah) register.

I²C interface interrupt

Interrupt Condition

Clear Interrupt

After transmit a byte.

After receive a byte.

Received a STOP condition when slave mode.

Write address to MI2C_AR register.

Sync Processor interrupt

Interrupt Condition

Clear Interrupt

Latch a new H frequency to HFREQ_H and Read HFREQ_H Register.

HFREQ_L register every 32.768ms or 16.384ms.

IRQ1 pin interrupt

Interrupt Condition

NIRQ1 has been triggered.

Clear Interrupt

Write “1” to CLR_IRQ1 bit in IRQ_CON1 register

then write “0” to CLR_IRQ1.

IRQ2 pin interrupt

Interrupt Condition

Clear Interrupt

NIRQ2 has been triggered.

Write “1” to CLR_IRQ2 bit in IRQ_CON1 register

then write “0” to CLR_IRQ2.

Vsync output leading edge interrupt

Interrupt Condition

Clear Interrupt

Leading edge of VOUT pin signal.

Write “1” to CLR_VSO bit in IRQ_CON1 register

then write “0” to CLR_VSO.

Vsync input leading edge interrupt

Interrupt Condition

Clear Interrupt

Leading edge of VIN pin signal.

Write “1” to CLR_VIN bit in IRQ_CON1 register then

write “0” to CLR_VSI.

Polarity change interrupt

Interrupt Condition

Clear Interrupt

HIN or VIN polarity has been changed.

Write “1” to CLR_POL bit in IRQ_CON1 register

then write “0” to CLR_POL.

Weltrend Semiconductor, Inc.

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Monitor Controller

Vsync input overflow interrupt

Interrupt Condition

Clear Interrupt

VIN is lower than VFQ_OVF.

Write “1” to CLR_OV bit in IRQ_CON1 register then

write “0” to CLR_OV.

Hsync input change interrupt

Interrupt Condition

Clear Interrupt

The new H_PERD is not in the old H_PERD ± Read H_PERD (Addr 14h) to clear this interrupt and

H_CNT (addr 19h).

HCHG.

IR interrupt

Interrupt Condition

Clear Interrupt

Receive DATA.

Receive the REPEAT code.

Read IR_DATA (Addr 43h) will clear this bit.

Write “1” to CLR_KP bit in IR_CTL (Addr 42h)

register then write “0” to CLR_KP.

Transmit timing error.

Write “1” to CLR_ERR bit in IR_CTL (Addr 42h)

register then write “0” to CLR_ERR.

Weltrend Semiconductor, Inc.

Page 34

WT61P4 v1.03

Monitor Controller

A/D Converter

The Analog-to-Digital Converter (ADC) is 8-bit resolution with four selectable input channels. When

EN_CHn is set, PCn is configured as ADC input and PCn pull-high resistor is disabled. When CHn is

set, it will reset the ADC_DA register and start converting. After the conversion is done, the ADRDY bit

is set and valid data is stored in ADC_DA. The total conversion time is 12us. If program wants to make

a new conversion, it writes CHn register again and it will start another conversion.

ADC Data Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

ADC_DA 001Ch

ADC_RD 001Dh

R

xxh

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

xxh ADRDY

Bit Name

Description

ADRDY ADC data is ready to read when this bit is set.

AD7 ~ AD0 ADC data.

ADC Channel Select Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

ADC_CH 001Ch

W

00h EN_CH3 EN_CH2 EN_CH1 EN_CH0

CH3

CH2

CH1

CH0

Bit Name

Description

EN_CH3 “1”: PC3 is configured as ADC interface. (tri-state with no I/O function).

“0”: PC3 is configured as I/O port.

EN_CH2 “1”: PC2 is configured as ADC interface. (tri-state with no I/O function).

“0”: PC2 is configured as I/O port.

EN_CH1 “1”: PC1 is configured as ADC interface. (tri-state with no I/O function).

“0”: PC1 is configured as I/O port.

EN_CH0 “1”: PC0 is configured as ADC interface. (tri-state with no I/O function).

“0”: PC0 is configured as I/O port.

CH3

CH2

CH1

CH0

Select AD3 pin to ADC convert when this bit is set.

Select AD2 pin to ADC convert when this bit is set.

Select AD1 pin to ADC convert when this bit is set.

Select AD0 pin to ADC convert when this bit is set.

Note: The EN_CHn must be set before CHn.

Weltrend Semiconductor, Inc.

Page 35

WT61P4 v1.03

Monitor Controller

CH3

CH2

CH1

CH0

AD3

AD2

AD1

AD0

Comparator

Resistor Array

ADRDY

ADC 8-bits Control

Fig. 11 Block diagram of ADC

START

set EN_CH3(W1C.7) or

EN_CH2(W1C.6) or

EN_CH1(W1C.5) or

EN_CH0(W1C.4)

set CH3(W1C.3) or

CH2(W1C.2) or

CH1(W1C.1) or

CH0(W1C.0)

No

ADRDY(R1D.7)=1 ?

Yes

read ADC_DA(R1C)

Weltrend Semiconductor, Inc.

Page 36

WT61P4 v1.03

Monitor Controller

Remote Control IR Detector

IR Control Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

CLR_ERR

IR_CTL 0042h

W

00h

ENIR

IN_HL

CLR_KP

Bit Name

Description

ENIR

IN_HL

Enable remote control IR function.

IR input H or L trigger, IN_HL=1: H trigger, IN_HL=0: L trigger.

CLR_KP Clear IR_KEEP interrupt.

CLR_ERR Clear IR_ERR interrupt.

IR Status & Data

Name

Addr R/W Initial

Bit 7

IRRDY IR_RD IR_KEEP IR_ERR

IRD7 IRD6 IRD5 IRD4

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

IRDCNT1 IRDCNT0

Bit 0

IR_STA 0042h

IR_DATA 0043h

R

00h

IRD3

IRD2

IRD1

IRD0

Bit Name

Description

IRRDY

IR_RD

IR event ready when (a) receive DATA (b) IR_KEEP=1 (c) IR_ERR=1, data time out.

“1” receive DATA. Read IR_DATA (Addr 43h) will clear this bit.

IR_KEEP “1” receive the REPEAT code.

IR_ERR “1” transmit timing error. Data time out <0.56ms or >1.69ms.

IRDCNTx Byte count of the received IR data.

IRD7~IRD0 Receive DATA.

CODE

DATA

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

9ms

4.5ms

IRRDY=1

IR_RD=1

IRDCNT1=0

IRDCNT0=0

IR_RD=1

IRDCNT1=0

IRDCNT0=1

IR_RD=1

IRDCNT1=1

IRDCNT0=0

IR_RD=1

IRDCNT1=1

IRDCNT0=1

0 1

9ms

IRRDY=1

IR_KEEP=1

IRRDY=1

IR_ERR=1

Weltrend Semiconductor, Inc.

Page 37

WT61P4 v1.03

Monitor Controller

Watchdog Timer

Watchdog Timer Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

WDT

001Eh 00h DISWDT

W

WDT1

WDT0

Bit Name

Description

DISWDT “1” : Disable Watchdog Timer.

“0” : Enable Watchdog Timer.

(WDT1, WDT0)=(0,0): reset time = 1.536s

(WDT1, WDT0)=(0,1): reset time = 3.072s

(WDT1, WDT0)=(1,0): reset time = 48ms

(WDT1, WDT0)=(1,1): reset time = 96ms

WDT

Power Saving Control

Power Saving Control Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DDC_WK

PSC_CTL 0041h

W

00h IRQ1_WK IRQ2_WK

H_in1&SOG

Vin1

Hin2

Vin2

Bit Name

Description

IRQ1_WK NIRQ1 falling edge trigger to wake up OSC.

IRQ2_WK NIRQ2 falling edge trigger to wake up OSC.

DDC_WK SCL, SDA falling edge trigger to wake up OSC.

Hin1_WK& Hin1, SOG falling edge trigger to wake up OSC.

SOG_WK

Vin1_WK Vin1 falling edge trigger to wake up OSC.

Hin2_WK Hin2 falling edge trigger to wake up OSC.

Vin2_WK Vin2 falling edge trigger to wake up OSC.

Bit0

Must be 0.

It will clear all PSC_CTL trigger latch buffer when write data to the register 41H. The trigger latch buffer

must be cleared before entering the power down mode. After the external trigger signal received, CPU

delays 64ms and wakes up..

Function Configuration Register

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PWMCLK

OTH_CTL1 004Eh

W

00h

ENT0T1

ICLK

Bit Name

Description

ENT0T1 “1”: Enable the 8031 T0 and T1 source by external.

“0”: Disable.

“1”: PWM clock is 1.5MHz.

“0”: PWM clock is 12MHz.

PWMCLK

“1”: The clock of CPU is the same to OSCI but the clock of system is OSCI/2.

“0”: The clock of CPU and system is the same as OSCI.

ICLK

Weltrend Semiconductor, Inc.

Page 38

WT61P4 v1.03

Monitor Controller

PWM

PWM0: 12-bit PWM and +5/3.3V push-pull output, shared with I/O.

PWM1 ~ PWM15: 8-bit PWM and +5/3.3V push-pull output, shared with I/O.

The corresponding PWM register controls the PWM duty cycle. Duty cycle range is from 0/256 to

255/256. PWM0 duty cycle range is from 0/4096 to 4095/4096.

LSB 3-bit of the PWM1~PWM15 will extend Tpwm to the frame0~7, Fig.

000: no Tpwm extended.

001: extended Tpwm to the frame 4.

010: extended Tpwm to the frame 2 and 6.

011: extended Tpwm to the frame 2, 4 and 6.

100: extended Tpwm to the frame 1, 3, 5 and 7.

101: extended Tpwm to the frame 1, 3, 4, 5 and 7.

110: extended Tpwm to the frame 1, 2, 3, 5, 6 and 7.

111: extended Tpwm to the frame 1, 2, 3, 4, 5, 6 and 7.

PWMCLK=0, Tpwm=1/12MHz. PWMCLK=1, Tpwm=1/1.5MHz. Tframe=32Tpwm.

MSB 5-bit of the PWM1~PWM15: 0/32 to 31/32 duty of the Tframe.

LSB 6-bit of the PWM0 will extend Tpwm to the frame0~63, Fig.

000000 : no Tpwm extended.

000001 : extended Tpwm to the frame 32.

000010 : extended Tpwm to the frame 16 and 48.

000100 : extended Tpwm to the frame 8, 24, 40 and 56.

001000 : extended Tpwm to the frame 4, 12, 20, 28, 36, 44, 52 and 60.

010000 : extended Tpwm to the frame 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58 and 62.

100000 : extended Tpwm to the frame 1, 3, 5, 7, 9, ………57, 59, 61 and 63.

PWMCLK=0, Tpwm=1/12MHz. PWMCLK=1, Tpwm=1/1.5MHz. Tframe=64Tpwm.

MSB 6-bit of the PWM0: 0/64 to 63/64 duty of the Tframe.

Frame 0 Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 Frame 7

Tpwm

PWM=00001000B

32 Tpwm

256 Tpwm

Tpwm

PWM=00000001B

PWM=00000010B

PWM=00000100B

Tpwm

2Tpwm

Tpwm

PWM=00001001B

PWM=00010010B

2Tpwm

3Tpwm

2Tpwm

2

Tpwm

2Tpwm

3Tpwm

2Tpwm

Fig. 14 PWM output waveform

Weltrend Semiconductor, Inc.

Page 39

WT61P4 v1.03

Monitor Controller

PWM Registers

Name

PWM0L 000Ch R/W 00h

PWM0H 000Dh R/W 80h PWM0₁₁PWM0₁₀PWM0₉PWM0₈PWM0₇PWM0₆PWM0₅PWM0₄

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

PWM0₃PWM0₂PWM0₁PWM0₀

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

0031h R/W 80h PWM1₇PWM1₆PWM1₅PWM1₄PWM1₃PWM1₂PWM1₁PWM1₀

0032h R/W 80h PWM2₇PWM2₆PWM2₅PWM2₄PWM2₃PWM2₂PWM2₁PWM2₀

0033h R/W 80h PWM3₇PWM3₆PWM3₅PWM3₄PWM3₃PWM3₂PWM3₁PWM3₀

0034h R/W 80h PWM4₇PWM4₆PWM4₅PWM4₄PWM4₃PWM4₂PWM4₁PWM4₀

0035h R/W 80h PWM5₇PWM5₆PWM5₅PWM5₄PWM5₃PWM5₂PWM5₁PWM5₀

0036h R/W 80h PWM6₇PWM6₆PWM6₅PWM6₄PWM6₃PWM6₂PWM6₁PWM6₀

0037h R/W 80h PWM7₇PWM7₆PWM7₅PWM7₄PWM7₃PWM7₂PWM7₁PWM7₀

0038h R/W 80h PWM8₇PWM8₆PWM8₅PWM8₄PWM8₃PWM8₂PWM8₁PWM8₀

0039h R/W 80h PWM9₇PWM9₆PWM9₅PWM9₄PWM9₃PWM9₂PWM9₁PWM9₀

PWM10 003Ah R/W 80h PWM10₇PWM10₆PWM10₅PWM10₄PWM10₃PWM10₂PWM10₁PWM10₀

PWM11 003Bh R/W 80h PWM11₇PWM11₆PWM11₅PWM11₄PWM11₃PWM11₂PWM11₁PWM11₀

PWM12 003Ch R/W 80h PWM12₇PWM12₆PWM12₅PWM12₄PWM12₃PWM12₂PWM12₁PWM12₀

PWM13 003Dh R/W 80h PWM13₇PWM13₆PWM13₅PWM13₄PWM13₃PWM13₂PWM13₁PWM13₀

PWM14 003Eh R/W 80h PWM14₇PWM14₆PWM14₅PWM14₄PWM14₃PWM14₂PWM14₁PWM14₀

PWM15 003Fh R/W 80h PWM15₇PWM15₆PWM15₅PWM15₄PWM15₃PWM15₂PWM15₁PWM15₀

PWM_EN1 000Eh

PWM_EN2 000Fh

W

00h EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1 EPWM0

EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10

00h

EPWM9 EPWM8

Bit Name

Description

PWMX₇~ PWMX₀Select duty cycle of PWM1~15 output.

00000000: duty cycle = 0

00000001: duty cycle = 1/256

00000010: duty cycle = 2/256

:

11111110: duty cycle = 254/256

11111111: duty cycle = 255/256

PWM0₁₁~ PWM0₀Select duty cycle of PWM0 output.

duty cycle = 0/4096 ~ 4095/4096

EPWMx

Set the corresponding EPPWMx will enable the PWM output. (x from 0 to 15)

Weltrend Semiconductor, Inc.

Page 40

WT61P4 v1.03

Monitor Controller

WT61P4 Register Map:

Name

Addr R/W Initial

Bit 7

PA7

Bit 6

Bit 5

PA5

Bit4

PA4

Bit 3

PA3

Bit 2

PA2

Bit 1

PA1

Bit 0

PA0

PA_CTRL 0000h R/W 00h PA7OE PA6OE PA5OE PA4OE PA3OE PA2OE PA1OE PA0OE

PA_DATA 0001h R/W ffh

PB_CTRL 0002h R/W 00h

PB_DATA 0003h R/W xfh

PA6

PB6OE PB5OE PB4OE PB3OE PB2OE PB1OE PB0OE

PB6 PB5 PB4 PB3 PB2 PB1 PB0

PC_CTRL 0004h R/W 00h PC7OE PC6OE PC5OE PC4OE PC3OE PC2OE PC1OE PC0OE

PC_DATA 0005h R/W ffh PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD_CTRL 0006h R/W 00h PD7OE PD7OE PD5OE PD4OE PD3OE PD2OE PD1OE PD0OE

PD_DATA 0007h R/W ffh

PE_CTRL 0008h R/W 00h

PE_DATA 0009h R/W xfh

PD7

PD6

PD5

PD4

PD3

PE3OE PE2OE PE1OE PE0OE

PE3 PE2 PE1 PE0

00h PD7HE PD6HE PD5HE PD4HE PD3HE PD2HE PD1HE PD0HE

PD2

PD1

PD0

PD_CTRL2 000Ah

HFREQ_L 0010h

HFREQ_H 0011h

VFREQ_L 0012h

VFREQ_H 0013h

H_PERD 0014h

HF_VL 0015h

HF_VH 0016h

VFQ_OVF 0010h

HV_CR1 0011h

W

R

W

xxh

HLVL HINPOL HCHG

HOVF

VF7

HFL4

HFH4

VF4

HFL3

HFH3

VF3

HFL2

HFH2

VF2

HFL1

HFH1

VF1

HFL0

HFH0

VF0

HFH6

VF6

HFH5

VF5

VLVL VINPOL VOVF

VF12

VF11

VF10

VF9

VF8

xxh HPRD7 HPRD6 HPRD5 HPRD4 HPRD3 HPRD2 HPRD1 HPRD0

00h

FFh OVVF11 OVVF10 OVVF9 OVVF8 OVVF7 OVVF6 OVVF5 OVVF4

00h ENHOU ENVOUT HOPOL VOPOL QUICK SEPART ENFREE ENPAT

T

HFV7

HFV6

HFV5

HFV4

HFV3

HFV11 HFV10

HFV2

HFV1

HFV9

HFV0

HFV8

HV_CR2 0012h

FRH_CR 0013h

FRHD_CR 0014h

FRHB_CR 0015h

FRV_CR 0016h

FRVD_CR 0017h

FRVB_CR 0018h

HPD_CHG 0019h

1/2HV_CR 001Ah

ADC_DA 001Ch

ADC_CH 001Ch

ADC_RD 001Dh

W

R

00h ENCLP CLPEG CLPPO CLPPW1 CLPPW0 SOG HVPASS BYPASS

00h

FRH5

FRH4

FRH3

FRH2

FRH1

FRH0

00h FRHB4 FRHD6 FRHD5 FRHD4 FRHD3 FRHD2 FRHD1 FRHD0

00h FRHB3 FRHB2 FRHB1 FRHB0 FRHW3 FRHW2 FRHW1 FRHW0

00h

FRV7

FRV6

FRV5

FRV4

FRV3

FRV2

FRV1

FRV0

00h FRVD7 FRVD6 FRVD5 FRVD4 FRVD3 FRVD2 FRVD1 FRVD0

00h FRVB4 FRVB3 FRVB2 FRVB1 FRVB0 FRVW2 FRVW1 FRVW0

00h

00h ENH2D ENV2D HEDG

xxh AD7 AD6 AD5

00h EN_CH3 EN_CH2 EN_CH1 EN_CH0

xxh ADRDY

HVIN2

EN_LMT HCNT2 HCNT1 HCNT0

AD4

AD3

CH3

AD2

CH2

AD1

CH1

AD0

CH0

W

R

WDT

001Eh

W

R

W

R

W

R

00h DISWDT

WDT1

WDT0

I2C_STA 0020h

I2C_CON 0020h

I2C_RX 0021h

I2C_TX 0021h

I2C_ADR 0022h

22h

02h

xxh

X0h

BB

SFIRST SSTOP

SRW RXNAK2 I2CRDY

ENI2C MCLK1 MCLK0 MSTR MSTOP I2CRW TXNAK2 SLAVE

MRX7

MTX7

SAR7

MRX6

MTX6

SAR6

BB

MRX5

MTX5

SAR5

DDC2

MRX4

MTX4

SAR4

FIRST

MRX3

MTX3

SAR3

MRX2

MTX2

SAR2

MRX1

MTX1

SAR1 DLYHLD

MRX0

MTX0

DDC_STA1

0024h

0025h

01h ALGRDY

00h

STOP ALGRW MATCH RXNAK1

IN_CMD WR_D3

DDC_STA2

R

DDC_CON1 0024h

DDC_CON2 0025h

DDC_RTX 0026h R/W FFh

W

00h ENDDC

80h RAMAS1 RAMAS0

DDC2

ENRAMA

TX

TXNAK1

WR_EN

DRX0

ENRAMB CLR_ADR CLR_WD3

RAMBS

DRX4

DRX7 DRX6

DRX5

DRX3

DRX2

DRX1

ENADRA7 ENADRA6 ENADRA5 ENADRA4 ENADRA3 ENADRA2 ENADRA1 ENADRA0

DDC_AAE 0027h

DDC_ABE 0028h

DDC_AR0 0029h

DDC_AR1 002Ah

DDC_AR2 002Bh

W

FFh

00h

ENADRB7 ENADRB6 ENADRB5 ENADRB4 ENADRB3 ENADRB2 ENADRB1 ENADRB0

X0h DAR07 DAR06 DAR05 DAR04

ENAR0

X0h DAR17 DAR16 DAR15 DAR14 DAR13 DAR12 DAR11 ENAR1

X0h DAR27 DAR26 DAR25 DAR24 DAR23 DAR22 DAR21 ENAR2

Weltrend Semiconductor, Inc.

Page 41

WT61P4 v1.03

Monitor Controller

Name

Addr R/W Initial

Bit 7

Bit 6

Bit 5

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

INT_FLG 002Ch

INT_EN 002Ch

INT_FLG2 002Dh

INT_EN2 002Dh

INT_SRC 002Eh

IRQ_CON1 002Eh

IRQ_CON2 002FH

R

W

R

W

R

00h IF_DDC IF_MI2C IF_RGB IF_SYNC IF_IRQ2 IF_IRQ1 IF_VSO IF_VIN

IE_SYNC

IF_IR

IE_IR

00h IE_DDC IE_MI2C IE_RGB

IE_IRQ2 IE_IRQ1 IE_VSO IE_VIN

IF_HCHG

IE_HCHG

RGBRDY

00h IF_POL IF_OVV

00h IE_POL IE_OVV

00h POLINT OVVINT

SYNC

IRQ2

IRQ1

VSO

VIN

CLR_POL

CLR_IRQ2 CLR_IRQ1 CLR_VSO

W

00h

CLR_OV

CLR_VIN

IRQ1_EG

IRQ2_RF IRQ2_EG IRQ1_RF

PWM0L 000Ch R/W 00h

PWM0₃PWM0₂PWM0₁PWM0₀

PWM0H 000Dh R/W 80h PWM0₁₁PWM0₁₀PWM0₉PWM0₈PWM0₇PWM0₆PWM0₅PWM0₄

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

0031h R/W 80h PWM1₇PWM1₆PWM1₅PWM1₄PWM1₃PWM1₂PWM1₁PWM1₀

0032h R/W 80h PWM2₇PWM2₆PWM2₅PWM2₄PWM2₃PWM2₂PWM2₁PWM2₀

0033h R/W 80h PWM3₇PWM3₆PWM3₅PWM3₄PWM3₃PWM3₂PWM3₁PWM3₀

0034h R/W 80h PWM4₇PWM4₆PWM4₅PWM4₄PWM4₃PWM4₂PWM4₁PWM4₀

0035h R/W 80h PWM5₇PWM5₆PWM5₅PWM5₄PWM5₃PWM5₂PWM5₁PWM5₀

0036h R/W 80h PWM6₇PWM6₆PWM6₅PWM6₄PWM6₃PWM6₂PWM6₁PWM6₀

0037h R/W 80h PWM7₇PWM7₆PWM7₅PWM7₄PWM7₃PWM7₂PWM7₁PWM7₀

0038h R/W 80h PWM8₇PWM8₆PWM8₅PWM8₄PWM8₃PWM8₂PWM8₁PWM8₀

0039h R/W 80h PWM9₇PWM9₆PWM9₅PWM9₄PWM9₃PWM9₂PWM9₁PWM9₀

PWM10 003Ah R/W 80h PWM10₇PWM10₆PWM10₅PWM10₄PWM10₃PWM10₂PWM10₁PWM10₀

PWM11 003Bh R/W 80h PWM11₇PWM11₆PWM11₅PWM11₄PWM11₃PWM11₂PWM11₁PWM11₀

PWM12 003Ch R/W 80h PWM12₇PWM12₆PWM12₅PWM12₄PWM12₃PWM12₂PWM12₁PWM12₀

PWM13 003Dh R/W 80h PWM13₇PWM13₆PWM13₅PWM13₄PWM13₃PWM13₂PWM13₁PWM13₀

PWM14 003Eh R/W 80h PWM14₇PWM14₆PWM14₅PWM14₄PWM14₃PWM14₂PWM14₁PWM14₀

PWM15 003Fh R/W 80h PWM15₇PWM15₆PWM15₅PWM15₄PWM15₃PWM15₂PWM15₁PWM15₀

PWM_EN1 000Eh

PWM_EN2 000Fh

PSC_CTL 0041h

IR_STA 0042h

IR_DATA 0043h

IR_CTL 0042h

OTH_CTL1 004Eh

W

R

W

00h EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1 EPWM0

EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10

00h

EPWM9 EPWM8

DDC_WK

00h IRQ1_WK IRQ2_WK

H_in1&SOG

Vin1

IRD3

ICLK

Hin2

Vin2

IRDCNT1 IRDCNT0

00h

IRRDY IR_RD IR_KEEP IR_ERR

IRD7

ENIR

IRD6

IN_HL

IRD5

IRD4

IRD2

IRD1

CLR_KP

IRD0

CLR_ERR

PWMCLK

ENT0T1

Weltrend Semiconductor, Inc.

Page 42

WT61P4 v1.03

Monitor Controller

TARGET AC AND DC SPECIFICATION

Absolute Maximum Ratings

Parameter

Min.

Max.

Units

DC Supply Voltage (VDD)

Input and output voltage with respect to Ground

Storage temperature

-0.3

-25

-10

5.5

VDD+0.3

125

V

^oC

Ambient temperature with power applied

85

D.C Characteristics (VDD=5.0V±10%, Ta=0-70°C)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

V_DD5v

I_VDD

I_Suspend

V_IH,IO

V_IL,IO

V_OH,IO

V_OL,IO

R_PH

+5v Supply Voltage

Operating Current

Power Down Mode Current

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Output Low Voltage (PC0-PC7) I_OL= 10mA

Pull High Resistance

4.5

--

0.7VDD

-0.3

4

5

12

150

--

5.5

30

--

V

mA

µA

V

Kohm

V

F_OSC= 12MHz, No load

No load

VDD+0.3

0.2VDD

VDD

0.4

--

I_OH= -6mA

I_OL= 6mA

4.5

0.18

0.15

25

0

--

0.4

50

--

V_IH,SYNC

HIN, VIN, SOG Input High

Voltage (Schmitt trigger)

1.6

V_IL,SYNC

I_IL,SYNC

HIN, VIN, SOG Input Low

Voltage (Schmitt trigger)

Input Leakage Current

HSYNC and VSYNC pins

SCL, SDA Input High Voltage

(Schmitt trigger)

SCL, SDA Input Low Voltage

(Schmitt trigger)

Reset Input High Voltage

Reset Input Low Voltage

Low VDD Reset Voltage

--

-1

1.2

--

1

V

µA

V

0V <V_IN< VDD

V_IH,SCL

V_IH,SDA

V_IH,SCL

V_IH,SDA

V_IH,RES

V_IL,RES

V_LVD

2.8

-0.3

--

VDD+0.3

1.6

--

V

2.8

-0.3

2.5

--

2.7

VDD+0.3

1.6

V

2.9

Weltrend Semiconductor, Inc.

Page 43

WT61P4 v1.03

Monitor Controller

D.C Characteristics (VDD=3.3V±10%, Ta=0-70°C)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

V_DD5v

I_VDD

I_Suspend

V_IH,IO

V_IL,IO

V_OH,IO

V_OL,IO

R_PH

+5v Supply Voltage

Operating Current

Power Down Mode Current

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Output Low Voltage (PC0-PC7) I_OL= 10mA

Pull High Resistance

3.0

--

3.3

12

50

--

3.6

30

--

V

mA

µA

V

Kohm

V

F_OSC= 12MHz, No load

No load

0.7VDD

VDD+0.3

0.2VDD

VDD

0.4

-0.3

2.8

0

--

I_OH= -6mA

I_OL= 6mA

0.4

50

--

25

1.2

V_IH,SYNC

HIN,VIN,SOGIN Input High

Voltage (Schmitt trigger)

--

V_IL,SYNC

I_IL,SYNC

HIN,VIN,SOG Input High

Voltage(Schmitt trigger)

--

-1

0.9

--

1

V

µA

V

Input Leakage Current

HSYNC and VSYNC pins

SCL,SDA Input High Voltage

(Schmitt trigger)

SCL,SDA Input Low Voltage

(Schmitt trigger)

Reset Input High Voltage

Reset Input Low Voltage

Low VDD Reset Voltage

0V <V_IN< VDD

V_IH,SCL

V_IH,SDA

V_IH,SCL

V_IH,SDA

V_IH,RES

V_IL,RES

V_LVD

2.0

-0.3

--

VDD+0.3

1.0

--

V

2.0

-0.3

2.5

--

2.7

VDD+0.3

1.0

V

2.9

Weltrend Semiconductor, Inc.

Page 44

WT61P4 v1.03

Monitor Controller

A.C Characteristics (VDD=5.0V±5%, fosc=24MHz, Ta=0-70°C)

NRES and NIRQ Timing

Symbol

Parameter

Min.

Typ.

Max.

Units

t_LOW,RES

t_LOW,IRQ

NRES pin low pulse

83

--

ns

NIRQ low pulse (level trigger)

RESET

IRQ

t_LOW,RES

t_HIGH,IRQ

SYNC Processor Timing

Symbol

Parameter

Min.

Typ.

Max.

Units

t_HIGH,SYNC

t_LOW,SYNC

HSYNC and VSYNC high time

HSYNC and VSYNC low time

167

--

ns

HSYNC

VSYNC

t_HIGH,SYNC

t_LOW,SYNC

DDC1 Timing

Symbol

t_VAA,DDC1

Parameter

Min.

125

Typ.

--

Max.

500

Units

ns

SDA1 output valid from VSYNC rising edge

t_VAA,DDC1

SDA1

Bit 0 (LSB)

Null Bit

Bit 7 (MSB)

VSYNC

t_HIGH,SYNC

t_{LOW ,SYNC}

Weltrend Semiconductor, Inc.

Page 45

WT61P4 v1.03

Monitor Controller

DDC2B Timing

Symbol Parameter

Min.

Typ.

Max.

Units

f_SCL

t_BF

SCL1 input clock frequency

Bus free time

Hold time for START condition

Set-up time for START condition

SCL1 clock high time

--

1.3

0.6

1.3

0

--

100

--

400

--

kHz

us

ns

Ns

ns

us

t_HD,START

t_SU,START

t_HIGH,SCL

t_LOW,SCL

t_HD,DATA

SCL1 clock low time

Hold time for DATA input

Hold time for DATA output

Set-up time for DATA input

Set-up time for DATA output

SCL1 and SDA1 rise time

SCL1 and SDA1 fall time

Set-up time for STOP condition

t_SU,DATA

--

t_RISE,DDC

t_FALL.DDC

t_SU,STOP

--

0.6

300

--

SLAVE I or II I2C Timing

Symbol Parameter

Min.

Typ.

Max.

Units

f_SCL

t_BF

SCL1 input clock frequency

Bus free time

Hold time for START condition

Set-up time for START condition

SCL1 clock high time

0

2

1

0

167

334

-

100

-

1

300

-

kHz

us

ns

us

ns

us

t_HD,START

t_SU,START

t_HIGH,SCL

t_LOW,SCL

t_HD,DATA

SCL1 clock low time

Hold time for DATA input

Hold time for DATA output

Set-up time for DATA input

Set-up time for DATA output

SCL1 and SDA1 rise time

SCL1 and SDA1 fall time

Set-up time for STOP condition

t_SU,DATA

t_RISE,DDC

t_FALL.DDC

t_SU,STOP

-

2

t_BF

SDA1

t_RISE

t_HD,START

t_FALL

SCL1

t_HIGH,SCL

t_SU,STOP

t_LOW,SCL

t_HD,DATA

t_SU,START

t_SU,DATA

Weltrend Semiconductor, Inc.

Page 46

WT61P4 v1.03

Monitor Controller

TYPICAL APPLICATION CIRCUIT

Crystal Oscillator

NRES Pin and 3.3V Regulator

VDD=3.3v

Weltrend Semiconductor, Inc.

Page 47

WT61P4 v1.03

Monitor Controller

PWM Output

Hsync, Vsync and DDC Interface Protection

+5V +5V

47K

WT61P4

220

VIN

HIN

VSYNC

HSYNC

220

100P

470P

5.1V

+5V +5V

47K

10K

150

SCL1

SDA1

SCL

SDA

5.1V

Weltrend Semiconductor, Inc.

Page 48

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