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IXE2424EE

型号：

IXE2424EE

品牌：

INTEL[ INTEL ]

页数：

28 页

PDF大小：

191 K

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Intel® Media Switch  
IXE2424 10/100 + Gigabit L2/3/4  
Advanced Device  
Data Sheet  
Advance Information  
Product Features/Benefits  
Single-chip, 24-port 10/100 and 4-port Gigabit  
Ethernet Layer 2/3/4 switch/router  
— High integration, compact footprint, and low  
power dissipation enables the design of  
high-port density systems at the lowest  
per-port cost  
Wire speed performance across all ports in  
switching or IP/IPX/MPLS routing modes  
— Delivers congestion-free performance  
through Enterprise switches during peak load  
periods  
Advanced multicast, broadcast, and filtering  
capabilities  
— Enables video and voice multicasting on IP  
networks,  
— Protects from broadcast storms  
— Enables high-performance intranet firewalls  
Support for multiple IP networks on a single  
port, as well as multiple ports on the same  
network  
— Accommodates adds, moves, and changes in  
network topology  
Hardware assistance for several Layer 2 and  
Layer 2/3/4 protocols such as STP, Multiple  
Spanning Trees (802.1s), Rapid Reconfiguration  
(802.1w), Port-based Network Access Control  
(802.1x), GVRP, GMRP, RIP, IPX/RIP, VoIP,  
and IPSec packets  
— Reduces complexity and cost of CPU  
subsystem, which can be significant in stacks  
or chassis designs  
Link aggregation of all ports in groups up to 8  
for 10/100 and 4 for Gigabit Ethernet ports  
— Enables meshed configurations with  
redundant paths for fail-safe networks  
Advanced traffic prioritization, QoS,  
Diffserv,WRED and bandwidth management  
capabilities  
— Enables the convergence of voice, video, and  
data traffic of Ethernet/IP networks  
Fully compliant with VLAN implementation  
standards based on ports, tags, and addresses  
— Enables flat plug-and-play networks that are  
easy to maintain  
Supports MPLS label edge router and label  
switch router configurations  
— Enhances and simplifies packet forwarding  
through routers using MPLS labels or  
forwarding decisions  
Connections to other devices using  
standards-based interfaces such as  
SERDES/GMII, SMII, PCI, I2C, and SSRAM  
— Simplifies system design and provides  
flexibility when used with other devices  
Support for MAC-based and switch -based  
statistics gathering on chip  
— Enables effective network management  
using counters with SNMP  
IXE2424EE version supports extended  
temperature range of -40° to +85° C  
— Operates at the very high and low  
temperatures required for  
telecommunications applications  
Note:  
Key features and benefits for the IXE2424 device are given above. Please refer  
to Section 10.0 for a complete feature list.  
Notice: This document contains information on products in the sampling and initial production  
phases of development. The specifications are subject to change without notice. Verify with your  
local Intel sales office that you have the latest data sheet before finalizing a design.  
August 2001  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual  
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability  
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to  
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel® products are not  
intended for use in medical, life saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for  
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.  
The Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device may contain design defects or errors known as errata which may cause the  
product to deviate from published specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copyright © Intel Corporation, 2001  
*Other brands and names are the property of their respective owners.  
Data Sheet  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Contents  
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
7.0  
8.0  
9.0  
10.0  
IXE2424 General Description.............................................................................................1  
Applications........................................................................................................................1  
Functional Description........................................................................................................2  
Interface Descriptions.........................................................................................................4  
Data Structures ..................................................................................................................5  
Hardware Assisted Features............................................................................................10  
Electrical and Environmental Specifications.....................................................................13  
Hardware Support ............................................................................................................16  
Software Support..............................................................................................................17  
Feature List ......................................................................................................................20  
Figures  
1
2
3
4
5
6
IXE2424 Block Diagram ........................................................................................1  
IXE2424 System Block Diagram ...........................................................................3  
Switching Flow in IXE2424....................................................................................5  
Clock Interface Timing Diagram..........................................................................15  
IXE2424 Reference Design System....................................................................16  
Software Architecture Illustrating APIs Supported by the IXE2424.....................17  
Tables  
1
2
3
4
5
6
7
8
9
IXE2424 Interfaces................................................................................................4  
Switching Block Entries.........................................................................................6  
Absolute Maximum Ratings.................................................................................13  
Thermal Resistance ............................................................................................13  
Thermal Resistance with Airflow .........................................................................13  
Operating Conditions...........................................................................................14  
Clock Interface Timing.........................................................................................14  
APIs Supported by the IXE2424..........................................................................18  
Protocols Enabled by the IXE2424......................................................................19  
Data Sheet  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Data Sheet  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
1.0  
IXE2424 General Description  
The IXE2424 device supports 24 10/100 Mbps ports and 4 Gigabit ports, integrating the MACs,  
switching, routing, and queuing logic on-chip. The IXE2424 device is capable of wire speed Layer  
2 switching and wire speed Layer 3 and 4 routing on all ports. It provides advanced filtering,  
mirroring, and prioritizing capabilities and Layer 4 bandwidth management features.The device  
also supports MPLS switching on all ports.  
A system designed using a IXE2424 device requires transceivers on the 10/100 Mbps and Gigabit  
ports, memory for storing switching data structures, memory for storing packets, and a CPU  
subsystem. The IXE2424 device interfaces to the CPU subsystem via a 32-bit PCI bus.  
The IXE2424 is available as two parts:  
• IXE2424EA: Temperature range 0oC to +55 oC  
• IXE2424EE: Temperature range -40 oC to +85 oC  
2.0  
Applications  
Key applications for the IXE2424 include:  
• 24 + 4 Layer 2/3/4 workgroup and enterprise switches  
• Layer 2/3/4 switch/router with Gigabit uplinks and advanced bandwidth management  
• Cascadable high port count Layer 2/3/4 switch/router when using one or all Gigabit ports for  
cascading  
• 24 + 4 MPLS label edge/switch router  
Figure 1.  
IXE2424 Block Diagram  
Intel® Media Switch IXE2424 10/100/1000  
L2/3/4 Advanced Device  
24 x 10/100  
MACs  
10/ 100  
Phys  
Packet  
Packet  
Data  
Storage  
Path  
Gigabit  
Phys  
4 x 10/100/1000  
MACs  
Packet Classifier  
Engine  
Queuing  
Engine  
CPU  
Interface  
(Optional)  
PCI  
Interface  
External  
SSRAM for  
Address  
Tables  
Data Sheet  
1
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
3.0  
Functional Description  
3.1  
Introduction  
The IXE2424 device is a highly integrated Layer 2 switch, MPLS Label/Edge Switch /Router and  
Layer 2/3/4 switch/router. It supports twenty-four 10/100 Mbps ports and four Gigabit ports with  
on-chip MACs. It also supports integrated switching and routing logic and on-chip packet queuing  
memory. The IXE2424 is capable of switching and routing packets at wire speed on all ports  
regardless of packet size.  
In Layer 2 mode, the IXE2424 supports:  
• IEEE 802.1D, 1998 Edition standard, including 802.1p, 802.1Q  
It also supports the IEEE 802.3, 1998 Edition standard, which includes:  
• 802.3x flow control  
• 802.3u Fast Ethernet  
• 802.3z Gigabit Ethernet standards  
• 802.3ad Link Aggregation standards  
The IXE2424 provides on-chip 32-bit statistics counters to support the Etherstats group of RMON  
standards. In addition, it provides counters for monitoring flow-based statistics.  
In addition to the IEEE standards support, the IXE2424 provides many advanced features such as  
Filtering, Mirroring, Bandwidth Management, Broadcast, and Multicast Storm Control, all in a  
single device.  
The IXE2424 connects to other devices using standards based interfaces such as SERDES/GMII,  
SMII, PCI, and SSRAM. This simplifies the system design and provides flexibility when used with  
other devices.  
Figure 2 illustrates a system block diagram of the IXE2424 device.  
2
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Figure 2.  
IXE2424 System Block Diagram  
4 x Gigabit  
Phys  
3 x Octal  
10/100  
Phys  
PCI  
BUS  
Address Table  
RAM  
PCI  
Controller  
Intel® Media Switch  
IXE2424 10/100+Gigabit L2/3/4  
Advanced Device  
CPU  
Subsystem  
Packet Storage  
RAM  
Data Sheet  
3
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
4.0  
Interface Descriptions  
Table 1 provides a description of the IXE2424 interfaces.  
Table 1.  
IXE2424 Interfaces  
Interface  
Description  
PCI Rev 2.2 compliant interface with bus mastering  
capability for packet and unresolved entry transfers to  
CPU.  
PCI  
Two pin interface that allows the IXE2424 to  
communicate to the external 10/100 Mbps  
transceivers and provides three separate SYNC  
signals for point -to-point connections to three 8-port  
transceivers.  
SMII  
Configurable interface used to link the IXE2424 to the  
four Gigabit ports.  
GMII/SERDES  
Address Table SRAM  
Packet Storage  
MDIO  
64-bit wide Pipelined Burst Synchronous SRAM  
interface for address storage.  
128-bit wide Pipelined Burst Synchronous Storage  
SRAM interface for packet storage.  
Serial MDIO interface for management of up to 32  
Phy devices.  
Transfers the Gigabit ports’ LED status. Can be  
attached to an external 74HC595-type shift register.  
LED  
4
Data Sheet  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
5.0  
Data Structures  
The Switching Engine block of the IXE2424 device uses a group of data structures when making  
its forwarding decisions. These data structures called “entries” are linked to each other via pointers  
and are usually stored in an external SSRAM (some of them can also be stored on-chip).  
Each type of “entry” contains different information that allows the IXE2424 to support its diverse  
set of features. Multiple addresses can point to the same entry type, unless they use different  
features. This results in compact and efficient memory usage, with memory requirements  
increasing only as more of these features are enabled.  
Figure 3.  
Switching Flow in IXE2424  
Each Address has a unique  
Record and Rule Entry combination  
Record Entry & Rule Entry  
Protocol Entry W0  
Dest Swap Entry  
Protocol Entry W1  
Protocol Entry W2  
Multiple Words of the Protocol  
Entry can point to the same  
NetID Entry or to separate  
NetID Entry  
Net ID Entry  
Net ID Entry  
Data Sheet  
5
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Table 2 entries are maintained by the Switching Engine block for Layer 2, IP, IPX and MPLS  
addresses.  
Table 2.  
Switching Block Entries  
Entry Type  
Description  
The basic entry associated with every address. Is associated with another entry called  
the Rules Entry.  
Record Entry  
Rules Entry  
Contains further information about the address including the port on which this address  
resides. Contains further pointers to a destination swap Entry and a Protocol Entry.  
Destination Swap  
Entry  
This entry contains the Destination Swap Address. For IP and MPLS Multicast  
addresses, this entry contains pointers to Multicast Information entries.  
Contains filter, mirror, QoS, CoS, and priority configuration information and can be  
configured as a list of one or more words with different protocols selecting to different  
words in the same entry. Contains one or more pointers to a Net ID Entry.  
Protocol Entry  
Net ID Entry  
This entry contains address based VLAN information. For IP addresses this entry  
contains information about any MPLS labels to be pushed into the packet.  
Multicast  
Information Entry  
Contains Multicast packet replication information for IP and MPLS multicast addresses  
5.1  
5.2  
Enabled Layer 2 Protocols  
The Layer 2 protocols enabled are: ARP, RARP, AppleTalk, DECNet, SNA, NetBios, DLC/LLC.  
IP Switching/Routing Features  
The IXE2424 will forward the first packet of the flow to the CPU if it does not find a forwarding  
entry in its tables.  
The CPU programs the outgoing port number and the Ethernet address of the next hop or  
destination address into the IXE2424 tables. The first packet must then be routed on the port that  
has the destination node connected through it.  
Once the entries are created in the IXE2424 tables for the source and destination, all the packets  
belonging to the flow are routed in hardware at wire speed. Packets belonging to protocols other  
than IP and IPX will be switched in hardware at wire speeds using the Layer 2 switching algorithm.  
5.2.1  
Routing Domains  
A routing domain is an IP network. An IP address and a subnet mask identify an IP routing domain.  
Multiple routing domains can exist on the same port (in which case, they are identified by 802.1Q  
VLAN tags) or multiple ports can belong to a routing domain. All the ports that belong to a routing  
domain have the same IP address.  
The IXE2424 device supports up to 256 routing domains.  
6
Data Sheet  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
5.2.2  
Enabled IP Protocols  
The IP protocols enabled are: TCP, UDP, ICMP, IGMP, EGP, OSPF, RSVP, and IGRP.  
5.3  
IPX Switching/Routing Features  
5.3.1  
Network and Node Addresses  
For IPX packet processing, the IXE2424 uses network or node addresses to perform the switching  
feature.  
The IXE2424 maintains a shared address table for IPX network addresses and IPX node addresses,  
supporting one routing domain per port for IPX networks.  
5.3.2  
Enabled IPX Protocols  
There are registers provided for each protocol that indicate the increment from the Protocol Offset  
where the protocol specific information for that protocol may be obtained.  
The IPX protocols enabled are: SPX, RIP, NCP, NLSP, and SAP.  
5.4  
Port-based VLAN Features  
The IXE2424 provides Port-based VLAN features by allowing each port to specify the group of  
ports that belong in that VLAN. The Port based VLANs are the default means of creating VLANs  
when no other type of VLANs (for example, 802.1Q Tag) have been programmed.  
A separate VLAN per port is provided for:  
• Layer 2 packets  
• IP packets  
• IPX packets  
5.5  
Protocol-based VLAN Features  
Protocol-based VLANs can be configured on the IXE2424 by having different protocols point to  
different words in the Protocol Entry. This allows the protocols to use different Net ID Entries, and  
thus create different VLANs.  
The Protocol Entry used by each protocol is programmed in the Protocol Registers.  
Data Sheet  
7
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
5.6  
802.1Q VLAN and 802.1D, 1998 Edition Priority and Class of  
Service Features  
The IXE2424 provides extensive support for VLANs and priorities based on the 802.1Q and  
802.1D, 1998 Edition specifications.  
It provides four levels of queues for all ports. The 3-bit Tag Priority field from the tagged packet  
can be mapped into the four priority levels, by using the Map Priority Level register. The outgoing  
packet can be modified to regenerate Tag Priority by using the per port Port Regenerate Priority  
Entry. Map Priority Level register is a global mapping applying to all ports, while there is a per port  
Regenerate Priority Entry. The Regenerate Priority Entry is indexed using the receive port number.  
Also supported is regenerating the priority the packet should go out on. If there is not a need for  
regenerating the priority, then the user can program the outgoing priority to be the same as the  
incoming priority. The outgoing priority is also used to determine which internal queue the packet  
will be queued to.  
5.7  
Port Aggregation Features  
The IXE2424 supports port aggregation on all ports in groups of up to eight ports for the 10/100  
Mbps ports, and in a group of four ports for the Gigabit ports.  
The two modes of port aggregation supported are:  
• Ingress aggregation only (the default mode),  
• Ingress and Egress aggregation.  
5.8  
5.9  
Interrupt Generation and Handling  
The IXE2424 provides flexible interrupt generation mechanisms. It provides two interrupt pins and  
two on-chip mask registers that enable the CPU to map any interrupt to either of the interrupt pins.  
This allows the CPU to treat certain interrupts as high priority and others as low priority.  
The CPU can also mask off any interrupt from both registers and effectively convert the bit into a  
poll bit.  
Packet Transfers to CPU  
The IXE2424 provides extensive packet processing support in its hardware in order to reduce the  
burden of the CPU.  
It provides four queues for packets that are to be sent to the CPU. Each queue can be individually  
turned on or off to start and stop the CPU from receiving packets from that queue, and can be  
assigned a guaranteed bandwidth. This allows the CPU to prioritize the types of packets that it  
wants to process.  
The DMA engines that are provided per queue allow the IXE2424 to directly transfer data into the  
CPU memory without CPU intervention.  
8
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
5.10  
Unresolved Packet Transfers to CPU  
The IXE2424 also maintains four queues for unresolved packets. Each queue can be individually  
turned on or off and assigned a guaranteed bandwidth. This allows the CPU to prioritize the types  
of packets that it wants to process. The Scatter-Gather DMA engines provided per queue allow the  
IXE2424 to directly transfer data into the CPU memory without CPU intervention.  
The only difference between “unresolved packet transfers to CPU” versus “resolved packet  
transfers to CPU”, is that unresolved packets have an option to not send the whole packet, but only  
part of the packet to the CPU.  
5.11  
Packet Transfers From CPU  
The IXE2424 provides two queues, which are supported by DMA, for packet transfers from the  
CPU. Queue 1 is treated as the high priority queue, and is always processed before queue 0, unless  
a packet transfer had already started for queue 0. In this case, the complete packet from queue 0 is  
fetched from the CPU memory first, and then the packet from queue 1 is processed. The two  
queues allow a high priority process (for example, Spanning Tree BPDUs) to not have its packets  
stuck behind other lower-priority packets.  
Data Sheet  
9
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
6.0  
Hardware Assisted Features  
This section describes the hardware assisted features provided in the IXE2424.  
6.1  
Address Learning  
The IXE2424 facilitates address learning by using a hardware engine that provides a content  
addressable memory-like interface to the CPU. The IXE2424 needs CPU support to learn  
addresses.  
6.2  
6.3  
Address Aging  
The IXE2424 contains hardware assistance for the entry aging process. It has three modes of  
operation to support various levels of CPU intervention. In all modes, the aging controller steps  
through a programmable number of zones, broadcasting the current zone (also known as the “age  
zone”) throughout the device.  
Learning of Socket Address  
The IXE2424 provides a separate address learning interface for Layer 4 Socket Addresses in order  
to speed up the process of application based rules generation. The IXE2424 also provides an add,  
delete, and lookup state machine called the Layer 4 processor. This simplifies the adding and  
deleting of socket addresses.  
6.4  
6.5  
Aging of Socket Address  
The IXE2424 has a separate aging state machine for aging Layer 4 Record Entries.  
MDIO/MDC Scanning  
The IXE2424 provides a controller to manage up to 32 devices via the MDIO and MDC pins. Up to  
thirty-two 16-bit registers per device can be addressed. The controller allows the CPU to use the  
PCI bus to communicate with these devices, performing all serialization and deserialization. In  
addition, it allows the CPU to perform “gang” operations that work on several devices at a time.  
Finally, it can be set to continuously scan the devices looking for a change in their status,  
interrupting the CPU only when it detects such a change. The controller uses an internal RAM for  
all gang operations.  
6.6  
Statistic Counters  
The IXE2424 provides MAC-based and switch-based statistics gathering support on chip.  
10  
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
6.7  
6.8  
Bandwidth Management  
When performing bandwidth management, it is necessary to account for the size of the packets  
being arbitrated, not just the number of packets. Also, latency can become a problem. The  
IXE2424 supports two types of algorithms per port: the Credit Algorithm and the Strict Priority  
Algorithm.  
QoS  
The QoS logic in the IXE2424 allows certain flows to be mapped as QoS. These flows can be  
queued to a certain priority that has been assigned a guaranteed bandwidth. The rate at which the  
flow is sending is also constantly monitored, and this is compared to the configured rate for this  
flow. If the rate is exceeded, then the packets that caused this exception are either dropped or  
remarked with new Diffserv code point and WRED precedences.  
Multiple flows can be mapped to the same transmit queue, and still be guaranteed the required  
bandwidth for that flow—the bandwidth management feature takes care of guaranteeing the  
bandwidth for the queue, and the QoS feature takes care of guaranteeing the bandwidth for all the  
flows mapped to the same queue.  
6.9  
Diffserv  
The IXE2424 allows marking of packets belonging to certain flows. Packets belonging to such  
flows are assigned a particular value of the Diffserv Code point. The Diffserv code point can also  
be changed based on QOS settings. Traffic prioritization and policing is done by mapping the  
Diffserv Code Point to internal priority levels,802.1 p tag priority levels, and WRED parameter set.  
6.10  
6.11  
WRED  
The IXE2424 supports two precedence classes on every priority queue. The WRED parameters are  
selectable in a per port per priority queue basis. WRED can be used along with QoS and Diffserv  
Broadcast and Multicast Storm Control  
The IXE2424 provides a per port configuration on the incoming and/or outgoing port basis that  
allows broadcast and/or multicast storm control. The CPU can program a threshold value per port  
that indicates the number of broadcast and/or multicast packets/bytes that are allowed in a given  
time interval.  
6.12  
IP Multicast Routing  
The IXE2424 supports up to 256 routing domains without placing any per port limitations. A port  
can have one or more routing domains (or IP networks) associated with it. An IP multicast packet  
that must be forwarded on such a port may need to be sent out multiple times, each time with a  
Data Sheet  
11  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
different 802.1Q tag associated with that routing domain. The number of times the packet must sent  
depends on the number of routing domains on that port that have members that belong to that  
multicast group. The IXE2424 allows up to 256 multicast group members on a port.  
12  
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
7.0  
Electrical and Environmental Specifications  
This chapter contains the electrical and environmental specifications for the IXE2424. The  
IXE2424 supports both 5V and 3.3V signaling environments.  
7.1  
Absolute Maximum Rating  
Applying stresses beyond the absolute maximum may cause unrecoverable damage to the device.  
Operation of this product is not implied for any condition beyond the ranges specified in the  
functional operation range described in Section 9.3, “Functional Operating Range” on page 9-2.  
Operating this product at the absolute maximum rating for a prolonged period can negatively  
impact device reliability. The following table, Table 9-1, “Absolute Maximum Ratings” on  
page 9-1 lists the absolute maximum ratings for the IXE2424.  
Table 3.  
Absolute Maximum Ratings  
Parameter  
Sym  
Min  
Max  
Units  
Supply Voltage Core  
Supply Voltage IO  
V
TBD  
TBD  
-40  
1.98  
3.6  
V
V
DDCORE  
V
DDIO  
Operating Temperature  
Storage Temperature  
T
85  
oC  
oC  
op  
T
-65  
+150  
st  
Caution: Exceeding these values may cause permanent damage. Functional operation under these  
conditions is not implied. Exposure to maximum rating conditions for extended periods may  
affect device reliability.  
7.2  
Thermal Resistance  
Table 4.  
Table 5.  
Thermal Resistance  
Thermal Resistance  
Parameter  
Value  
θJC  
θCA  
Junction to case  
Case to ambient  
TBD  
TBD  
Thermal Resistance with Airflow  
Thermal  
Package  
0 LFPM  
TBD  
100 LFPM  
TBD  
200 LFPM  
300 LFPM  
500 LFPM  
Resistance  
θJA (o C/W)  
TBGA Type IA  
TBD  
TBD  
TBD  
Note:  
Heat Sink may be required depending on the air flow in the system.  
Data Sheet  
13  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
7.3  
Functional Operating Range  
The following table, Table 6 lists the functional operating range.  
Table 6.  
Operating Conditions  
1
Parameter  
Sym  
Min  
Typ  
Max  
Units  
2
Recommended Supply Voltage Core  
Recommended Supply Voltage IO  
V
1.71  
1.8  
3.3  
1.89  
V
DDCORE  
2
V
3.135  
3.456  
V
DD  
Recommended Operating Temperature  
(IXE2424EA)  
T
0
55  
85  
oC  
oC  
op  
Recommended Operating Temperature  
(IXE2424EE)  
T
-40  
op  
IDDAnalog  
TBD  
TBD  
TBD  
TBD  
300  
1.5  
mA  
mA  
A
IDDIO  
IDDCORE  
Total Power (3.3V/1.8V)  
P
3.7  
W
tot  
Maximum Junction Temperature  
T
-40  
125  
oC  
jmax  
1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production  
testing.  
2. Voltages with respect to ground unless otherwise specified.  
7.4  
Clock Interface  
7.4.1  
Signal Timing  
Table 7 describes the clock interface timing specifications.  
Clock Interface Timing  
Table 7.  
Symbol  
Parameter  
Min  
Max  
f
Frequency  
Duty Cycle  
100MHz  
80%  
FREQ  
40%  
Cycle-to-Cycle Jitter  
Time High  
200ps  
t
4ns  
4ns  
KH  
t
Time Low  
KL  
t
Rise Time  
1.5ns  
1.5ns  
R
t
Fall Time  
F
Figure 4 illustrates the Clock interface timing diagram.  
14  
Data Sheet  
Intel Confidential  
 
 
 
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Figure 4.  
Clock Interface Timing Diagram  
tKC  
tKL  
CLK  
(100MHz)  
tKH  
Data Sheet  
15  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
8.0  
Hardware Support  
Figure 5 illustrates the hardware supported in the IXC2424 reference design.  
Figure 5.  
IXE2424 Reference Design System  
1. LED Arrays  
3. Fiber Transceivers  
5. RJ45 Connectors  
2. Processor  
4. Magnetics  
6. Fast Ethernet Phys  
10. DRAM Modules  
8. Serdes Phys  
9. System Controller  
7. Intel® Media Switch  
IXE2424 10/100+Gigabit  
L2/3/4 Advanced Device  
16  
Data Sheet  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
9.0  
Software Support  
9.1  
APIs Supported  
The IXE2424 supports the APIs illustrated in the software architecture block diagram shown in  
Figure 6.  
Figure 6.  
Software Architecture Illustrating APIs Supported by the IXE2424  
Higher Layer  
Protocols  
Configuration &  
Management  
Functions  
Higher Layer Protocols  
(Sending and Receiving  
Packets)  
Packet MUX/  
DEMUX  
Address  
Resolution  
Task  
Address Aging  
ASIC Database  
Manager  
Port  
Aggregation  
DMA and CPU  
Packet  
Interface  
Module  
Event Manager  
Task  
Configuration  
Mgmt. Task  
IXE2424  
Phy Driver  
MAC Driver  
Stats  
API’s  
Misc.  
API’s  
Interrupt  
Handler  
Priority  
Diffserv WRED  
QoS  
Mirror  
Filter  
VLAN MPLS  
Data Sheet  
17  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Summary descriptions and use of APIs supported by the IXE2424 are provided in Table 8.  
Table 8.  
APIs Supported by the IXE2424 (Sheet 1 of 2)  
API Module  
Description/Use  
Handles the interrupt from the IXE2424.  
Interrupt Handling  
OS Wrapper  
Provides services needed from the underlying real time operating system. You can  
port these wrappers to your target operating system.  
Provides a generic method for distributing information within a system. Allows  
different software modules to register for events of interest and makes the  
information distribution transparent, modular, and flexible.  
Notification Manager  
Enables you to program the performance of different functions. Provides functions  
for the ASIC, MAC, and Phy initialization, configuration, and management, which  
include functions for ASIC initialization and routines for bit level manipulations of  
the IXE2424 registers for various configurations.  
ASIC, MAC, and PHY  
Address Resolution  
MAC and Phy provide functions to initialize the Ethernet controllers built into the  
IXE2424 and theLXT9782 Phy (such as functions to change the speed, functions  
to change the duplex mode, etc.).  
Contains functions used for learning IP, IPX, and Layer 2 addresses.  
Include the ability to perform a routing table lookup (for IP and IPX Address  
Resolution—call into IP and IPX routing modules), determine the Ethernet address  
of the destination station or the next-hop (for routed packets whose destination is  
unresolved to determine the address programmed into swap entry—call into ARP  
module for IP or SAP module for IPX), etc.  
IP Configuration and  
Management  
Provides functions to send and receive packets between the IXE2424 and the  
CPU. The ASIC Driver provides a full set of functions supporting packet send and  
packet receive, and a separate set of functions that allow higher level software to  
manage the receive and send DMA buffer pools directly.  
DMA Interface  
Provides functions for configuring an ageing interval. The IXE2424 tracks the  
address record entries that have been accessed over the ageing interval. Different  
aging time intervals can be specified for Layer 2, Layer 3, and Layer 4 entries.  
Address Aging  
Provides functions for address learning in the software. The hardware provides a  
CAM interface to facilitate fast learning of addresses.  
Address Learning  
Supports configuring filters, mirrors, priorities, differentiated services, and quality of  
service for networks, nodes and ports. These APIs can be called from higher-layer  
software modules (such as SNMP agent) to configure these special rules for  
addresses.  
Filter, Mirror, Priority,  
DiffServ and Quality of  
Service  
Provides APIs (based on ports, 802.1Q tags, and multicast addresses) to make  
VLAN configuration and management easier for higher-layer software modules  
such as GVRP, GMRP, or SNMP agent (for user-configured VLANs).  
VLAN  
Provides counters that count different events required for both standard and draft  
MIB implementations and functions for gathering MAC, PHY, and ASIC statistics,  
including RMON stats. The APIs provided for higher-layer software modules are for  
reading these counters.  
Statistics Gathering  
18  
Data Sheet  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
Table 8.  
APIs Supported by the IXE2424 (Sheet 2 of 2)  
API Module  
Description/Use  
Support for port aggregation on all ports in groups of up to eight ports for the  
10/100 Mbps ports, and in a group of two ports for the Gigabit ports. Supports  
Ingress Aggregation Only and Ingress and Egress Aggregation modes of which  
Ingress Aggregation Only mode is the default.  
Link Aggregation  
Configuration and  
Management  
Used by Label Distribution Protocols to set up the MPLS forwarding plane in the  
IXE2424.  
MPLS  
Provides functions for all other miscellaneous configurations, such as adding static  
entries to address tables, creating static routes, creating default routes, broadcast  
and multicast storm control, etc. The Miscellaneous API module interfaces to  
various modules including ASIC Database Manager, Configuration Management  
task, Address Resolution task, etc., to provide these functionalities to higher-layer  
protocol stacks.  
Miscellaneous  
9.2  
Protocols  
The IXE2424 can perform extensive packet parsing and can obtain packet type (Type II, SNAP,  
etc.) and protocol (IP, GARP, GVRP, STP, etc.) information directly from the packet header.  
Enabled protocols are summarized in Table 9.  
Table 9.  
Protocols Enabled by the IXE2424  
Protocol  
Description/Use  
GxRP family protocols enabled include GARP, GARP Multicast Registration  
Protocol (GMRP), and GARP VLAN Registration Protocol (GVRP), which comprise  
a task within a MAC bridge system that interacts with other tasks and the driver  
through messages and events.  
GxRP  
GxRP services are the basis for implementing GMRP and GVRP. GMRP provides  
the ability to register (and de-register) Group Address membership in a MAC  
bridge. GVRP provides the functionality to register (and de-register) VLANs  
dynamically.  
Enabled IP protocol modules are the:  
•
•
•
•
•
•
•
Internet Protocol (IP)  
Address Resolution Protocol (ARP)  
Internet Control Message Protocol (ICMP)  
Internet Group Management Protocol (IGMP)  
Routing Information Protocol (RIPv1 and RIPv2)  
Internet Control Message Protocol (ICMP)  
User Datagram Protocol (UDP)  
IP  
IP modules can be organized as independent tasks or be grouped together into a  
single task depending upon the target environment and user requirement.  
Spanning Tree Algorithm and Protocol (STAP) functionality, which computes single  
spanning tree of all nodes in the arbitrary bridged network.  
Spanning Tree  
Stacking Control  
LACP  
Enables multiple Ethernet switches to be interconnected and managed as if they  
were a single larger switching device. All features supported as it would for a  
stand-alone system.  
Allows one or more links to be aggregated to form a link aggregation group so that  
a MAC client can treat the link aggregation group as a single link.  
Data Sheet  
19  
Intel Confidential  
 
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
10.0  
Feature List  
• 24 10/100 Mbps ports and 4 Gigabit port switching/routing in a single 792-pin TBGA chip  
• Integrated Gigabit and 10/100 Ethernet MACs  
• On-chip storage for port transmit queues  
• 10/100 Mbps ports configurable to half or full duplex  
• Wire speed switching and routing on every port  
• Hardware assisted address learning and aging  
• Link aggregation of all ports in groups up to 8 for 10/100 Mbps ports and 4 for Gigabit ports  
• Scatter-Gather based DMA support  
• Broadcast and multicast storm control with configurable per port settings  
• 66 MHz PCI Interface  
10.1  
Interfaces  
• SERDES & GMII interface for Gigabit ports and SMII interface for 10/100 Mbps ports  
• 10/100/1000 Mbps MACs for Gigabit Ports  
• PCI Rev 2.2 compliant 66MHz CPU interface with bus mastering capability for packet and  
unresolved entry transfers to CPU  
• SSRAM interface for address table sizes up to 40K entries (16K each for Layer 2, IP, and 8K  
IPX/MPLS entries) with no per port limits. In Layer 2 Only mode, address table sizes can be as  
large as 40K entries.  
10.2  
Layer 3/ Layer 4  
• Packet by packet IP and IPX routing in hardware  
• Layer 4 application level intelligence for IP switching and routing  
• Layer 2 switching for protocols other than IP and IPX  
• Automatic recognition of Ethernet Type II, 802.3, and SNAP packets  
• 256 IP networks with no per port limit. The same IP network can span multiple ports.  
• IP nodes can belong to up to 256 multicast groups on any port.  
10.3  
MPLS Switching  
• Supports MPLS switching on all ports  
• Device can work as an Ingress/Egress MPLS/IP router in addition to being used as a pure  
MPLS forwarding node  
20  
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
• QoS, WRED, Diffserv are also supported for MPLS packets  
10.4  
10.5  
IEEE Standards  
• 802.1D, 1998 edition which includes 802.1p Priority and Class of Service standard  
• 802.1Q VLAN standard  
• 802.3, 1998 edition which includes 802.3u Fast Ethernet standard, 802.3z Gigabit standard,  
and 802.3x Flow control standard  
• Proposed 802.1ad standard  
VLAN Configuration  
based on:  
• 802.1Q tags  
• Ports  
• Addresses  
• Protocols  
10.6  
Filtering  
based on:  
• Ports  
• Source Ethernet, IP, or IPX address  
• Destination Ethernet, IP, or IPX address  
• Source-destination Ethernet, IP, or IPX address pairs  
• MPLS label  
• End to end IP applications  
• Protocols  
10.7  
Class of Service  
based on:  
• 802.1p tags  
• Ports  
• Source Ethernet, IP, or IPX address  
• Destination Ethernet, IP, or IPX address  
• Source-destination Ethernet, IP, or IPX address pairs  
Data Sheet  
21  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
• MPLS label  
• End to end IP applications  
• Protocols  
• Support for Differential Services based on IETF RFC 2474  
10.8  
Port Mirroring  
based on:  
• Ports  
• Source Ethernet, IP, or IPX address  
• Destination Ethernet, IP, or IPX address  
• Source-destination Ethernet, IP, or IPX address pairs  
• MPLS label  
• End to end IP applications  
• Protocols  
10.9  
Bandwidth Management  
based on:  
• Source Ethernet, IP, or IPX address  
• Destination Ethernet, IP, or IPX address  
• Source-destination Ethernet, IP, or IPX address pairs  
• MPLS label  
• End to end IP applications  
10.10  
Queues  
• Two queues for packets from CPU; to allow prioritizing of packet types  
• Four queues for CPU packets; to allow prioritizing of packet types  
• Four queues for unresolved packets to CPU; to allow prioritizing of unresolved types  
• Four queues per port with user configurable priorities and weighted fair queuing  
• WRED implemented for all queues  
10.11  
Counters  
based on:  
22  
Data Sheet  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
• EtherStats group of RMON  
• Proposed SMON standard  
• RFC 1573 and Ethernet interfaces MIB (RFC 1643)  
10.12  
10.13  
Protocols  
• Hardware enabling for BPDU, GVRP, GMRP, IGMP, ICMP packets  
• Hardware enabling for routing protocols such as RIP, IPX/RIP, IPX/SAP, OSPF, DVMRP  
• Hardware enabling for VoIP packets  
• Hardware enabling for IPSec Packets  
Low Cost Mode Of Operation  
• Supports building a low cost 24 + 4 Layer 2 only switch with no external address table  
SSRAM  
• Up to 6K Layer 2 addresses and 64 802.1Q VLANs can be supported without external address  
table SSRAM  
Data Sheet  
23  
Intel Confidential  
Intel® Media Switch IXE2424 10/100+Gigabit L2/3/4 Advanced Device  
24  
Data Sheet  
Intel Confidential  
厂商 型号 描述 页数 下载

INTEL

 		IXE2412 [ Interface Circuit, PBGA600, 40 X 40 MM, 1.27 MM PITCH, TBGA-600 ] 26 页

INTEL

 		IXE2412EA [ Interface Circuit, PBGA600, TBGA-600 ] 26 页

INTEL

 		IXE2412EE [ Interface Circuit, PBGA600, TBGA-600 ] 26 页

INTEL

 		IXE2424EA [ Interface Circuit, PBGA792, TBGA-792 ] 28 页

INTEL

 		IXE2426EA [ Interface Circuit, PBGA792, TBGA-792 ] 24 页

INTEL

 		IXE2426EE [ Interface Circuit, PBGA792, TBGA-792 ] 24 页

INTEL

 		IXE5416 [ Support Circuit, PBGA836, EBGA-836 ] 16 页

ETC

 		IXE5418 电信/数据通信\n[ Telecomm/Datacomm ] 30 页

IXYS

 		IXEH25N120 NPT3 IGBT[ NPT3 IGBT ] 4 页

IXYS

 		IXEH25N120D1 [ Insulated Gate Bipolar Transistor, 36A I(C), 1200V V(BR)CES, N-Channel, TO-247AD, PLASTIC PACKAGE-3 ] 4 页

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