WV3HG32M72EER-AD6
White Electronic Designs
PRELIMINARY
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
534
403
Units
IDD0
*
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,400
1,355
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as IDAD6W
IDD1
*
1,490
1,400
mA
Precharge power-down current;
IDD2P**
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
572
725
770
572
725
770
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE;
Data bus inputs are FLOATING
I
DD2Q**
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD2N**
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
770
635
770
635
mA
mA
IDD3P**
Active standby current;
I
DD3N**
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,130
2,075
1,085
1,715
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
IDD4W
*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS
=
IDD4R
*
1,940
1,670
mA
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
Burst auto refresh current;
IDD5
*
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,985
45
1,940
45
mA
mA
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
IDD6**
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address
=
IDD7
*
2,795
2,795
mA
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
Notes:
DD specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
I
* Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
September 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
