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2T13K33MDBVREPG4

型号：

2T13K33MDBVREPG4

描述：

处理器监控电路和窗口看门狗[ PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG ]

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

16 页

PDF大小：

452 K

下载PDF手册
TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG  
FEATURES  
APPLICATIONS  
•
Applications Using DSPs, Microcontrollers,  
or Microprocessors  
•
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
•
•
•
Safety Critical Systems  
Automotive Systems  
Healing Systems  
•
•
Extended Temperature Performance of -55°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
TPS3813  
DBV PACKAGE  
(TOP VIEW)  
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
1
2
3
6
5
4
RESET  
WDR  
WDI  
Window-Watchdog With Programmable Delay  
and Window Ratio  
GND  
•
•
•
6-Pin SOT-23 Package  
V
DD  
WDT  
Supply Current of 9 µA (Typ)  
Power On Reset Generator With a Fixed  
Delay Time of 25 ms  
ACTUAL SIZE  
3,00 mm x 3,00 mm  
•
•
Precision Supply Voltage Monitor 2.5 V, 3 V,  
3.3 V, 5 V  
Open-Drain Reset Output  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION  
The TPS3813 family of supervisory circuits provides circuit initialization and timing supervision, primarily for  
DSPs and processor-based systems.  
During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the  
supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage  
(VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset.  
The delay time, td = 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply  
voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components  
are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage  
divider.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
TYPICAL OPERATING CIRCUIT  
V
DD  
0.1 µF  
0.1 µF  
R
V
DD  
V
DD  
WDR RESET  
TPS3813  
RESET  
uC  
WDT  
WDI  
I/O  
GND  
GND  
C
WP  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION (CONTINUED)  
For safety critical applications the TPS3813 family incorporates  
a so-called window-watchdog with  
programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting  
WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting  
WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813 within this window not to  
assert a RESET.  
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in  
a 6-pin SOT-23 package.  
The TPS3813 devices are characterized for operation over a temperature range of –55°C to 125°C.  
PACKAGE INFORMATION  
TA  
DEVICE NAME  
THRESHOLD VOLTAGE  
MARKING  
PLEM  
TPS3813J25MDBVREP  
TPS3813L30MDBVREP  
TPS3813K33MDBVREP  
TPS3813I50MDBVREP  
2.25 V  
2.64 V  
2.93 V  
4.55 V  
PLFM  
–55°C to 125°C  
PLGM  
PLHM  
ORDERING INFORMATION  
TPS381  
3
J
25  
DBV  
R
Reel  
Package  
Nominal Supply Voltage  
Nominal Threshold Voltage  
Functionality  
Family  
TPS3813 FUNCTION/TRUTH  
TABLE  
VDD > VIT  
RESET  
0
1
L
H
2
Submit Documentation Feedback  
TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
RESET  
Oscillator  
WDT  
Reset Logic  
and Timer  
Detection  
Circuit  
GND  
V
DD  
Power to circuitry  
Watchdog  
Ratio  
R
1
WDR  
WDI  
Detection  
+
_
R
2
Bandgap  
Voltage  
Reference  
Rising Edge  
Detection  
GND  
GND  
GND  
V
DD  
V
IT  
0.6 V  
t
t
t
t
d
d
d
RESET  
Output Condition  
Undefined  
Output Condition  
Undefined  
t
WDI  
t
1st Window  
Without Lower  
Boundary  
3rd Window  
With Lower  
Boundary  
2nd Window  
With Lower  
Boundary  
Trigger Pulse  
1st Window  
Without Lower  
Boundary  
3rd Window  
With Lower  
Boundary  
Lower Window  
2nd Window  
With Lower  
Boundary  
1st Window  
Boundary  
Without Lower  
Boundary  
Figure 1. Timing Diagram  
The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same  
time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the  
different oscillator frequency. This is described in more detail in the following section. The timing diagram and  
especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description.  
3
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
GND  
NO.  
2
I
O
I
Ground  
RESET  
VDD  
6
Open-drain reset output  
4
Supply voltage and supervising input  
Watchdog timer input  
WDI  
1
I
WDR  
WDT  
5
I
Selectable watchdog window ratio input  
Programmable watchdog delay input  
3
I
DETAILED DESCRIPTION  
IMPLEMENTED WINDOW-WATCHDOG SETTINGS  
There are two different ways to set up the watchdog window. The first way is to use the implemented timing  
which is a default setting. Or, the default settings can be activated by wiring the WDT and WDR pin to VDD or  
GND. There are a total of four different timings available with these settings which are listed in the table below.  
SELECTED OPERATION MODE  
WINDOW FRAME  
Max = 0.3 s  
Typ = 0.25 s  
Min = 0.2 s  
Max = 0.3 s  
Typ = 0.25 s  
Min = 0.2 s  
Max = 3 s  
LOWER WINDOW FRAME  
Max = 9.46 ms  
Typ = 7.86 ms  
Min = 6.27 ms  
Max = 2.43 ms  
Typ = 2 ms  
WDR = 0 V  
WDT = 0 V  
WDR = VDD  
WDR = 0 V  
WDR = VDD  
Min = 1.58 ms  
Max = 93.8 ms  
Typ = 78.2 ms  
Min = 62.5 ms  
Max = 23.5 ms  
Typ = 19.6 ms  
Min = 15.6 ms  
Typ = 2.5 s  
Min = 2 s  
WDT = VDD  
Max = 3 s  
Typ = 2.5 s  
Min = 2 s  
To visualize the values named in the table, a timing diagram (see Figure 2) was prepared. The timing diagram is  
used to describe the upper and lower boundary settings. For an application, the important boundaries are the  
tboundary,max and twindow,min. Within these values, the watchdog timer should be retriggered to avoid a timeout  
condition or a boundary violation in the event of a trigger pulse in the lower boundary. The values in the table  
above are typical and worst case conditions. They are valid over the whole temperature range of –55°C to  
125°C.  
In the shaded area of Figure 2, it cannot be predicted if the device will detect a violation or not and release a  
reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between  
twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas.  
WDI  
Detection of  
Rising Edge  
Window Frame to Reset the WDI  
t
t
boundary, min  
t
boundary, typ  
t
boundary, max  
t
window, min  
t
window, typ  
t
window, max  
Figure 2. Upper and Lower Boundary Visualization  
4
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
TIMING RULES OF WINDOW-WATCHDOG  
After the reset of the supervisor is released, the lower boundary of the first WDI window is disabled. However,  
after the first WDI pulse low-to-high transition is detected, the lower boundary function of the window is enabled.  
All further WDI pulses will need to fit into the configured window frame.  
PROGRAMMABLE WINDOW-WATCHDOG BY USING AN EXTERNAL CAPACITOR  
The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT pin  
and GND. Common consumer electronic capacitors can be used to implement this feature. They should have  
low ESR and low tolerances since the tolerances have to be considered if the calculations are performed. The  
first formula is used to calculate the upper window frame. After calculating the upper window frame, the lower  
boundary can be calculated. As in the last example, the most important values are the tboundary,max and twindow,min  
.
The trigger pulse has to fit into this window frame.  
The external capacitor should have a value between a minimum of 47 pF and a maximum of 63 nF.  
SELECTED OPERATION MODE  
WINDOW FRAME  
twindow,max = 1.25 x twindow,typ  
twindow,min = 0.75 x twindow,typ  
WDT = external capacitor C(ext) WDR = 0 V and WDR = VDD  
C
(ext)  
t
+
) 1   6.25 ms  
ǒ Ǔ  
window,typ  
15.55 pF  
(1)  
LOWER BOUNDARY CALCULATION  
The lower boundary can be calculated based on the values given in the switching characteristics. Additionally,  
facts have to be taken into account to verify that the lower boundary is where it is expected. Since the internal  
oscillator of the window watchdog is running free, any rising edge at the WDI pin will be taken into account at  
the next internal clock cycle. This happens regardless of the external source. Since the shift between internal  
and external clock is not known, it is best to consider the worst case condition for calculating this value.  
SELECTED OPERATION MODE  
LOWER BOUNDARY OF FRAME  
tboundary,max = twindow,max / 23.5  
tboundary,typ = twindow,typ / 25.8  
tboundary,min = twindow,min / 28.7  
tboundary,max = twindow,max / 51.6  
tboundary,typ = twindow,typ / 64.5  
tboundary,min = twindow,min / 92.7  
WDR = 0 V  
WDT = external capacitor C(ext)  
WDR = VDD  
WATCHDOG SOFTWARE CONSIDERATIONS  
To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more  
closely, it is recommended that the watchdog be set and reset at different points in the program rather than  
pulsing the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the  
watchdog trigger pulses should be set to different timings inside the window frame to release a defined reset, if  
the program should hang in any subroutine. This allows the window watchdog to detect timeouts of the trigger  
pulse as well as pulses that distort the lower boundary.  
APPLICATION EXAMPLE  
A typical application example (see Figure 3) is used to describe the function of the watchdog in more detail.  
To configure the window watchdog function, two pins are provided by the TPS3813. These pins set the window  
timeout and ratio.  
The window watchdog ratio is a fixed ratio, which determines the lower boundary of the window frame. It can be  
configured in two different frame sizes.  
5
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
If the window watchdog ratio pin (WDR) is set to VDD, Position 1 in Figure 3, then the lower window frame is a  
value based on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT)  
connected to GND, it is a ratio of 1:124.9, for WDT connected to VDD, it is a ratio of 1:127.7, and for an external  
capacitor connected to WDT, it is a ratio of 1:64.5.  
If the window watchdog ratio pin (WDR) is set to GND, Position 2, the lower window frame will be a value based  
on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT) connected to  
GND, it will be a ratio of 1:31.8, for WDT connected to VDD it will be 1:32, and for an external capacitor  
connected to WDT it will be 1:25.8.  
The watchdog timeout can be set in two fixed timings of 0.25 seconds and 2.5 seconds for the window or can by  
programmed by connecting a external capacitor with a low leakage current at WDT.  
Example: If the watchdog timeout pin (WDT) is connected to VDD, the timeout will be 2.5 seconds. If the window  
watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower  
boundary is 19.6 ms.  
V
DD  
0.1 µF  
0.1 µF  
V
DD  
R
Position 1  
V
DD  
V
DD  
See Note A  
Position 2  
See Note B  
WDR  
WDT  
RESET  
RESET  
I/O  
TPS3813  
GND  
Position 4  
uC  
See Note D  
WDI  
Position 5  
See Note E  
C
(ext)  
Position 3  
See Note C  
GND  
V
DD  
A. Watchdog window ratio  
B. Watchdog timeout set to typical 2.5 sec  
C. Watchdog timeout programmed by external capacitor  
D. Watchdog timeout set to typical 0.25 sec  
Figure 3. Application Example  
6
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
(1)  
UNIT  
7 V  
Supply voltage(2)  
VDD RESET  
–0.3 V to VDD + 0.3 V  
–0.3 V to 7 V  
5 mA  
(2)  
All other pins  
IOL  
IOH  
IIK  
Maximum low output current  
Maximum high output current  
Input clamp current (VI < 0 or VI > VDD  
–5 mA  
)
±20 mA  
IOK  
Output clamp current (VO < 0 or VO > VDD  
Continuous total power dissipation  
Operating free-air temperature range  
Storage temperature range  
)
±20 mA  
See Dissipation Rating Table  
–55°C to 125°C  
–65°C to 150°C  
260°C  
TA  
Tstg  
Soldering temperature  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to GND. For reliable operation, the device should not be operated at 7 V for more than t = 1000h  
continuously.  
DISSIPATION RATING TABLE  
TA < 25°C  
POWER RATING  
DERATING FACTOR  
ABOVE TA = 25°C  
TA = 70°C  
POWER RATING  
TA = 85°C  
POWER RATING  
PACKAGE  
DBV  
437 mW  
3.5 mW/°C  
280 mW  
227 mW  
100  
10  
1
120  
125  
130  
135  
140  
145  
150  
155  
160  
Continuous T − 5C  
J
Figure 4. TPS3813K33DBV Wirebond Life  
7
Submit Documentation Feedback  
TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
RECOMMENDED OPERATING CONDITIONS  
at specified temperature range  
MIN  
MAX UNIT  
VDD  
VI  
Supply voltage  
2
0
6
V
V
Input voltage  
VDD + 0.3  
VIH  
VIL  
∆t/∆V  
tw  
High-level input voltage  
Low-level input voltage  
Input transition rise and fall rate  
Pulse width of WDI trigger pulse  
Operating free-air temperature range  
0.7 x VDD  
V
0.3 x VDD  
100  
V
ns/V  
ns  
°C  
50  
TA  
–55  
125  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VDD = 2 V to 6 V, IOL = 500 µA  
MIN TYP MAX UNIT  
0.2  
VOL Low-level output voltage  
VDD = 3.3 V IOL = 2 mA  
VDD = 6 V, IOL = 4 mA  
0.4  
0.4  
0.2  
2.3  
2.7  
3
V
V
(1)  
Power up reset voltage  
VDD ≥ 1.1 V, IOL= 50 µA  
TPS3813J25  
TPS3813L30  
2.2 2.25  
2.58 2.64  
2.87 2.93  
2.8  
Negative-going input  
threshold  
voltage  
VIT  
TA = 25°C  
V
(2)  
TPS3813K33  
TA = Full Range  
3.1  
TPS3813I50  
TPS3813J25  
TPS3813L30  
TPS3813K33  
TPS3813I50  
4.45 4.55 4.65  
30  
35  
40  
60  
Vhys Hysteresis  
mV  
TA = 25°C  
–100  
–1000  
–100  
100  
1000  
100  
WDI, WDR  
WDT  
WDI = VDD = 6 V, WDR = VDD = 6 V  
TA = Full Range  
TA = 25°C  
IIH  
High-level input current  
WDT = VDD = 6 V, VDD > VIT,  
RESET = High  
TA = Full Range  
TA = 25°C  
–1000  
–100  
1000  
100  
nA  
nA  
WDI, WDR  
WDT  
WDI = 0 V, WDR = 0 V, VDD = 6 V  
WDT = 0 V, VDD > VIT, RESET = High  
VDD = VOH = 6 V  
TA = Full Range  
TA = 25°C  
–1000  
–100  
1000  
100  
IIL  
Low-level input current  
High-level output current  
TA = Full Range  
TA = 25°C  
–1000  
1000  
100  
IOH  
TA = Full Range  
1000  
13  
VDD = 2 V output unconnected  
VDD = 5 V output unconnected  
VI = 0 V to VDD  
9
20  
5
IDD  
CI  
Supply current  
µA  
25  
Input capacitance  
pF  
(1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.  
(2) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.  
TIMING REQUIREMENTS  
at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C  
PARAMETER  
Pulse width at VDD  
TEST CONDITIONS  
MIN  
TYP MAX UNIT  
tw  
VDD = VIT– + 0.2 V, VDD = VIT–– 0.2 V  
3
µs  
8
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
SWITCHING CHARACTERISTICS  
at RL = 1 MΩ, CL = 50 pF, TA = -55°C to 125°C  
PARAMETER  
TEST CONDITIONS  
TA = 25°C  
TA = Full Range  
MIN  
20  
TYP MAX UNIT  
25  
30  
40  
td  
Delay time  
V
DD ≥ VIT + 0.2 V, See Figure 1  
ms  
15  
WDT = 0 V  
0.25  
s
tt(out  
Watchdog time-out  
Upper limit  
WDT = VDD  
2.5  
)
(1)  
(2)  
WDT = programmable  
See  
ms  
WDR = 0 V, WDT = 0 V  
1:31.8  
1:32  
WDR = 0 V, WDT = VDD  
WDR = 0 V, WDT = programmable  
WDR = VDD, WDT = 0 V  
1:25.8  
1:124.9  
1:127.7  
1:64.5  
Watchdog window ratio  
Propagation (delay)  
WDR = VDD, WDT = VDD  
WDR = VDD, WDT = programmable  
VDD to RESET  
delay  
tPHL time, high-to-low-level  
output  
VIL = VIT - 0.2 V, VIH = VIT + 0.2 V  
30  
µs  
(1) 155 pF < C(ext) < 63 nF  
(2) (C(ext) ÷ 15.55 pF + 1) x 6.25 ms  
TYPICAL CHARACTERISTICS  
SUPPLY CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
vs  
SUPPLY VOLTAGE  
2
20  
18  
16  
14  
12  
WDI = GND,  
WDT = GND,  
WDR = GND  
V
DD  
= 2 V,  
WDI = GND,  
WDT = GND,  
WDR = GND  
1.75  
1.50  
85°C  
25°C  
1.25  
1
25°C  
10  
8
−40°C  
0.75  
0.50  
0.25  
0
85°C  
6
0°C  
0°C  
4
−40°C  
2
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
V
DD  
− Supply Voltage − V  
I
− Low-Level Output Current − mA  
OL  
Figure 5.  
Figure 6.  
9
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TPS3813J25-EP, TPS3813L30-EP  
TPS3813K33-EP, TPS3813I50-EP  
www.ti.com  
SGLS343A–MAY 2006–REVISED MAY 2006  
TYPICAL CHARACTERISTICS (continued)  
INPUT CURRENT  
vs  
INPUT VOLTAGE AT WDT  
NORMALIZED INPUT THRESHOLD VOLTAGE  
vs  
FREE-AIR TEMPERATURE AT VDD  
1000  
800  
600  
400  
200  
1.001  
1.000  
0.999  
0.998  
25°C  
85°C  
0°C  
0
−200  
−40°C  
0.997  
0.996  
0.995  
−400  
−600  
V
= 6 V,  
DD  
WDI = GND,  
WDR = GND  
WDI = Triggered,  
WDR = GND,  
WDT = GND  
−800  
−1000  
0
1
2
3
4
5
6
−40  
−20  
0
20  
40  
60  
80  
V − Input Voltage at WDT − V  
I
T
A
− Free-Air Temperature At V − °C  
DD  
Figure 7.  
Figure 8.  
MINIMUM PULSE DURATION AT VDD  
vs  
VDD THRESHOLD OVERDRIVE VOLTAGE  
20  
18  
16  
14  
12  
10  
8
6
4
2
0
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
V
DD  
− Threshold Overdrive Voltage − V  
Figure 9.  
10  
Submit Documentation Feedback  
PACKAGE OPTION ADDENDUM  
www.ti.com  
22-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
2T13K33MDBVREPG4  
TPS3813K33MDBVREP  
V62/06627-01XE  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOT-23  
DBV  
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOT-23  
SOT-23  
DBV  
DBV  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TPS3813K33-EP :  
Catalog: TPS3813K33  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Aug-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
TPS3813K33MDBVREP SOT-23  
DBV  
6
3000  
180.0  
9.0  
3.15  
3.2  
1.4  
4.0  
8.0  
Q3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Aug-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOT-23 DBV  
SPQ  
Length (mm) Width (mm) Height (mm)  
182.0 182.0 20.0  
TPS3813K33MDBVREP  
6
3000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
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