200 MS/s, 16-Bit Arbitrary Waveform Generator
Specifications
General
Onboard Clock (Internal VCXO)
Frequency accuracy.......................................... 25 ppm
Number of channels.........................................
1
DAC resolution ................................................. 16 bits
Maximum sampling rate .................................. 200 MS/s
Output paths..................................................... 1. Main Output Path setting with driver selected Low
Gain Amplifier or High Gain Amplifier
PLL reference clock sources............................. PXI_CLK10, CLK IN
Digital Data and Control, DDC (optional front panel connector)
Data output signals.......................................... 16 LVDS data lines (ANSI/TIA/EIA-644 compliant)
2. Direct Path optimized for IF applications
Start Trigger
Recommended Maximum Output Frequencies
Sources ............................................................ PFI <0:3>, PXI_TRIG<0:6>, PXI Star Trigger, Software, Immediate
Direct Path................................................. 80 MHz
Low Gain Path ........................................... 80 MHz
High Gain Path........................................... 40 MHz up to 12 Vpp (80 MHz up to 8 Vpp
Modes............................................................... Single, Continuous, Stepped, Burst
Markers
)
Destinations ..................................................... PFI <0:1>, PFI <4:5>, PXI_TRIG <0:6>
Analog Output
Quantity............................................................ 1 Marker per Segment
Amplitude range (full scale)
Waveform and Instruction Memory Utilization
Main output path....................................... 12 Vpp to 5.64 mVpp (50
Direct path................................................. 1 Vpp to 0.707 Vpp (50
Ω
load)
Ω
load)
8 MB Standard
32 MB Option
256 MB Option
512 MB Option
Offset range ..................................................... 50ꢀ of Amplitude Range (Signal plus offset not to
exceed amplitude range)
Onboard Memory Size 8,388,608 bytes 33,554,432 bytes 268,435,456 bytes 536,870,912 bytes
Output modes................................................... Function Generator Emulation, Arbitrary Waveform
and Arbitrary Sequence
Loop count........................................................ 1 to 16,777,215. Burst Trigger: Unlimited
Output impedance............................................ 50
DC Accuracy ..................................................... 0.4ꢀ of Amplitude 0.05ꢀ of offset 1 mV
AC amplitude accuracy .................................... 1.0ꢀ of Amplitude 1 mV at 50 kHz
Ωor 75Ω, software selectable
Output filter...................................................... Software enabled seven-pole elliptical analog filter
available on Main Output Path
Memory Limits
Arbitrary Waveform
Mode Maximum
Waveform Memory
Arbitrary Sequence
Mode Maximum
Waveform Memory1
Arbitrary Sequence
Mode Maximum
Waveforms1
Arbitrary Sequence
8 MB Standard
4,194,176
Samples
32 MB Option
16,777,088
Samples
256 MB Option
134,217,600
Samples
512 MB Option
268,435,328
Samples
Low Gain Passband Flatness (Typical)
5.000
4,194,120
Samples
16,777,008
Samples
134,217,520
Samples
268,435,200
Samples
0.000
-5.000
65,000
Samples
262,000
Samples
2,097,000
Samples
4,194,000
Samples
-10.000
-15.000
-20.000
-25.000
104,000
Samples
418,000
Samples
3,354,000
Samples
6,708,000
Samples
Mode Maximum
Segments in a Sequence2
Refer to detailed specifications for all trigger modes.
1Condition One or two segments in a sequence
2Condition: Waveform memory is <4,000 samples.
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
80.00
90.00
100.00
Frequency (MHz)
Power
Rise time .......................................................... < 1.8 ns for Main Output Low Gain Path
Fall time............................................................ < 2.1 ns for Main Output Low Gain Path
Pulse Aberration............................................... < 6 ꢀ for Main Output Low Gain Path
+3.3 VDC
2.0 A
2.0 A
+5 VDC
2.0 A
3.0 A
+12 VDC
0.46 A
0.46 A
-12 VDC
0.01 A
0.01 A
Total Power
22.2 W
27.2 W
Typical operating conditions
Maximum overload
Spectral Characteristics
Frequency
Direct Path
Low Gain Path
Comments
Total Harmonic Distortion
(THD)
Amplitude –1
dBFS
Physical
20 kHz
1 MHz
-85 dBc (0.006ꢀ) -81 dBc (0.009ꢀ)
Dimensions....................................................... Single 3U PXI slot
-87 dBc
-67 dBc
-80 dBc
-65 dBc
-60 dBc
-63 dBc
-60 dBc
-78 dBc
-63 dBc
-55 dBc
2nd through 6th
harmonics
Each tone is
-7 dBFS. 200kHz
spacing
Front panel connectors
10 MHz
10 MHz
40 MHz
70 MHz
CH0 ............................................................ SMB (Jack)
CLK IN........................................................ SMB (Jack)
PFI 0 ........................................................... SMB (Jack)
PFI 1 ........................................................... SMB (Jack)
Intermodulation Distortion
(IMD)
Digital data and control ................................... 68-pin VHDCI Female Receptacle
Typical
Environment
Average Noise Density
Operating temperature..................................... 0 to +55 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
Storage temperature........................................ -25 to +85 °C (Meets IEC-60068-2-1 and IEC-60068-2-2)
Relative humidity ............................................. 10 to 90ꢀ, noncondensing (Meets IEC 60068-2-56)
Amplitude Range
Average Noise Density
nV/√Hz dBm/Hz dBfs/Hz
Path
Vpk-pk
1
0.1
2
dBm
4
-16.0
10.0
25.6
Direct Path
Low Gain
Low Gain
High gain
25
14
45
-139
-144
-134
-118
-143.0
-128.0
-144.0
-143.6
Calibration
Self-calibration................................................. DC gain and offset
External calibration interval............................. 2 years
12
282
Sample Clock
Certifications and Compliances
Sources ............................................................ Internal Divide-by-N, Internal High-Resolution, External CLK
IN, External DDC Clk In, PXI star Trigger, PXI_TRIG <0:7>
Frequency resolution
Divide-by-N................................................ (200 MS/s) / N where 1
High Resolution ......................................... 1.06 µHz
CE Mark Compliance
Note
≤N 40
Unless otherwise noted, the following conditions were used for each specification:
A. Analog filter enabled
B. Signals terminated with 50
C. Direct path set to 1 Vpk-pk, Low Gain Amplifier Path set to 2 Vpk-pk,
and High Gain Amplifier Path set to 12 Vpk-pk
Ω
System Phase Noise and Jitter
System Phase
Noise Density
System Output
Jitter
< 1.3 ps rms
< 3.0 ps rms
< 1.1 ps rms
Comment
10 MHz carrier
D. Sample clock set to 200 MS/s
Divide-by-N
High Resolution
External Clock
-138 dBc/Hz (10 kHz offset)
-122 dBc/Hz (10 kHz offset)
-143 dBc/Hz (10 kHz offset)
Specifications subject to change without notice. Please see detailed specifications for more information.
2
National Instruments • Tel: (800) 433-3488 • Fax: (512) 683-9300 • info@ni.com • ni.com
