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9UMS9610CKLF

型号：

9UMS9610CKLF

描述：

电脑主时钟[ PC MAIN CLOCK ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

20 页

PDF大小：

135 K

下载PDF手册
DATASHEET  
PC MAIN CLOCK  
ICS9UMS9610  
Features/Benefits:  
Recommended Application:  
Poulsbo Based Ultra-Mobile PC (UMPC) - CK610  
•
Supports Dothan ULV CPUs with 100 to 200 MHz  
CPU outputs  
Output Features:  
•
Dedicated TEST/SEL and TEST/MODE pins saves  
isolation resistors on pins  
•
•
•
•
•
3 - CPU low power differential push-pull pairss  
3 - SRC low power differential push-pull pairs  
1 - LCD100 SSCD low power differential push-pull pair  
1 - DOT96 low power differential push-pull pair  
1 - REF, 14.31818MHz, 3.3V SE output  
•
•
•
•
CPU STOP# input for power manangment  
Fully integrated Vreg  
Integrated series resistors on differential outputs  
1.5V VDD IO, 1.5V VDD core, 3.3V VDD supply pin for  
REF  
Pin Configuration  
48 47 46 45 44 43 42 41 40 39 38 37  
CPU_STOP#_3.3 1  
CLKPWRGD#/PD_3.3 2  
X2 3  
36 *CR#2_1.5  
35 SRCT2_LPR  
34 SRCC2_LPR  
33 GNDSRC  
X1 4  
VDDREF_3.3 5  
REF_3.3_2x 6  
GNDREF 7  
32 SRCT1_LPR  
31 SRCC1_LPR  
30 VDDIO_1.5  
29 VDDCORE_1.5  
28 *CR#1_1.5  
27 SRCT0_LPR  
26 SRCC0_LPR  
25 GNDSRC  
9UMS9610  
VDDCORE_1.5 8  
FSC_L_1.5 9  
TEST_MODE_1.5 10  
TEST_SEL_1.5 11  
SCLK_3.3 12  
13 14 15 16 17 18 19 20 21 22 23 24  
48-pin MLF, 6x6 mm, 0.4mm pitch  
* indicates inputs with internal pull up of ~10Kohm to 1.5V  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
1
ICS9UMS9610  
PC MAIN CLOCK  
Pin Description  
Logic Level  
Input Level  
Tolerance (V)  
3.3  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
(V)  
3.3  
1
CPU_STOP#_3.3  
IN This active-low input stops all CPU clocks that are set to be stoppable.  
This level sensitive strobe determines when latch inputs are valid and are  
IN ready to be sampled. When high, this asynchronous input places the  
device into the power down state.  
2
CLKPWRGD#/PD_3.3  
3.3  
3.3  
3
4
5
6
7
8
X2  
X1  
OUT Crystal output, Nominally 14.318MHz  
IN Crystal input, Nominally 14.318MHz.  
PWR Power pin for the XTAL and REF clocks, nominal 3.3V  
OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength  
GND Ground pin for the REF outputs.  
N/A  
1.5  
3.3  
3.3  
0
N/A  
1.5  
3.3  
N/A  
N/A  
1.5  
VDDREF_3.3  
REF_3.3_2x  
GNDREF  
VDDCORE_1.5  
PWR 1.5V power for the PLL core  
1.5  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.  
9
FSC_L_1.5  
IN  
1.5  
1.5  
TEST_MODE is a real time input to select between Hi-Z and REF/N divider  
IN mode while in test mode. Refer to Test Clarification Table. Max input  
voltage is 1.5V.  
10 TEST_MODE_1.5  
11 TEST_SEL_1.5  
1.5  
3.3  
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V  
IN  
1 = All outputs are tri-stated for test  
0 = All outputs behave normally.  
1.5  
3.3  
12 SCLK_3.3  
IN Clock pin of SMBus circuitry, 3.3V tolerant.  
I/O Data pin for SMBus circuitry, 3.3V tolerant.  
PWR 1.5V power for the PLL core  
3.3  
3.3  
1.5  
1.5  
3.3  
3.3  
1.5  
1.5  
13 SDATA_3.3  
14 VDDCORE_1.5  
15 VDDIO_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
Complement clock of low power differential pair for 96.00MHz DOT clock.  
No 50ohm resistor to GND needed. No Rs needed.  
True clock of low power differential pair for 96.00MHz DOT clock. No  
50ohm resistor to GND needed. No Rs needed.  
16 DOT96C_LPR  
17 DOT96T_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
OUT  
18 GNDDOT  
19 GNDLCD  
GND Ground pin for DOT clock output  
GND Ground pin for LCD clock output  
0
0
N/A  
N/A  
Complement clock of low power differential pair for LCD100 SS clock. No  
50ohm resistor to GND needed. No Rs needed.  
True clock of low power differential pair for LCD100 SS clock. No 50ohm  
resistor to GND needed. No Rs needed.  
20 LCD100C_LPR  
21 LCD100T_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
OUT  
22 VDDIO_1.5  
23 VDDCORE_1.5  
24 *CR#0_1.5  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 1.5V power for the PLL core  
IN 1.5V Clock request for SRC0, 0 = enable, 1 = disable  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
2
ICS9UMS9610  
PC MAIN CLOCK  
Pin Description (continued)  
Logic Level  
Input Level  
Tolerance (V)  
N/A  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
(V)  
0
25 GNDSRC  
GND Ground pin for the SRC outputs  
Complementary clock of differential 0.8V push-pull SRC output with  
integrated 33ohm series resistor. No 50ohm resistor to GND needed.  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
26 SRCC0_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
27 SRCT0_LPR  
OUT  
28 *CR#1_1.5  
29 VDDCORE_1.5  
30 VDDIO_1.5  
IN 1.5V Clock request for SRC1, 0 = enable, 1 = disable  
PWR 1.5V power for the PLL core  
PWR Power supply for low power differential outputs, nominal 1.5V.  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
Complementary clock of differential 0.8V push-pull SRC output with  
integrated 33ohm series resistor. No 50ohm resistor to GND needed.  
31 SRCC1_LPR  
OUT  
0.8  
N/A  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
GND Ground pin for the SRC outputs  
32 SRCT1_LPR  
33 GNDSRC  
OUT  
0.8  
0
N/A  
N/A  
N/A  
Complementary clock of differential 0.8V push-pull SRC output with  
integrated 33ohm series resistor. No 50ohm resistor to GND needed.  
34 SRCC2_LPR  
OUT  
0.8  
True clock of differential 0.8V push-pull SRC output with integrated 33ohm  
series resistor. No 50ohm resistor to GND needed.  
IN 1.5V Clock request for SRC2, 0 = enable, 1 = disable  
35 SRCT2_LPR  
36 *CR#2_1.5  
37 FSB_L_1.5  
OUT  
0.8  
1.5  
1.5  
N/A  
1.5  
1.5  
Low threshold input for CPU frequency selection. Refer to input electrical  
characteristics for Vil_FS and Vih_FS values. 1.5V Max input voltage.  
IN  
Complementary clock of differential pair 0.8V push-pull CPU outputs with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
38 CPUC2_LPR  
39 CPUT2_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
OUT  
40 GNDCPU  
41 VDDIO_1.5  
42 VDDCORE_1.5  
GND Ground pin for the CPU outputs  
PWR Power supply for low power differential outputs, nominal 1.5V.  
PWR 1.5V power for the PLL core  
0
1.5  
1.5  
N/A  
1.5  
1.5  
Complementary clock of differential pair 0.8V push-pull CPU outputs with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
43 CPUC1_LPR  
44 CPUT1_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
OUT  
45 GNDCPU  
46 VDDIO_1.5  
GND Ground pin for the CPU outputs  
PWR Power supply for low power differential outputs, nominal 1.5V.  
0
1.5  
N/A  
1.5  
Complementary clock of differential pair 0.8V push-pull CPU outputs with  
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.  
True clock of differential pair 0.8V push-pull CPU outputs with integrated  
33ohm series resistor. No 50 ohm resistor to GND needed.  
47 CPUC0_LPR  
48 CPUT0_LPR  
OUT  
0.8  
0.8  
N/A  
N/A  
OUT  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
3
ICS9UMS9610  
PC MAIN CLOCK  
Funtional Block Diagram  
REF  
X1  
X2  
OSC  
SRC(2:0)  
CPU(2:0)  
CPU, SRC  
SS-PLL  
LCD100_SSC  
LCD  
SS-PLL  
96M  
Non-SS  
PLL  
DOT96MHz  
FSLC  
FSLB  
CKPWRGD/PD#  
CPU_STOP#  
CR(2:0)#  
Control  
Logic  
TESTSEL  
TESTMODE  
SMBDAT  
SMBCLK  
Power Groups  
Pin Number  
VDD GND  
Description  
41, 46  
Low power outputs  
VDDCORE_1.5V  
Low power outputs  
VDDCORE_1.5V  
Low power outputs  
VDDCORE_1.5V  
Low power outputs  
VDDCORE_1.5V  
Xtal, REF  
40, 45 CPUCLK  
42  
30  
25, 33 SRCCLK  
29  
22  
19  
LCDCLK  
23  
15  
14  
5
18 DOT 96Mhz  
7
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
4
ICS9UMS9610  
PC MAIN CLOCK  
Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
VDDxxx_3.3  
VDDxxx_1.5  
CONDITIONS  
Supply Voltage  
Supply Voltage  
MIN  
MAX  
3.9  
UNITS Notes  
3.3V Supply Voltage  
1.5V Supply Voltage  
V
V
1,2  
1,2  
2.1  
VDD_3.3+  
0.3V  
3.3_Input High Voltage  
1.5_Input High Voltage  
VIH3.3  
VIH1.5  
3.3V Inputs  
1.5V Inputs  
V
V
1,2,3  
1,2,3  
VDD_1.5+  
0.3V  
Minimum Input Voltage  
Storage Temperature  
Input ESD protection  
VIL  
Ts  
Any Input  
GND - 0.5  
-65  
V
°C  
V
1
-
150  
1,2  
1,2  
ESD prot  
Human Body Model  
2000  
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied, nor guaranteed.  
3 Maximum input voltage is not to exceed maximum VDD  
Electrical Characteristics - Input/Supply/Common Output Parameters  
PARAMETER  
Ambient Operating Temp  
3.3V Supply Voltage  
1.5V Supply Voltage  
SYMBOL  
CONDITIONS  
MIN  
MAX  
UNITS Notes  
Tambient  
No Airflow  
0
85  
°C  
V
1
1
1
VDDxxx_3.3  
VDDxxx_1.5  
3.3V +/- 5%  
1.5V +/- 5%  
3.135  
1.425  
3.465  
1.575  
V
VDDxx_3.3  
0.3  
+
3.3V Input High Voltage  
3.3V Input Low Voltage  
1.5V Input High Voltage  
VIHSE3.3  
VILSE3.3  
VIHSE1.5  
Single-ended inputs  
Single-ended inputs  
Single-ended inputs  
2
V
V
V
1
1
1
VSS - 0.3  
1.2  
0.8  
VDDxxx_1.5  
0.3  
+
1.5V Input Low Voltage  
Input Leakage Current  
VILSE1.5  
IIN  
Single-ended inputs  
VIN = VDD , VIN =GND  
VSS - 0.3  
-5  
0.3  
V
1
1
5
uA  
Inputs with pull or pull down  
resistors  
Input Leakage Current  
IINRES  
-200  
2.4  
200  
uA  
1
VIN = VDD , VIN =GND  
Output High Voltage  
Output Low Voltage  
VOHSE  
VOLSE  
Single-ended output, IOH = -1mA  
Single-ended output, IOL = 1 mA  
V
V
1
1
0.4  
1.5  
Low Threshold Input-  
High Voltage  
Low Threshold Input-  
Low Voltage  
VIH_FS  
VIL_FS  
1.5 V +/-5%  
1.5 V +/-5%  
0.7  
V
V
1
1
VSS - 0.3  
0.35  
IDD_3.3  
3.3V supply  
10  
45  
mA  
mA  
1
1
IDD_DEFAULT1.5  
1.5V core supply, LCDPLL off  
Operating Supply Current  
IDD_LCDEN1.5  
1.5V core supply, LCDPLL enabled  
55  
mA  
1
1.5V supply, Differential IO current,  
all outputs enabled  
IDD_IO1.5  
IDD_PD3.3  
15  
0.5  
0.5  
mA  
mA  
mA  
1
1
1
3.3V supply, Power Down Mode  
1.5V CORE supply, Power Down  
Mode  
IDD_PD1.5CORE  
Power Down Current  
IDD_PD1.5IO  
1.5V IO supply, Power Down Mode  
VDD = 3.3 V  
0.1  
mA  
1
Input Frequency  
Pin Inductance  
Fi  
15  
7
MHz  
nH  
pF  
2
1
1
1
1
Lpin  
CIN  
Logic Inputs  
Output pin capacitance  
X1 & X2 pins  
1.5  
5
Input Capacitance  
COUT  
CINX  
6
pF  
3
5
pF  
Spread Spectrum Modulation  
Frequency  
fSSMOD  
Triangular Modulation  
30  
33  
kHz  
1
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
5
ICS9UMS9610  
PC MAIN CLOCK  
AC Electrical Characteristics - Input/Common Parameters  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
MAX  
1.8  
UNITS Notes  
From VDD Power-Up or de-  
assertion of PD# to 1st clock  
Differential output enable after  
PD# de-assertion  
Clk Stabilization  
TSTAB  
ms  
us  
1
1
1
Tdrive_PD#  
Tdrive_CPU  
TDRPD  
300  
6
CPU output enable after  
CPU_STOP# de-assertion  
TDRSRC  
2
Cycles  
Tfall_PD#  
TFALL  
TRISE  
5
5
ns  
ns  
1
1
Fall/rise time of PD# and  
CPU_STOP# inputs  
Trise_PD#  
AC Electrical Characteristics - Low Power Differential Outputs  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
MAX  
4
UNITS NOTES  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Rise/Fall Time Variation  
Maximum Output Voltage  
Minimum Output Voltage  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Duty Cycle  
tSLR  
Differential Measurement  
Differential Measurement  
Single-ended Measurement  
Includes overshoot  
0.6  
V/ns  
V/ns  
ps  
1,2  
tFLR  
0.6  
4
1,2  
tSLVAR  
125  
1150  
1
VHIGH  
mV  
mV  
mV  
mV  
mV  
%
1
VLOW  
Includes undershoot  
-300  
300  
300  
1
VSWING  
VXABS  
VXABSVAR  
DCYC  
Differential Measurement  
Single-ended Measurement  
Single-ended Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
Differential Measurement  
1
550  
140  
55  
1,3,4  
1,3,5  
45  
1
1
1
1
1
1
1
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
LCD Jitter - Cycle to Cycle  
CPU[2:0] Skew  
CPUJC2C  
SRCJC2C  
DOTJC2C  
LCDJC2C  
CPUSKEW10  
SRCSKEW  
85  
ps  
125  
250  
85  
ps  
ps  
ps  
100  
250  
ps  
SRC[2:0] Skew  
ps  
Electrical Characteristics - REF-14.318MHz  
PARAMETER  
SYMBOL  
CONDITIONS  
see Tperiod min-max values  
14.318MHz output nominal  
14.318MHz output nominal  
IOH = -1 mA  
MIN  
-300  
MAX  
300  
UNITS Notes  
Long Accuracy  
ppm  
ppm  
ns  
ns  
V
1,2  
2
Clock period  
Tperiod  
Tabs  
69.8203  
69.8203  
2.4  
69.8622  
70.86224  
Absolute min/max period  
Output High Voltage  
Output Low Voltage  
2
VOH  
1
VOL  
IOL = 1 mA  
0.4  
-33  
V
1
VOH @MIN = 1.0 V,  
Output High Current  
Output Low Current  
IOH  
-33  
30  
mA  
mA  
1
1
V
OH@MAX = 3.135 V  
VOL @MIN = 1.95 V,  
OL @MAX = 0.4 V  
IOL  
38  
V
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Duty Cycle  
tSLR  
tFLR  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
1
1
4
4
V/ns  
V/ns  
%
1
1
1
1
dt1  
45  
55  
Jitter  
tjcyc-cyc  
VT = 1.5 V  
1000  
ps  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
6
ICS9UMS9610  
PC MAIN CLOCK  
Electrical Characteristics - SMBus Interface  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
2.7  
MAX  
3.6  
UNITS Notes  
SMBus Voltage  
VDD  
V
V
1
1
Low-level Output Voltage  
Current sinking at  
VOLSMB = 0.4 V  
VOLSMB  
@ IPULLUP  
0.4  
IPULLUP  
SMB Data Pin  
4
mA  
1
SCLK/SDATA  
Clock/Data Rise Time  
SCLK/SDATA  
(Max VIL - 0.15) to  
(Min VIH + 0.15)  
(Min VIH + 0.15) to  
(Max VIL - 0.15)  
TRI2C  
TFI2C  
1000  
300  
ns  
ns  
1
1
1
Clock/Data Fall Time  
Maximum SMBus Operating  
Frequency  
FSMBUS  
Block Mode  
100  
kHz  
Notes on Electrical Characteristics:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Slew rate measured through Vswing centered around differential zero  
3 Vxabs is defined as the voltage where CLK = CLK#  
4 Only applies to the differential rising edge (CLK rising and CLK# falling)  
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of  
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets  
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate  
calculations.  
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz  
7 Operation under these conditions is neither implied, nor guaranteed.  
8 Maximum input voltage is not to exceed maximum VDD  
9 See PCI Clock-to-Clock Delay Figure  
Clock Periods Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Lg+  
Symbol  
Lg-  
-SSC  
-ppm error  
0ppm  
+ ppm error  
+SSC  
Absolute Short-term Long-Term  
Period Average Average  
Long-Term Short-term  
Period  
Period  
Average  
Average  
Definition  
Minimum Minimum Minimum  
Absolute Absolute Absolute  
Nominal  
Maximum  
Maximum Maximum  
Period  
9.87400  
9.91400  
7.41425  
Period  
9.99900  
9.99900  
7.49925  
Period  
9.99900  
9.99900  
7.49925  
Units  
ns  
Notes  
1,2  
10.00000  
10.00000  
7.50000  
10.00100  
10.00100  
7.50075  
10.05130  
10.05130  
7.53845  
10.17630  
10.13630  
7.62345  
SRC 100  
CPU 100  
CPU 133  
ns  
1,2  
ns  
1,2  
Clock Periods Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
0.1s  
0.1s  
0.1s  
1us  
1 Clock  
Lg+  
Symbol  
Lg-  
-SSC  
-ppm error  
0ppm  
+ ppm error  
+SSC  
Absolute Short-term Long-Term  
Period Average Average  
Long-Term Short-term  
Period  
Period  
Average  
Average  
Definition  
Minimum Minimum Minimum  
Absolute Absolute Absolute  
Nominal  
Maximum  
Maximum Maximum  
Period  
9.87400  
9.91400  
7.41425  
10.16560  
Period  
Period  
9.99900  
9.99900  
7.49925  
10.41560  
Units  
ns  
Notes  
1,2  
10.00000  
10.00000  
7.50000  
10.00100  
10.00100  
7.50075  
10.17630  
10.13630  
7.62345  
SRC 100  
CPU 100  
CPU 133  
DOT 96  
ns  
1,2  
ns  
1,2  
10.41670  
10.41770  
10.66770  
ns  
1,2  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
7
ICS9UMS9610  
PC MAIN CLOCK  
Table 1: CPU Frequency Select Table  
CPU  
MHz  
SRC  
MHz  
DOT  
MHz  
LCD100 REF  
MHz MHz  
FSLC1 FSLB1  
0
0
1
1
0
1
0
1
133.33  
166.67  
100.00  
200.00  
100.00  
96.00  
100.00 14.318  
1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
Table 2: LCD Spread Select Table (Pin 20/21)  
Spread  
B1b5  
B1b4  
B1b3  
Comment  
%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5%  
-1%  
LCD100  
LCD100  
LCD100  
LCD100  
-2%  
-2.5%  
+/- 0.25% LCD100  
+/-0.5% LCD100  
+/-1%  
LCD100  
+/-1.25% LCD100  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
8
ICS9UMS9610  
PC MAIN CLOCK  
General I2C serial interface information for the ICS9UMS9610  
How to Write:  
How to Read:  
• Controller (host) will send start bit.  
• Controller (host) sends the write address D2(H)  
• ICS clock will acknowledge  
• Controller (host) sends a start bit.  
• Controller (host) sends the write address D2(H)  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte location = N  
• ICS clock will acknowledge  
• Controller (host) sends the begining byte  
location = N  
• Controller (host) sends the data byte count = X  
• ICS clock will acknowledge  
• Controller (host) starts sending Byte N through  
Byte N + X -1  
• ICS clock will acknowledge  
• Controller (host) will send a separate start bit.  
• Controller (host) sends the read address D3(H)  
• ICS clock will acknowledge  
• ICS clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• ICS clock will send the data byte count = X  
• ICS clock sends Byte N + X -1  
• ICS clock sends Byte 0 through byte X (if X(H)  
was written to byte 8).  
• Controller (host) will need to acknowledge each byte  
• Controllor (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
ICS (Slave/Receiver)  
Controller (Host)  
ICS (Slave/Receiver)  
T
starT bit  
starT bit  
T
Slave Address D2(H)  
Slave Address D2(H)  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
RT  
Repeat starT  
Slave Address D3(H)  
RD  
ReaD  
ACK  
Data Byte Count = X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
9
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
Bit(s) Pin #  
0
PLL & Divider Enable Register  
Name  
Description  
Type  
0
1
Default  
This bit controls whether the PLL driving the  
CPU and SRC clocks is enabled or not.  
This bit controls whether the PLL driving the  
DOT and clock is enabled or not.  
This bit controls whether the PLL driving the  
LCD clock is enabled or not.  
7
6
-
-
PLL1 Enable  
PLL2 Enable  
PLL3 Enable  
RW  
0 = Disabled  
1 = Enabled  
1
RW  
RW  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1
5
4
-
-
1
0
Reserved  
This bit controls whether the CPU output  
divider is enabled or not.  
CPU Divider  
Enable  
3
2
1
-
-
-
RW  
RW  
RW  
RW  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
1
1
1
This bit should be automatically set to  
‘0’ if bit 7 is set to ‘0’.  
NOTE:  
This bit controls whether the SRC output  
divider is enabled or not.  
Divider Enable NOTE: This bit should be automatically set to  
‘0’ if bit 7 is set to ‘0’.  
SRC Output  
This bit controls whether the LCD output  
LCD Output  
Divider Enable  
divider is enabled or not.  
This bit should be automatically set to  
‘0’ if bit 5 is set to ‘0’.  
NOTE:  
This bit controls whether the DOT output  
divider is enabled or not.  
DOT Output  
Divider Enable  
0
-
This bit should be automatically set to  
‘0’ if bit 6 is set to ‘0’.  
NOTE:  
Byte  
Bit(s) Pin #  
1
PLL SS Enable/Control Register  
Name  
Description  
Type  
0
1
Default  
This bit controls whether PLL1 has spread  
enabled or not. Spread spectrum for PLL1 is  
set at -0.5% down-spread. Note that PLL1  
drives the CPU and SRC clocks.  
7
PLL1 SS Enable  
RW  
0 = Disabled  
1 = Enabled  
1
This bit controls whether PLL3 has spread  
enabled or not. Note that PLL3 drives the SSC  
clock, and that the spread spectrum amount is  
set in bits 3-5.  
These 3 bits select the frequency of PLL3 and  
the SSC clock when Byte 1 Bit 6 (PLL3  
Spread Spectrum Enable) is set.  
6
PLL3 SS Enable  
PLL3 FS Select  
RW  
RW  
0 = Disabled  
1 = Enabled  
1
5
4
3
2
1
0
0
0
0
0
0
0
See Table 2: LCD Spread Select  
Table  
Reserved  
Reserved  
Reserved  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
10  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
Bit(s) Pin #  
2
Output Enable Register  
Name  
Description  
Type  
0
1
Default  
This bit controls whether the CPU[0] output  
buffer is enabled or not.  
This bit controls whether the CPU[1] output  
buffer is enabled or not.  
This bit controls whether the CPU[2] output  
buffer is enabled or not.  
This bit controls whether the SRC[0] output  
buffer is enabled or not.  
This bit controls whether the SRC[1] output  
buffer is enabled or not.  
This bit controls whether the SRC[2] output  
buffer is enabled or not.  
This bit controls whether the DOT output  
buffer is enabled or not.  
This bit controls whether the LCD output buffer  
is enabled or not.  
7
CPU0 Enable  
CPU1 Enable  
CPU2 Enable  
SRC0 Enable  
SRC1 Enable  
SRC2 Enable  
DOT Enable  
RW  
0 = Disabled  
1 = Enabled  
1
6
5
4
3
2
1
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
1
1
1
1
1
1
LCD100 Enable  
Byte  
Bit(s) Pin #  
3
Output Control Register  
Name  
Description  
Type  
0
1
Default  
7
6
Reserved  
Reserved  
0
0
This bit controls whether the REF output  
buffer is enabled or not.  
5
4
3
REF Enable  
RW  
RW  
0 = Disabled  
1 = Enabled  
1
00 = Slow Edge Rate  
These bits control the edge rate of the REF  
clock.  
01 = Medium Edge Rate  
10 = Fast Edge Rate  
11 = Reserved  
REF Slew  
10  
This bit controls whether the CPU[0] output  
buffer is free-running or stoppable. If it is set  
to stoppable the CPU[0] output buffer will be  
disabled with the assertion of CPU_STP#.  
This bit controls whether the CPU[1] output  
buffer is free-running or stoppable. If it is set  
to stoppable the CPU[1] output buffer will be  
disabled with the assertion of CPU_STP#.  
CPU0 Stop  
Enable  
2
1
RW  
RW  
Free Running  
Free Running  
Stoppable  
Stoppable  
0
0
CPU1 Stop  
Enable  
This bit controls whether the CPU[2] output  
buffer is free-running or stoppable. If it is set  
to stoppable the CPU[2] output buffer will be  
disabled with the assertion of CPU_STP#.  
CPU2 Stop  
Enable  
0
RW  
Free Running  
Stoppable  
0
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
11  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
4
CPU PLL M/N Register  
Name  
Control Function  
N Divider Prog bit 8  
N Divider Prog bit 9  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
CPU N Div8  
CPU N Div9  
CPU M Div5  
CPU M Div4  
CPU M Div3  
CPU M Div2  
CPU M Div1  
CPU M Div0  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 4 and 5 will  
configure the CPU VCO  
frequency. Default at power up  
= latch-in. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
M Divider Programming  
bit (5:0)  
[MDiv(5:0)]  
Bit 0  
Byte  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
5
CPU PLL M/N Register  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
CPU N Div7  
CPU N Div6  
CPU N Div5  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 4 and 5 will  
configure the CPU VCO  
frequency. Default at power up  
= latch-in. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
N Divider Programming Byte5 bit(7:0) and  
Byte5 bit(7:6)  
CPU N Div4  
CPU N Div3  
CPU N Div2  
CPU N Div1  
CPU N Div0  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
[MDiv(5:0)]  
Bit 0  
Byte  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
6
DOT96 PLL M/N Register  
Name  
Control Function  
N Divider Prog bit 8  
N Divider Prog bit 9  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DOT N Div8  
DOT N Div9  
DOT M Div5  
DOT M Div4  
DOT M Div3  
DOT M Div2  
DOT M Div1  
DOT M Div0  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 6 and 7 will  
configure the DOT VCO  
frequency. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
M Divider Programming  
bit (5:0)  
[MDiv(5:0)]  
Bit 0  
Byte  
Bit(s) Pin #  
Bit 7  
7
DOT96 PLL M/N Register  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DOT N Div7  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 6 and 7 will  
configure the DOT VCO  
frequency. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
DOT N Div6  
Bit 6  
DOT N Div5  
Bit 5  
N Divider Programming Byte7 bit(7:0) and  
Byte6 bit(7:6)  
DOT N Div4  
DOT N Div3  
DOT N Div2  
DOT N Div1  
DOT N Div0  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
[MDiv(5:0)]  
Bit 0  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
12  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
8
LCD100 PLL M/N Register  
Name  
Control Function  
N Divider Prog bit 8  
N Divider Prog bit 9  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
LCD100 N Div8  
LCD100 N Div9  
LCD100 M Div5  
LCD100 M Div4  
LCD100 M Div3  
LCD100 M Div2  
LCD100 M Div1  
LCD100 M Div0  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 8 and 9 will  
configure the DOT VCO  
frequency. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
M Divider Programming  
bit (5:0)  
[MDiv(5:0)]  
Bit 0  
Byte  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
9
LCD100 PLL M/N Register  
Name  
LCD100 N Div7  
LCD100 N Div6  
LCD100 N Div5  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
X
X
X
X
X
X
X
X
The decimal representation of M  
and N Divider in Byte 8 and 9 will  
configure the DOT VCO  
frequency. VCO Frequency =  
14.318 x [NDiv(11:0)] /  
N Divider Programming Byte9 bit(7:0) and  
Byte8 bit(7:6)  
LCD100 N Div4  
LCD100 N Div3  
LCD100 N Div2  
LCD100 N Div1  
LCD100 N Div0  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
[MDiv(5:0)]  
Bit 0  
Byte  
10 Status Readback Register  
Bit(s) Pin #  
Name  
FSB  
FSC  
Description  
Frequency Select B  
Frequency Select C  
Type  
R
R
R
R
0
1
Default  
Latch  
Latch  
7
6
5
4
3
2
1
0
37  
9
24  
28  
36  
See Table 1: CPU Frequency  
Select Table  
CR0# is Low  
CR1# is Low  
CR2# is Low  
CR0# Readbk  
CR1# Readbk  
CR2# Readbk  
Reserved  
Reserved  
Reserved  
Real time CR0# State Indicator  
Real time CR1# State Indicator  
Real time CR2# State Indicator  
CR0# is High  
CR1# is High  
CR2# is High  
X
X
X
0
0
0
R
Byte  
11 Revision ID/Vendor ID Register  
Bit(s) Pin #  
Name  
Description  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
7
6
5
4
3
2
1
0
Rev Code Bit 3  
Rev Code Bit 2  
Rev Code Bit 1  
Rev Code Bit 0  
Vendor ID bit 3  
Vendor ID bit 2  
Vendor ID bit 1  
Vendor ID bit 0  
X
X
X
X
0
0
0
1
Revision ID  
Vendor specific  
Vendor ID  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
13  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
12 Device ID Register  
Bit(s) Pin #  
Name  
Description  
Device ID MSB  
Device ID 2  
Device ID 1  
Device ID LSB  
Type  
R
R
R
R
0
0
0
0
1
1
1
1
Default  
7
6
5
4
3
2
1
0
DEV_ID3  
DEV_ID2  
DEV_ID1  
DEV_ID0  
Reserved  
Reserved  
Reserved  
Reserved  
1
0
1
0
0
0
0
0
Byte  
13 Reserved Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Control Function  
Control Function  
Type  
Type  
Type  
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Byte  
14 Reserved Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
0
0
0
0
Byte  
15 Byte Count Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Reserved  
BC6  
Default  
0
0
0
0
1
1
1
1
Byte Count 6 (MSB)  
Byte Count 5  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
BC5  
BC4  
BC3  
BC2  
BC1  
BC0  
Specifies Number of bytes to be  
read back during an SMBus  
read.  
Byte Count 4  
Byte Count 3  
Byte Count 2  
Byte Count 1  
Default is 0xF.  
Byte Count LSB  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
14  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
16 M/N Enable Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Enables PLL MN programming  
Type  
RW  
0
1
Default  
MN Enable  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
MN Disabled  
MN Enabled  
0
0
0
0
0
0
0
0
Byte  
17 CPU PLL Spread Spectrum Index Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
CPUSSP7  
CPUSSP6  
CPUSSP5  
CPUSSP4  
CPUSSP3  
CPUSSP2  
CPUSSP1  
CPUSSP0  
X
X
X
X
X
X
X
X
These Spread Spectrum bits in  
Byte 17 and 18 will program the  
spread percentage of the CPU  
and SRC outputs  
Spread Spectrum Programming bit(7:0)  
Contact IDT before editing these values.  
Byte  
18 CPU PLL Spread Spectrum Index Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
CPUSSP15  
CPUSSP14  
CPUSSP13  
CPUSSP12  
CPUSSP11  
CPUSSP10  
CPUSSP9  
CPUSSP8  
X
X
X
X
X
X
X
X
These Spread Spectrum bits in  
Byte 17 and 18 will program the  
spread percentage of the CPU  
and SRC outputs  
Spread Spectrum Programming bit(15:8)  
Contact IDT before editing these values.  
Byte  
19 LCD100 PLL Spread Spectrum Index Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
LCDSSP7  
LCDSSP6  
LCDSSP5  
LCDSSP4  
LCDSSP3  
LCDSSP2  
LCDSSP1  
LCDSSP0  
X
X
X
X
X
X
X
X
These Spread Spectrum bits in  
Byte 19 and 20 will program the  
spread percentage of the CPU  
and SRC outputs  
Spread Spectrum Programming bit(7:0)  
Contact IDT before editing these values.  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
15  
ICS9UMS9610  
PC MAIN CLOCK  
Byte  
20 LCD100 PLL Spread Spectrum Index Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
LCDSSP15  
LCDSSP14  
LCDSSP13  
LCDSSP12  
LCDSSP11  
LCDSSP10  
LCDSSP9  
LCDSSP8  
X
X
X
X
X
X
X
X
These Spread Spectrum bits in  
Byte 19 and 20 will program the  
spread percentage of the CPU  
and SRC outputs  
Spread Spectrum Programming bit(15:8)  
Contact IDT before editing these values.  
Byte  
21 CPU PLL M/N Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
CPU NDIV 10  
CPU NDIV 11  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Control Function  
N Divider Prog bit 10  
N Divider Prog bit 11  
Type  
RW  
RW  
0
1
Default  
X
X
0
0
0
0
0
0
See Byte 4/5 Description  
Byte  
22 LCD100 PLL M/N Register  
Bit(s) Pin #  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Name  
LCD NDIV 10  
LCD NDIV 11  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Control Function  
N Divider Prog bit 10  
N Divider Prog bit 11  
Type  
RW  
RW  
0
1
Default  
X
X
0
0
0
0
0
0
See Byte 8/9 Description  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
16  
ICS9UMS9610  
PC MAIN CLOCK  
Test Clarification Table  
Comments  
HW  
TEST_SEL TEST_MODE  
HW PIN  
HW PIN  
OUTPUT  
<0.35V  
X
NORMAL  
Power-up w/ TEST_SEL = 1 to enter test mode  
Cycle power to disable test mode  
TEST_MODE -->low Vth input  
>0.7V  
>0.7V  
<0.35V  
>0.7V  
HI-Z  
REF/N  
TEST_MODE is a real time input  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
17  
ICS9UMS9610  
PC MAIN CLOCK  
MLF Top Mark Information (9UMS9610)  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
3
4
5
6
7
8
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
ICS  
UMS9610yL  
YYWW  
9
C of O  
10  
11  
12  
#######  
13 14 15 16 17 18 19 20 21 22 23 24  
Line 1. Company name  
Line 2. Part Number  
Line 3.YYWW = Date Code  
Line 3. Country of Origin  
Line 4. ####### = Lot Number  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
18  
ICS9UMS9610  
PC MAIN CLOCK  
(Ref.)  
ND & N  
Even  
Seating Plane  
Anvil  
(ND -1)x e  
(Ref.)  
A1  
Index Area  
L
A3  
E2  
N
N
(Typ.)  
e
2
If ND & N  
are Even  
1
2
Singulation  
(N -1)x  
e
OR  
(Ref.)  
E2  
2
Sawn  
Singulation  
Top View  
D
b
e
Thermal  
Base  
(Re f.)  
D2  
2
A
&
ND  
Odd  
N
D2  
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
C
0. 08  
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH  
QUAD FLAT / NO LEAD PLASTIC PACKAGE  
DIMENSIONS  
DIMENSIONS  
48L  
SYMBOL  
MIN.  
0.8  
0
MAX.  
1.0  
0.05  
SYMBOL  
N
TOLERANCE  
48  
A
A1  
A3  
b
ND  
12  
0.20 Reference  
0.18  
0.40 BASIC  
NE  
12  
0.3  
D x E BASIC  
D2 MIN. / MAX.  
E2 MIN. / MAX.  
L MIN. / MAX.  
6.00 x 6.00  
3.95 / 4.25  
3.95 / 4.25  
0.30 / 0.50  
e
Ordering Information  
Part / Order Number  
9UMS9610CKLF  
9UMS9610CKLFT  
Marking  
Shipping Packaging  
Tubes  
Package  
48-pin MLF  
48-pin MLF  
Temperature  
0 to +85° C  
0 to +85° C  
see page 18  
Tape and Reel  
Parts that are ordered w ith a "LF" suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant.  
IDTTM/ICSTM PC MAIN CLOCK  
1336—06/01/09  
19  
ICS9UMS9610  
PC MAIN CLOCK  
Revision History  
Rev.  
0.1  
Issue Date Description  
Page #  
04/25/07 Initial Release  
-
1
-
0.15  
0.2  
0.3  
0.4  
0.5  
05/03/07 Corrected CLKPWRGD#/PD polarity  
5/18/2007 Updated Test Clarification Table with the correct voltage levels.  
8/31/2007 Updated Input Pin names to indicate maximum Input voltage level  
9/11/2007 Added Logic Level and Input Level Tolerance Columns to Pin Descriptions.  
9/13/2007 Clarified that X1 is 1.5V only input  
-
2, 3  
2
1. Byte Count in Byte 15 is 7 bits, not 8 bits. B15b7 is now reserved.  
2. Modified PLL programming formulas in Bytes(4:9). N is 12 bits instead of 10 bits.  
3. Changed REF_3.3 output name to reflect default drive strength (new name is  
10/23/007 REF_3.3_2x).  
11/6/2007 Updated Bytes [9:4].  
11/29/2007 Added Bytes 16-22 to the SMBUS.  
2/26/2008 Added MLF Top Mark Information.  
7/8/2008 Updated Electrical Specifications  
7/21/2008 Updated Electrical Specifications  
5/21/2009 Moved to final.  
0.6  
0.7  
0.8  
0.9  
0.91  
0.92  
A
Various  
12-13  
15-16  
18  
5-7  
5-7  
-
B
6/1/2009 Updated electrical specs; TA spec in ordering information.  
Various  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
800-345-7015  
408-284-6578  
408-284-8200  
pcclockhelp@idt.com  
Fax: 408-284-2775  
Corporate Headquarters  
Asia Pacific and Japan  
Europe  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
United States  
800 345 7015  
Integrated Device Technology  
Singapore (1997) Pte. Ltd.  
Reg. No. 199707558G  
435 Orchard Road  
#20-03 Wisma Atria  
Singapore 238877  
IDT Europe, Limited  
Prime House  
Barnett Wood Lane  
Leatherhead, Surrey  
United Kingdom KT22 7DE  
+44 1372 363 339  
+408 284 8200 (outside U.S.)  
+65 6 887 5505  
TM  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks  
or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
20  
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