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6T39007ANLGI

型号：

6T39007ANLGI

描述：

时钟分配电路。[ CLOCK DISTRIBUTION CIRCUIT ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

279 K

下载PDF手册
DATASHEET  
CLOCK DISTRIBUTION CIRCUIT  
IDT6T39007A  
Description  
Features  
• Packaged in 24-pin QFN  
• TCXO sine wave input  
• +2.5 V operating voltage  
• Four buffered LVDS outputs  
The IDT6T39007A is a low-power, four output clock  
distribution circuit. The device takes a TCXO or 1.8 V to  
2.5 V LVCMOS input and generates four high-quality LVDS  
outputs, and two programmable divided outputs.  
It includes a redundant input with automatic glitch-free  
switching when the primary reference is removed. The  
primary input may be selected by the user by pulling the  
SEL pin low or high. If the primary input is removed and  
brought back, it will not be re-selected until 1024 cycles  
have passed.  
• Two programmable outputs for power control up to 3.0 V  
LVCMOS levels based on VDDO1/VDDO2  
2
• Individual output enables controlled via I C or OEx  
• Pb-free, RoHS compliant package  
• Industrial temperature range (-40°C to +85°C)  
The IDT6T39007A specifically addresses the needs of  
handheld applications in both performance and package  
size. The device is packaged in a small 4mm x 4mm 24-pin  
QFN, allowing optimal use for limited board space.  
Block Diagram  
VDD 2.5 V  
3
OE1  
SEL  
SCLK  
OUT1 LVDS  
OE2  
OUT2 LVDS  
SDATA  
OUT3 LVDS  
OUT4 LVDS  
LVCMOS_INB  
TCXO_INA  
±100mVpp  
VDDO1  
PWRCTRL_CLK1  
Divide  
Logic  
MUX  
VDDO2  
PWRCTRL_CLK2  
2
GND  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
1
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Pin Assignment  
SEL Pin Configuration Table  
SEL  
Primary Input  
LVCMOS_INB  
TCXO_INA  
0
1
OE Pin Configuration Table  
19  
1
OUT1  
OUT1B  
OUT2  
PWRCTRL_CLK1  
OEx  
OUTx LVDS  
Disabled  
Thermal pad  
connected to silicon  
substrate.  
PWRCTRL_CLK2  
SCLK  
0
1
OUT2B  
SDATA  
Connect to ground  
plane.  
Enabled  
VDDO2  
VDD  
OUT3  
13  
OUT3B  
7
24- pin QFN  
Pin Descriptions  
Pin  
Pin  
Pin  
Pin Description  
Number  
Name  
Type  
1
2
PWRCTRL_CLK1 Output Programmable power control output 1. See I2C table.  
PWRCTRL_CLK2 Output Programmable power control output 2. See I2C table.  
3
SCLK  
SDATA  
VDDO2  
VDD  
Input  
Input  
I2C clock input.  
I2C data input.  
4
5
Power Connect to +3.0 V.  
6
Power Connect to +2.5 V.  
7
GND  
Power Connect to ground.  
8
VDD  
Power Connect to +2.5 V.  
9
OUT4B  
OUT4  
OE2  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Output Buffered LVDS output. Outputs tri-state when disabled.  
10  
11  
12  
13  
14  
15  
Output enable control for OUT2 LVDSpins. Internal pull-up resistor. See table above.  
Output enable control for OUT1 LVDSpins. Internal pull-up resistor. See table above.  
Input  
Input  
OE1  
OUT3B  
OUT3  
OUT2B  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Output Buffered LVDS output. Outputs tri-state when disabled.  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
2
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Pin  
Pin  
Pin  
Pin Description  
Number  
Name  
Type  
16  
17  
18  
19  
20  
21  
22  
23  
24  
OUT2  
OUT1B  
OUT1  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Output Buffered LVDS output. Outputs tri-state when disabled.  
Power Connect to ground.  
GND  
VDD  
Power Connect to +2.5 V.  
LVCMOS_INB  
SEL  
Input  
Input  
Input  
Connect to primary LVCMOS input INB. See table above.  
Select pin for primary inputs. See table above. Internal pull-up resistor.  
Connect to TCXO input.  
TCXO_INA  
VDDO1  
Power Connect to +3.0 V.  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
3
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
General I2C Serial Interface  
How to Write:  
How to Read:  
• Controller (host) sends a start bit  
• Controller (host) sends the write address D4(H)  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location =N  
• IDT clock will acknowledge  
• Controller (host) sends a start bit  
• Controller (host) sends the write address D4(H)  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address D5(H)  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location =N  
• IDT clock will acknowledge  
• Controller (host) sends the data byte count = X  
• IDT clock will acknowledge  
• Controller (host) sends the data byte count = X  
• IDT clock sends Byte N + X - 1  
• Controller (host) starts sending Byte N through Byte N + X - 1  
(see Note 2)  
• IDT clock sends Byte 0 through byte X (if X(H) was written to  
byte 8)  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Controller (Host)  
starTbit  
IDT (Slave/Receiver)  
Index Block Write Operation  
T
Controller (Host)  
starTbit  
Slave Address D4(H)  
WR WRite  
IDT (Slave/Receiver)  
Slave Address D4(H)  
T
WR  
WRite  
ACK  
ACK  
Beginning Byte = N  
Repeat starT  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte = N  
RT  
Slave Address D5(H)  
RD  
ReaD  
ACK  
.
Data Byte Count = X  
Beginning Byte N  
X
B
Y
T
E
O
O
O
ACK  
ACK  
O
O
O
.
X
B
Y
T
E
O
O
O
Byte N + X - 1  
O
O
O
ACK  
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
4
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
I2C Address  
The IDT6T39007A is a slave-only device that supports block read and block write protocol using a single 7 bit address and  
read/write bit. A block write (D4 ) or block read (D5 ) is made up of seven (7) bits and one (1) read/write bit.  
(H)  
(H)  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W#  
1
1
0
1
0
1
0
X
In applications where the indexed block write and block read  
are used, the dummy byte (bit 11-18) functions as a  
register-offset (8 bits) pointer.  
Byte 0: Control Register  
Bit  
Description  
Type  
Power Up  
Condition  
Undefined  
Output(s) Affected  
Notes  
7
Reserved  
R
Not applicable  
6
5
4
3
2
1
0
Reserved  
OE for OUT3  
OE for OUT4  
Reserved  
R
RW  
RW  
R
Undefined  
1
Not applicable  
1=enabled  
0=disabled  
LVDS clock output  
LVDS clock output  
Not applicable  
1
1=enabled  
0=disabled  
Undefined  
Undefined  
Undefined  
Undefined  
Reserved  
R
Not applicable  
Reserved  
R
Not applicable  
Reserved  
R
Not applicable  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
5
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Byte 1: Control Register  
Bit  
Description  
Type  
Power Up  
Condition  
Output(s) Affected  
Notes  
7
PWRCTRL_CLK1 Divider SEL bit 7  
RW  
0
0
0
0
1
1
1
1
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
6
5
4
3
2
1
0
PWRCTRL_CLK1 Divider SEL bit 6  
PWRCTRL_CLK1 Divider SEL bit 5  
PWRCTRL_CLK1 Divider SEL bit 4  
PWRCTRL_CLK1 Divider SEL bit 3  
PWRCTRL_CLK1 Divider SEL bit 2  
PWRCTRL_CLK1 Divider SEL bit 1  
PWRCTRL_CLK1 Divider SEL bit 0  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Default is /15 to  
get 866.666 kHz  
from 13 MHz  
Byte 2: Control Register  
Bit  
Description  
Type  
Power Up  
Condition  
Output(s) Affected  
Notes  
7
PWRCTRL_CLK2 Divider SEL bit 7  
RW  
0
0
1
0
1
PWRCTRL_CLK2  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
6
5
4
3
PWRCTRL_CLK2 Divider SEL bit 6  
PWRCTRL_CLK2 Divider SEL bit 5  
PWRCTRL_CLK2 Divider SEL bit 4  
PWRCTRL_CLK2 Divider SEL bit 3  
RW  
RW  
RW  
RW  
PWRCTRL_CLK2  
PWRCTRL_CLK2  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
6
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
2
1
0
PWRCTRL_CLK2 Divider SEL bit 2  
RW  
RW  
RW  
1
1
0
PWRCTRL_CLK1  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
PWRCTRL_CLK2 Divider SEL bit 1  
PWRCTRL_CLK2 Divider SEL bit 0  
PWRCTRL_CLK1  
PWRCTRL_CLK1  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
Default is /46 to  
get 282.6kHz  
from 13 MHz  
Byte 3: Control Register  
Bit  
Description  
Type  
Power Up  
Output(s) Affected  
Notes  
Condition  
7 to 0  
Reserved  
R
Undefined  
Not applicable  
Byte 4 through 5: Control Register  
Bit  
Description  
Type  
Power Up  
Condition  
Undefined  
Output(s) Affected  
Notes  
7 to 0  
Reserved  
R
Not applicable  
Byte 6: Control Register  
Bit  
7
Description  
Revision ID bit 3  
Revision ID bit 2  
Revision ID bit 1  
Revision ID bit 0  
Vendor ID bit 3  
Vendor ID bit 2  
Vendor ID bit 1  
Vendor ID bit 0  
Type  
R
Power Up  
Output(s) Affected  
Not applicable  
Not applicable  
Not applicable  
Not applicable  
Not applicable  
Not applicable  
Not applicable  
Not applicable  
Notes  
0
0
0
0
0
0
0
1
6
R
5
R
4
R
3
R
2
R
1
R
0
R
IDT™ CLOCK DISTRIBUTION CIRCUIT  
7
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Applications Information  
External Components  
A minimum number of external components are required for  
proper operation.  
Decoupling Capacitors  
Decoupling capacitors of 0.01 µF should be connected  
between VDD and GND as close to the device as possible.  
Do not share ground vias between components. Route  
power from power source through the capacitor pad and  
then into IDT pin.  
PCB Layout Recommendations  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
2. No vias should be used between decoupling capacitor  
and VDD pin.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the IDT6T39007A.This includes signal  
traces just underneath the device, or on layers adjacent to  
the ground plane layer used by the device.  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
8
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT6T39007A. These ratings, which  
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at  
these or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical  
parameters are guaranteed only over the recommended operating temperature range.  
Item  
Rating  
Max Supply Voltage, VDD  
5 V  
LVCMOS_INB, SCLK and SDATA Inputs  
All Other Inputs and Outputs  
Ambient Operating Temperature  
Storage Temperature  
-0.5 V to +3.3 V  
-0.5 V to VDD+0.5 V  
-40 to +85° C  
-65 to +150° C  
125°C  
Junction Temperature  
Peak Soldering Temperature  
260°C  
Recommended Operation Conditions  
Parameter  
Min.  
Typ.  
Max.  
+85  
Units  
° C  
V
Ambient Operating Temperature  
Power Supply Voltage (measured in respect to GND)  
Output Supply Voltage (VDDO1, VDDO2)  
-40  
+2.25  
VDD  
+2.5  
+3.0  
+2.75  
+3.15  
V
DC Electrical Characteristics  
Unless otherwise specified, VDD =2.5 V 10ꢀ, VDDO1 = VDDO2 = 3.0 V 5ꢀ, Ambient Temp. -40 to +85° C  
Parameter  
Operating Supply Voltage  
Output Supply Voltage  
Input High Voltage  
Symbol  
Conditions  
Min.  
+2.25  
Typ.  
+2.5  
3.0  
Max.  
+2.75  
3.15  
Units  
VDD  
V
V
V
VDDO VDDO1, VDDO2  
VDD  
V
SEL, OEx, LVCMOS_INB  
SCLK and SDATA  
0.75xVDD  
0.7xVDD  
IH  
Input Low Voltage  
V
SEL, OEx, LVCMOS_INB  
SCLK and SDATA  
0.35xVDD  
0.3xVDD  
V
IL  
High-Level Output Voltage  
Low-Level Output Voltage  
Operating Supply Current  
V
I
I
= -4 mA  
= 4 mA  
1.7  
V
V
OH  
OH  
OL  
V
0.7  
18  
OL  
IDD  
No load, all outputs  
switching at 13 MHz  
15  
mA  
All outputs disabled  
Single-ended clocks  
TBD  
70  
mA  
mA  
Short Circuit Current  
I
OS  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
9
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Parameter  
Output Impedance  
Symbol  
Conditions  
All clock outputs, OEx=1  
SEL, OEx  
Min.  
Typ.  
15  
Max.  
Units  
Ω
Z
O
Internal Pull-Up Resistance  
Input Capacitance  
R
500  
6
kΩ  
pu  
C
All input pins  
pF  
IN  
AC Electrical Characteristics - Single-Ended Outputs  
Unless otherwise stated, VDD =2.5 V 10ꢀ, VDDO1 = VDDO2 = 3.0 V 5ꢀ, Ambient Temp. -40 to +85° C  
Parameter  
Symbol  
Conditions  
Min.  
Typ.  
Max. Units  
Input Frequency  
F
12.6  
13  
13.4  
0.4  
MHz  
MHz  
IN  
Variance Input Frequencies  
LVCMOS_INB, TCXO_INA,  
Note 2  
Time Switch Clock Inputs  
LVCMOS_INB, TCXO_INA,  
Note 3  
80  
µs  
TCXO Input Swing  
Output Frequency Error  
Output Rise Time  
TCXO_INA  
100  
45  
900  
mV  
ppm  
ns  
0
1
t
20% to 80%, Note 1  
1.5  
1.5  
55  
1
OR  
Output Fall Time  
t
80% to 20%, Note 1  
1
ns  
OF  
Output Clock Duty Cycle  
Output Enable time  
Measured at VDDO/2, Note 1  
50  
%
OE goes high, output within  
1% of final frequency  
ms  
Clock Stabilization Time from  
Power Up  
Power up, output within 1% of  
final frequency  
3
10  
ms  
Note 1: CL = 8 pF.  
Note 2: Delta from 13 MHz.  
Note 3: By removing primary input and then bringing back primary input.  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
10  
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
AC Electrical Characteristics - LVDS Outputs  
Unless otherwise stated, VDD = 2.5 V 10ꢀ, Ambient Temperature -40 to +85° C  
Parameter  
Conditions  
Min. Typ. Max.  
Units  
mV  
Differential Output Voltages | V  
|
R = 100Ω  
250  
-40  
350  
0
450  
40  
OD  
L
∆ V  
V
Magnitude  
Change  
mV  
OD  
OD  
Offset Voltage (V  
)
1.125  
45  
1.25  
50  
3
1.375  
55  
V
%
OS  
Output CLock Duty Cycle  
Measured at V  
OS  
∆ V  
V
Magnitude  
25  
mV  
OS  
OS  
Change  
Output Short Circuit Current (I  
Output Rise Time  
)
-10  
0.5  
mA  
ns  
OS  
20% to 80%,  
1.0  
1.0  
R = 100Ω  
L
Output Fall Time  
20% to 80%,  
0.5  
ns  
R = 100Ω  
L
IDT™ CLOCK DISTRIBUTION CIRCUIT  
11  
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Parameter Measurement Information  
VDD = 2.5V±5%  
SCOPE  
Z = 50  
Qx  
80%  
VOD  
80%  
50  
LVDS  
Z = 50  
nQx  
20%  
20%  
Clock  
Outputs  
50  
tOR  
tOF  
2.5V OUTPUT LOAD AC TEST CIRCUIT  
OUTPUT RISE/FALL TIME  
nCLK  
VDD  
CLK  
out  
out  
Pulse Width  
DC Input  
LVDS  
100  
VOD  
/
VOD  
tPERIOD  
tPW & tPERIOD  
VOD SETUP  
nCLK  
CLK  
VOH  
VOL  
VDD  
t(φ)  
out  
out  
50  
50  
DC Input  
LVDS  
tjit(φ) = t(φ) - t(φ)mean = Phase Jitter  
VOS/ VOS  
PHASE JITTER  
VOS SETUP  
VDD  
nCLK  
Cross Points  
VOS  
VOD  
CLK  
GND  
DIFFERENTIAL INPUT LEVEL  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
12  
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Marking Diagram  
TBD  
Notes:  
1. “Z” is the device step (1 to 2 characters).  
2. YYWW is the last two digits of the year and week that the part was assembled.  
3. “$” is the assembly mark code.  
4. “G” after the two-letter package code designates RoHS compliant package.  
5. “I” at the end of part number indicates industrial temperature range.  
6. Bottom marking: country of origin if not USA.  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
θ
Still air  
29.1  
22.8  
21.0  
41.8  
° C/W  
° C/W  
° C/W  
° C/W  
JA  
θ
1 m/s air flow  
JA  
θ
2.5 m/s air flow  
JA  
Thermal Resistance Junction to Case  
θ
JC  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
13  
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Package Outline and Package Dimensions (24-pin QFN)  
Package dimensions are kept current with JEDEC Publication No. 95  
(Ref)  
Seating Plane  
(ND-1)x  
(Ref)  
e
ND & NE  
Even  
A1  
Index Area  
(Typ)  
If ND & NE  
are Even  
L
A3  
e
2
N
1
2
N
1
2
(NE-1)x  
(Ref)  
e
Sawn  
Singulation  
E2  
E
E2  
2
Top View  
b
A
C
(Ref)  
ND & NE  
Odd  
e
Thermal Base  
D
D2  
2
C
D2  
0.08  
Millimeters  
Max  
1.00  
0.05  
0.25 Reference  
Symbol  
Min  
0.80  
0
A
A1  
A3  
b
0.18  
0.30  
e
0.50 BASIC  
N
24  
N
N
6
6
D
E
D x E BASIC  
4.00 x 4.00  
D2  
E2  
L
2.3  
2.3  
0.30  
2.55  
2.55  
0.50  
Ordering Information  
Part / Order Number  
6T39007ANLGI  
Marking  
Shipping Packaging  
Tubes  
Package  
24-pin QFN  
24-pin QFN  
Temperature  
-40 to +85° C  
-40 to +85° C  
TBD  
6T39007ANLGI8  
Tape and Reel  
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT™ CLOCK DISTRIBUTION CIRCUIT  
14  
IDT6T39007A REV G 111009  
IDT6T39007A  
CLOCK DISTRIBUTION CIRCUIT  
DISTRIBUTION CIRCUITS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device  
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered  
trademarks used to identify products or services of their respective owners.  
Printed in USA  
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IDT

 		6T39007ANLGI8 时钟分配电路。[ CLOCK DISTRIBUTION CIRCUIT ] 15 页

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