IDT5V50017
LOW EMI CLOCK GENERATOR
SSCG
Spread Spectrum Profile
External Components
The IDT5V50017 low EMI clock generator uses an
The IDT5V50017 requires a minimum number of external
components for proper operation.
optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3, as close to these
pins as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Modulation Rate
Series Termination Resistor
When the PCB trace between the clock output and the load
is over 1 inch, series termination should be used. To series
terminate a 50Ωtrace (a commonly used trace impedance)
place a 33Ωresistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω.
Time
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5V50017. This includes signal traces just underneath
the device, or on layers adjacent to the ground plane layer
used by the device.
IDT™ LOW EMI CLOCK GENERATOR
3
IDT5V50017 REV D 040709
