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5P90005DCGI

型号：

5P90005DCGI

描述：

串行实时时钟[ SERIAL REAL-TIME CLOCK ]

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

298 K

下载PDF手册
PRELIMINARY DATASHEET  
SERIAL REAL-TIME CLOCK  
Description  
IDT5P90005  
Features  
The IDT5P90005 is a serial real-time clock (RTC) device  
that consumes ultra-low power and provides a full  
binary-coded decimal (BCD) clock/calendar. The  
• Packaged in 8-pin SOIC  
• Counters for seconds, minutes, hours, days, date,  
months, years, and century  
clock/calendar provides seconds, minutes, hours, day,  
date, month, and year information. The clock operates in  
either the 24-hour or 12-hour format with AM/PM indicator.  
The end of the month date is automatically adjusted for  
months with fewer than 31 days, including corrections for  
leap year. Access to the clock/calendar registers is  
provided by an I C interface capable of operating in fast I C  
mode. Built-in Power-sense circuitry detects power failures  
and automatically switches to the backup supply,  
maintaining time and date operation.  
• 32 kHz crystal oscillator integrating load capacitance  
(12.5 pF) providing exceptional oscillator stability and  
high crystal series resistance operation  
• Serial interface supports I2C bus (100 or 400 kHz  
protocol)  
2
2
• Ultra low battery supply current of 0.8 µA (typ at 3 V)  
• 2.0 to 5.5 V clock operating voltage  
• Automatic switch over and deselect circuitry  
• Automatic leap year compensation  
• Operating temperature of -40 to +85°C  
Block Diagram  
1 Hz  
32.768 kHz  
Oscillator and  
Divider  
OSCI  
MUX/  
FT/OUT  
Buffer  
OSCO  
VCC  
GND  
VBAT  
Power  
Control  
Control  
Logic  
Clock, Calendar  
Counter  
SCL  
SDA  
I2C  
Interface  
1 Byte 7 Bytes  
Control  
Buffer  
IDT™ SERIAL REAL-TIME CLOCK  
1
IDT5P90005  
REV E 031209  
IDT5P90005  
SERIAL REAL-TIME CLOCK  
RTC  
Pin Assignment  
8
7
6
5
1
2
3
4
VCC  
OSCI  
OSCO  
VBAT  
FT/OUT  
SCL  
VSS  
SDA  
8-Pin (150 mil) SOIC  
Pin Descriptions  
Pin  
Number  
Pin  
Pin  
Type  
Pin Description  
Name  
OSCI  
OSCO  
VBAT  
1
2
3
4
5
6
7
8
Input  
Oscillator input.  
Output Oscillator output.  
Power  
Power  
I/O  
Battery supply voltage.  
VSS  
Connect to ground.  
SDA  
Serial data address input/output.  
Serial clock.  
SCL  
Input  
FT/OUT  
VCC  
Output Frequency test/output driver (open drain).  
Power Supply voltage.  
IDT™ SERIAL REAL-TIME CLOCK  
2
IDT5P90005  
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SERIAL REAL-TIME CLOCK  
RTC  
Device Operation  
The IDT5P90005 clock operates as a slave device on the  
serial bus. Access is obtained by implementing a start  
condition followed by the correct slave address (D0h). The  
8 bytes contained in the device can then be accessed  
sequentially in the following order:  
1st byte: seconds register  
2nd byte: minutes register  
3rd byte: century/hours register  
4th byte: day register  
5th byte: date register  
6th byte: month register  
7th byte: years register  
8th byte: control register  
The IDT5P90005 clock continually monitors VCC for an  
out-of-tolerance condition. Should VCC fall below VSO, the  
device terminates an access in progress and resets the  
device address counter. Inputs to the device will not be  
recognized at this time, to prevent erroneous data from  
being written to the device from an out-of-tolerance system.  
When VCC falls below VSO, the device automatically  
switches over to the battery and powers down into an ultra  
low current mode of operation to conserve battery life. Upon  
power-up, the device switches from battery to VCC at VSO  
and recognizes inputs.  
IDT™ SERIAL REAL-TIME CLOCK  
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RTC  
2
information is transferred byte-wise and each receiver  
acknowledges with a ninth bit.  
I C Serial Data Bus  
2
The IDT5P90005 supports the I C bus protocol. A device  
that sends data onto the bus is defined as a transmitter and  
a device receiving data as a receiver. The device that  
controls the message is called a master. The devices that  
are controlled by the master are referred to as slaves. The  
bus must be controlled by a master device that generates  
the serial clock (SCL), controls the bus access, and  
generates the START and STOP conditions. The  
Acknowledge: Each receiving device, when addressed, is  
obliged to generate an acknowledge after the reception of  
each byte. The master device must generate an extra clock  
pulse that is associated with this acknowledge bit.  
A device that acknowledges must pull down the SDA line  
during the acknowledge clock pulse in such a way that the  
SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse. Of course, setup and hold  
times must be taken into account. A master must signal an  
end of data to the slave by not generating an acknowledge  
bit on the last byte that has been clocked out of the slave. In  
this case, the slave must leave the data line HIGH to enable  
the master to generate the STOP condition.  
2
IDT5P90005 operates as a slave on the I C bus. Within the  
bus specifications, a standard mode (100 kHz maximum  
clock rate) and a fast mode (400 kHz maximum clock rate)  
are defined. The IDT5P90005 works in both modes.  
Connections to the bus are made via the open-drain I/O  
lines SDA and SCL.  
The following bus protocol has been defined (see the “Data  
Transfer on I C Serial Bus” figure):  
2
• Data transfer may be initiated only when the bus is not  
busy.  
• During data transfer, the data line must remain stable  
whenever the clock line is HIGH. Changes in the data line  
while the clock line is HIGH are interpreted as control  
signals.  
Accordingly, the following bus conditions have been  
defined:  
Bus not busy: Both data and clock lines remain HIGH.  
Start data transfer: A change in the state of the data line,  
from HIGH to LOW, while the clock is HIGH, defines a  
START condition.  
Stop data transfer: A change in the state of the data line,  
from LOW to HIGH, while the clock line is HIGH, defines the  
STOP condition.  
Data valid: The state of the data line represents valid data  
when, after a START condition, the data line is stable for the  
duration of the HIGH period of the clock signal. The data on  
the line must be changed during the LOW period of the clock  
signal. There is one clock pulse per bit of data.  
Each data transfer is initiated with a START condition and  
terminated with a STOP condition. The number of data  
bytes transferred between START and STOP conditions is  
not limited, and is determined by the master device. The  
IDT™ SERIAL REAL-TIME CLOCK  
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2
Data Transfer on I C Serial Bus  
Depending upon the state of the R/W bit, two types of data  
transfer are possible:  
bit (see the “Data Write–Slave Receiver Mode” figure). The  
slave address byte is the first byte received after the START  
condition is generated by the master. The slave address  
byte contains the 7-bit IDT5P90005 address, which is  
1101000, followed by the direction bit (R/W), which is 0 for  
a write. After receiving and decoding the slave address byte  
the slave outputs an acknowledge on the SDA line. After the  
IDT5P90005 acknowledges the slave address + write bit,  
the master transmits a register address to the IDT5P90005.  
This sets the register pointer on the IDT5P90005, with the  
IDT5P90005 acknowledging the transfer. The master may  
then transmit zero or more bytes of data, with the  
IDT5P90005 acknowledging each byte received. The  
address pointer increments after each data byte is  
transferred. The master generates a STOP condition to  
terminate the data write.  
1) Data transfer from a master transmitter to a slave  
receiver. The first byte transmitted by the master is the  
slave address. Next follows a number of data bytes. The  
slave returns an acknowledge bit after each received byte.  
Data is transferred with the most significant bit (MSB) first.  
2) Data transfer from a slave transmitter to a master  
receiver. The first byte (the slave address) is transmitted by  
the master. The slave then returns an acknowledge bit. This  
is followed by the slave transmitting a number of data bytes.  
The master returns an acknowledge bit after all received  
bytes other than the last byte. At the end of the last received  
byte, a “not acknowledge” is returned. The master device  
generates all of the serial clock pulses and the START and  
STOP conditions. A transfer is ended with a STOP condition  
or with a repeated START condition. Since a repeated  
START condition is also the beginning of the next serial  
transfer, the bus is not released. Data is transferred with the  
most significant bit (MSB) first.  
2) Slave Transmitter Mode (Read Mode): The first byte is  
received and handled as in the slave receiver mode.  
However, in this mode, the direction bit indicates that the  
transfer direction is reversed. Serial data is transmitted on  
SDA by the IDT5P90005 while the serial clock is input on  
SCL. START and STOP conditions are recognized as the  
beginning and end of a serial transfer (see the “Data  
Read–Slave Transmitter Mode” figure). The slave address  
byte is the first byte received after the START condition is  
generated by the master. The slave address byte contains  
the 7-bit IDT5P90005 address, which is 1101000, followed  
by the direction bit (R/W), which is 1 for a read. After  
receiving and decoding the slave address byte the slave  
outputs an acknowledge on the SDA line. The IDT5P90005  
The IDT5P90005 can operate in the following two modes:  
1) Slave Receiver Mode (Write Mode): Serial data and  
clock are received through SDA and SCL. After each byte is  
received an acknowledge bit is transmitted. START and  
STOP conditions are recognized as the beginning and end  
of a serial transfer. Address recognition is performed by  
hardware after reception of the slave address and direction  
IDT™ SERIAL REAL-TIME CLOCK  
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then begins to transmit data starting with the register  
address pointed to by the register pointer. If the register  
pointer is not written to before the initiation of a read mode  
the first address that is read is the last one stored in the  
register pointer. The address pointer is incremented after  
each byte is transferred. The IDT5P90005 must receive a  
“not acknowledge” to end a read.  
Data Write – Slave Receiver Mode  
Data Read (from current Pointer location) – Slave Transmitter Mode  
Data Read (Write Pointer, then Read) – Slave Receive and Transmit  
IDT™ SERIAL REAL-TIME CLOCK  
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RTC  
Bus Timing Requirements Sequence  
Note: P=STOP and S=START.  
IDT™ SERIAL REAL-TIME CLOCK  
7
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RTC  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the IDT5P90005. These ratings, which  
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at  
these or any other conditions above those indicated in the operational sections of the specifications is not implied.  
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical  
parameters are guaranteed only over the recommended operating temperature range.  
Parameter  
Condition  
Min.  
-0.3  
-0.3  
-0.5  
-55  
Typ.  
Max.  
7
Units  
V
Supply Voltage, VCC  
Input or Output Voltages  
Clock Outputs  
Referenced to GND  
Referenced to GND  
Referenced to GND  
7
V
VDD+ 0.5  
125  
V
Storage Temperature  
C  
C  
mA  
C  
W
1
Soldering Temperature  
Max 10 seconds  
260  
Output Current  
20  
Ambient Operating Temperature  
Power Dissipation  
-40  
+85  
0.25  
Note 1: Re flow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30  
seconds).  
Caution: Negative undershoots below -0.3 V are not allowed on any pin while in the backup mode.  
IDT™ SERIAL REAL-TIME CLOCK  
8
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SERIAL REAL-TIME CLOCK  
RTC  
DC and AC Parameters  
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of  
the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under  
the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in  
their projects match the measurement conditions when using the quoted parameters.  
1
Operating and AC Measurement Conditions  
Parameter  
Rating  
2.0 to 5.5 V  
Supply Voltage, VCC  
Ambient Operating Temperature  
Load Capacitance  
-40 to +85ºC  
100 pF  
Input Rise and Fall times  
< 5 ns  
Input Pulse Voltages  
0.2 VCC to 0.8 VCC  
0.3 VCC to 0.7 VCC  
Input and Output TIming Reference Voltages  
Note 1: Output Hi-Z is defined as the point where data is no longer driven.  
AC Testing Input/Output Waveform  
Capacitance  
Parameter1,2  
Symbol  
Min.  
Typ.  
Max.  
7
Units  
pF  
Input Capacitance  
C
IN  
3
Output Capacitance (SDA, FT/OUT)  
C
10  
pF  
OUT  
Low-pass Filter Input Time Constant (SDA and SCL)  
t
250  
1000  
ns  
LP  
Note 1: Effective capacitance measured with power supply at 3.3 V; sampled only, not 100% tested.  
Note 2: At 25°C, f = 1 MHz.  
Note 3: Output deselected.  
IDT™ SERIAL REAL-TIME CLOCK  
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RTC  
DC Characteristics  
Parameter  
Input Leakage Current  
Output Leakage Current  
Supply Current  
Symbol  
Conditions1  
Min.  
Typ.  
Max.  
±1  
Units  
µA  
µA  
µA  
µA  
V
I
0V = VIN = VCC  
LI  
I
0V = VOUT = VCC  
±1  
LO  
I
I
Switch Frequency = 100 kHz  
SCL, SDA = VCC - 0.3  
300  
CC1  
CC2  
RTC Supply Current (standby)  
Input Low Voltage  
70  
V
-0.3  
0.3VCC  
VCC+0.5  
0.4  
IL  
Input High Voltage  
V
0.7VCC  
V
IH  
Output Low Voltage  
V
I
= 3.0 mA  
V
OL  
OL  
Output Low Voltage (open drain)  
Battery Supply Voltage  
Battery Supply Current  
FT/OUT  
5.5  
V
V
2.5  
3.5  
V
BAT  
I
TA = 25°C, VCC = 0V  
0.8  
1
µA  
BAT  
Oscillator ON, V  
= 3 V  
BAT  
Note 1: Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted).  
Crystal Electrical Characteristics  
Parameter1  
Symbol  
Min.  
Typ.  
Max.  
Units  
kHz  
K  
Resonant Frequency  
Series Resistance  
Load Capacitance  
f
32.768  
O
R
60  
S
C
12.5  
pF  
L
Note 1: Load capacitors are integrated within the IDT5P90005. Circuit board layout considerations for the 32.768  
kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.  
IDT™ SERIAL REAL-TIME CLOCK  
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AC Electrical Characteristics  
Unless stated otherwise, VCC = 2.0 to 5.5 V, Ambient Temperature -40 to +85C  
Parameter  
Symbol  
STANDARD  
MODE  
FAST MODE  
Units  
Min.  
Max.  
Min.  
Max.  
SCL Clock Frequency  
f
100  
400  
kHz  
µs  
µs  
µs  
ns  
SCL  
Clock Low Period  
t
4.7  
4.0  
1.3  
0.6  
LOW  
Clock High Period  
t
HIGH  
SDA and SCL Rise time  
SDA and SCL Fall Time  
t
1
0.3  
R
t
300  
300  
F
START Condition Hold Time (after this  
period the first clock pulse is generated)  
t
:STA  
4
µs  
HD  
START Condition Setup Time (only relevant  
for a repeated start condition)  
t
:STA  
4.7  
0.6  
µs  
SU  
1
Data Hold Time  
t
:DAT  
0
1.3  
100  
0.6  
1.3  
ns  
ns  
µs  
µs  
HD  
Data Setup Time  
t
:DAT  
:STO  
250  
4.0  
4.7  
SU  
SU  
STOP Condition Setup Time  
t
Time the bus must be free before a new  
transmission can start  
t
BUF  
Note 1: Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling  
edge of SCL.  
Power Down/Up Mode AC Waveforms  
RTC Power Down/Up AC Characteristics  
Parameter1,2  
SCL and SDA at VIH before Power Down  
SCL and SDA at VIH after Power Up  
Symbol  
Min.  
0
Typ.  
Max.  
Units  
ns  
t
t
PD  
rec  
10  
2000  
µs  
Note 1: Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted).  
Note 2: VCC fall time should not exceed 5 mV/µs.  
IDT™ SERIAL REAL-TIME CLOCK  
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RTC Power Down/Up Trip Points DC Characteristics  
Parameter1,2  
Symbol  
Min.  
Typ.  
Max3  
Units  
3
Backup Switchover Voltage  
V
V
-0.90  
V
-0.50  
V -0.30  
BAT  
V
SO  
BAT  
BAT  
Note 1: Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted).  
Note 2: All voltages referenced to VSS.  
Note 3: Switchover and deselect point.  
Clock Operation  
The eight byte clock register (see “Register Map” table) is used to both set the clock and to read the date and time  
from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three  
registers. Bits D6 and D7 of clock register 2 (century/hours register) contain the century enable bit (CEB) and the  
century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the  
century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3  
contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final  
register is the control register (this is described in the clock calibration section). Bit D7 of register 0 contains the  
STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant  
amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator  
restarts within one second.  
When reading or writing the time and date registers, secondary(user) buffers are used to prevent error when the  
internal registers update. When reading the time and date registers, the user buffers are synchronized to the  
internal registers on any start or stop, and when the address pointer rolls over to zero. The countdown chain is reset  
whenever the seconds register is written. Write transfers occurs on the acknowledge pulse from the device. To  
avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written  
within one second. If enabled, the 1Hz square-wave output transitions high 500ms after the seconds data transfer,  
provided the oscillator is already running.  
Note: In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then reset this bit to a  
'0.' This sequence enables a “kick start” circuit which aids the oscillator start-up during worst case conditions of  
voltage and temperature.  
1
Register Map  
Data  
D7  
Function/Range  
BCD Format  
Address  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
1
2
ST  
10 seconds  
10 minutes  
Seconds  
Minutes  
Hours  
Seconds  
00 - 59  
00 - 59  
R
Minutes  
CEB2  
CB  
10 hours  
Century/Hours  
0-1/00-23  
IDT™ SERIAL REAL-TIME CLOCK  
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RTC  
Data  
Function/Range  
BCD Format  
Address  
D7  
R
D6  
R
D5  
D4  
D3  
D2  
D1  
D0  
3
4
5
6
7
R
R
R
Day  
Day  
Date  
01 - 07  
01 - 31  
R
R
10 date  
Date  
Month  
Years  
R
R
R
10 M  
Month/Century  
Year  
01 - 12  
00 - 99  
10 years  
OUT  
FT  
R
R
R
R
R
R
Control  
Note 1. Keys:  
FT = frequency test bit  
ST = stop bit  
OUT = output level  
CEB = century enable bit  
CB = century bit  
R = Reserved BIT(keep same as default value)  
Note 2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent  
upon the initial value set).When CEB is set to '0', CB will not toggle.  
Output Driver Pin  
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control  
register. In other words, when D6 of address 7 is a zero and D7 of address 7 is a zero and then the FT/OUT pin will  
be driven low.  
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.  
Table  
FT  
0
OUT  
FT/OUT  
0
1
x
0
1
0
1
512Hz  
Initial Power-on Defaults  
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All  
other register bits will initially power on in a random state.  
IDT™ SERIAL REAL-TIME CLOCK  
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Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
Still air  
150  
140  
120  
40  
C/W  
C/W  
C/W  
C/W  
JA  
1 m/s air flow  
3 m/s air flow  
JA  
JA  
Thermal Resistance Junction to Case  
JC  
Marking Diagram  
8
5
TBD  
1
4
Notes:  
1. ###### is the lot number.  
2. YYWW is the last two digits of the year and week that the part was assembled.  
3. Bottom marking: country of origin if not USA.  
IDT™ SERIAL REAL-TIME CLOCK  
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)  
Package dimensions are kept current with JEDEC Publication No. 95  
Millimeters  
Inches  
8
Symbol  
Min  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
Max  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
Min  
Max  
A
A1  
B
C
D
E
e
.0532  
.0040  
.013  
.0688  
.0098  
.020  
E
H
INDEX  
AREA  
.0075  
.1890  
.1497  
.0098  
.1968  
.1574  
1.27 BASIC  
0.050 BASIC  
1
2
H
h
5.80  
0.25  
0.40  
0  
6.20  
0.50  
1.27  
8  
.2284  
.010  
.016  
0  
.2440  
.020  
.050  
8  
D
L
A
h x 45  
A1  
C
- C -  
e
SEATING  
PLANE  
B
L
.10 (.004)  
C
Ordering Information  
Part / Order Number  
5P90005DCGI  
Marking  
see page 6  
Shipping Packaging  
Tubes  
Package  
8-pin SOIC  
8-pin SOIC  
Temperature  
-40 to +85C  
-40 to +85C  
5P90005DCGI8  
Tape and Reel  
Parts ordered with a “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT™ SERIAL REAL-TIME CLOCK  
15  
IDT5P90005  
REV E 031209  
IDT5P90005  
SERIAL REAL-TIME CLOCK  
RTC  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/clockhelp  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device  
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered  
trademarks used to identify products or services of their respective owners.  
Printed in USA  
厂商 型号 描述 页数 下载

IDT

 		5P90005CDCGH [ Serial Real-Time Clock ] 15 页

IDT

 		5P90005CDCGH8 [ Serial Real-Time Clock ] 15 页

IDT

 		5P90005DCGI8 串行实时时钟[ SERIAL REAL-TIME CLOCK ] 16 页

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