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LY62W1024LL

型号：

LY62W1024LL

描述：

128K ×8位低功耗CMOS SRAM[ 128K X 8 BIT LOW POWER CMOS SRAM ]

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

16 页

PDF大小：

231 K

下载PDF手册
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Description  
Initial Issue  
Issue Date  
Aug.28.2005  
Mar.30.2006  
Revised ISB1 LL/LLI-LLE(max)= 50/100 μA => 20/50 μA  
IDR LL/LLI-LLE(max)= 20/40 μA => 12/30 μA  
Rev. 1.2  
Rev. 1.3  
Added SL Spec.  
Nov.2.2007  
May.6.2008  
FEATURES  
Revised typos in  
Revised ISB1/IDR(MAX.)  
Added ISB1/IDR values when TA = 25 and TA = 40  
Rev. 1.4  
Mar.30.2009  
℃
℃
FEATURES ORDERING INFORMATION  
Revised  
&
Lead free and green package available to Green package  
available  
ORDERING INFORMATION  
Added packing type in  
Revised VTERM to VT1 and VT2  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
FEATURES  
GENERAL DESCRIPTION  
The LY62W1024 is a 1,048,576-bit low power  
CMOS static random access memory organized as  
131,072 words by 8 bits. It is fabricated using very  
high performance, high reliability CMOS technology.  
Its standby current is stable within the range of  
operating temperature.  
„ Fast access time : 35/55/70ns  
„ Low power consumption:  
Operating current : 12/10/7mA (TYP.)  
Standby current : 1μA (TYP.) LL-version  
0.8μA (TYP.) SL-version  
„ Single 2.7V ~ 5.5V power supply  
„ All outputs TTL compatible  
„ Fully static operation  
The LY62W1024 is well designed for very low power  
system applications, and particularly well suited for  
battery back-up nonvolatile memory application.  
„ Tri-state output  
„ Data retention voltage : 1.5V (MIN.)  
„ Green package available  
„ Package : 32-pin 450 mil SOP  
32-pin 600 mil P-DIP  
The LY62W1024 operates from a single power  
supply of 2.7V ~ 5.5V and all inputs and outputs are  
fully TTL compatible  
32-pin 8mm x 20mm TSOP-I  
32-pin 8mm x 13.4mm STSOP  
36-ball 6mm x 8mm TFBGA  
PRODUCT FAMILY  
Product Family  
Operating Temperature Vcc Range  
Speed  
0 ~ 70℃  
-20 ~ 80℃  
-40 ~ 85℃  
LY62W1024  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
2.7 ~ 5.5V  
35/55/70ns  
35/55/70ns  
35/55/70ns  
LY62W1024(E)  
LY62W1024(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0 - A16  
Vcc  
Vss  
DQ0 – DQ7 Data Inputs/Outputs  
CE#, CE2  
WE#  
OE#  
Chip Enable Inputs  
Write Enable Input  
Output Enable Input  
Power Supply  
128Kx8  
MEMORY ARRAY  
A0-A16  
DECODER  
VCC  
VSS  
Ground  
NC  
No Connection  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
CE2  
WE#  
OE#  
CONTROL  
CIRCUIT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
PIN CONFIGURATION  
NC  
A16  
A14  
A12  
A7  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A15  
CE2  
WE#  
A13  
A8  
3
4
A11  
A9  
A8  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
Vss  
DQ2  
DQ1  
DQ0  
A0  
5
A13  
WE#  
CE2  
A15  
Vcc  
NC  
A16  
A14  
A12  
A7  
A6  
6
A5  
7
A9  
8
A4  
A11  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
LY62W1024  
A3  
9
A2  
10  
11  
12  
13  
14  
15  
16  
A1  
A6  
A5  
A4  
A1  
A2  
A3  
A0  
DQ0  
DQ1  
DQ2  
Vss  
TSOP-I/STSOP  
SOP/P-DIP  
A0  
A1 CE2 A3  
A6  
A8  
A
B
C
D
E
F
DQ4 A2 WE# A4  
A7 DQ0  
DQ1  
DQ5  
Vss  
NC  
A5  
Vcc  
Vcc  
Vss  
DQ6  
NC NC  
DQ2  
DQ7 OE# CE# A16 A15 DQ3  
A9 A10 A11 A12 A13 A14  
G
H
1
2
3
4
5
6
TFBGA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 6.5  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
H
CE2  
X
OE#  
X
WE#  
X
SUPPLY CURRENT  
MODE  
I/O OPERATION  
High-Z  
ISB1  
Standby  
X
L
X
X
High-Z  
ISB1  
L
H
H
H
Output Disable  
Read  
High-Z  
ICC,ICC1  
ICC,ICC1  
ICC,ICC1  
L
H
L
H
DOUT  
L
H
X
L
Write  
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
0.7*Vcc  
- 0.2  
- 1  
TYP. *4  
3.0  
MAX.  
5.5  
VCC+0.3  
0.6  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
2.2  
-
2.7  
-
-
V
V
VOL  
IOL = 2mA  
0.4  
Cycle time = Min.  
CE# = VIL and CE2 = VIH  
mA  
12  
10  
7
80  
60  
50  
- 35  
- 55  
- 70  
-
-
-
,
mA  
mA  
ICC  
I
I/O = 0mA  
Other pins at VIL or VIH  
Cycle time = 1 s  
Average Operating  
Power supply Current  
µ
≧
CE# = 0.2V and CE2 VCC-0.2V,  
II/O = 0mA  
ICC1  
-
1
10  
mA  
Other pins at 0.2V or VCC - 0.2V  
LL  
-
-
1
1
15  
30  
A
A
µ
µ
LLE/LLI  
CE# ≧VCC-0.2V  
SL*5  
℃
-
-
0.8  
1
2
2
A
25  
40  
µ
µ
Standby Power  
Supply Current  
≦
or CE2 0.2V  
ISB1  
SLE*5  
SLI*5  
Others at 0.2V or  
CC - 0.2V  
℃
A
V
SL  
SLE/SLI  
-
-
0.8  
0.8  
7
10  
A
µ
A
µ
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25  
5. This parameter is measured at VCC = 3.0V  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
UNIT  
LY62W1024-35 LY62W1024-55 LY62W1024-70  
MIN.  
MAX.  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
tRC  
tAA  
35  
-
-
-
10  
5
-
-
10  
-
55  
-
-
-
10  
5
-
-
10  
-
70  
-
-
-
10  
5
-
-
10  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
35  
35  
25  
-
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
*
*
*
*
-
-
-
15  
15  
-
20  
20  
-
25  
25  
-
(2) WRITE CYCLE  
PARAMETER  
SYM.  
UNIT  
LY62W1024-35 LY62W1024-55 LY62W1024-70  
MIN.  
35  
30  
30  
0
25  
0
20  
0
MAX.  
MIN.  
55  
50  
50  
0
45  
0
25  
0
MAX.  
MIN.  
70  
60  
60  
0
55  
0
30  
0
MAX.  
Write Cycle Time  
tWC  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
tDH  
tOW  
*
*
5
-
5
-
5
-
tWHZ  
15  
20  
25  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
CE2  
WE#  
Dout  
Din  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
CE2  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high or CE2 must be low during all address transitions.  
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.  
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high  
impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN.  
TYP. MAX. UNIT  
VCC for Data Retention  
VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V  
1.5  
-
-
-
5.5  
12  
30  
V
LL  
0.5  
0.5  
A
A
µ
µ
LLE/LLI  
SL  
SLE  
SLI  
SL  
V
CC = 1.5V  
℃
-
-
0.4  
0.5  
2
2
A
25  
µ
µ
CE# ≧ VCC - 0.2V  
or CE2 ≦ 0.2V  
Other pins at 0.2V or VCC-0.2V  
Data Retention Current  
IDR  
℃
40  
A
-
-
0.4  
0.4  
5
8
A
µ
A
µ
SLE/SLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Low Vcc Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low Vcc Data Retention Waveform (2) (CE2 controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
CE2 ≦ 0.2V  
CE2  
VIL  
VIL  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
PACKAGE OUTLINE DIMENSION  
32 pin 450 mil SOP Package Outline Dimension  
UNIT  
SYM.  
INCH.(BASE)  
MM(REF)  
A
A1  
A2  
b
c
D
0.118 (MAX)  
0.004(MIN)  
0.111(MAX)  
0.016(TYP)  
0.008(TYP)  
0.817(MAX)  
2.997 (MAX)  
0.102(MIN)  
2.82(MAX)  
0.406(TYP)  
0.203(TYP)  
20.75(MAX)  
E
±
±
0.445 0.005 11.303 0.127  
E1  
e
±
±
0.555 0.012 14.097 0.305  
0.050(TYP) 1.270(TYP)  
L
±
±
0.0347 0.008 0.881 0.203  
L1  
S
y
±
±
0.055 0.008 1.397 0.203  
0.026(MAX)  
0.004(MAX)  
0o -10o  
0.660 (MAX)  
0.101(MAX)  
0o -10o  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
32 pin 600 mil P-DIP Package Outline Dimension  
UNIT  
SYM.  
INCH(BASE)  
0.001 (MIN)  
MM(REF)  
A1  
A2  
B
0.254 (MIN)  
±
3.810 0.127  
±
0.457 0.127  
±
0.150 0.005  
±
0.018 0.005  
D
±
±
41.910 0.127  
1.650 0.005  
E
±
±
15.240 0.254  
0.600 0.010  
E1  
e
±
±
0.544 0.004  
13.818 0.102  
0.100 (TYP)  
2.540 (TYP)  
eB  
L
±
±
16.256 0.508.  
±
3.302 0.254  
0.640 0.020  
±
0.130 0.010  
S
±
±
1.905 0.254  
0.075 0.010  
Q1  
±
±
1.778 0.127  
0.070 0.005  
Note : D/E1/S dimension do not include mold flash.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
32 pin 8mm x 20mm TSOP-I Package Outline Dimension  
UNIT  
INCH(BASE)  
MM(REF)  
SYM.  
A
0.047 (MAX)  
1.20 (MAX)  
A1  
A2  
±
±
0.004 0.002 0.10 0.05  
±
±
0.039 0.002 1.00 0.05  
0.008 + 0.002 0.20 + 0.05  
b
- 0.001  
0.005 (TYP)  
-0.03  
0.127 (TYP)  
c
D
±
±
0.724 0.004 18.40 0.10  
E
±
±
0.315 0.004 8.00 0.10  
e
0.020 (TYP) 0.50 (TYP)  
HD  
L
±
±
0.787 0.008 20.00 0.20  
±
±
0.0197 0.004 0.50 0.10  
L1  
y
Θ
±
±
0.0315 0.004 0.08 0.10  
0.003 (MAX) 0.076 (MAX)  
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
32 pin 8mm x 13.4mm STSOP Package Outline Dimension  
HD  
c
L
12° (2x)  
12° (2x)  
32  
1
17  
16  
"A"  
y
Seating Plane  
D
12° (2X)  
16  
17  
GAUGE PLANE  
0
SEATING PLANE  
L
12° (2X)  
L1  
"A" DATAIL VIEW  
1
32  
UNIT  
INCH(BASE)  
0.049 (MAX)  
MM(REF)  
1.25 (MAX)  
SYM.  
A
A1  
A2  
b
±
±
0.005 0.002 0.130 0.05  
±
±
0.039 0.002 1.00 0.05  
±
±
0.008 0.01  
0.20 0.025  
c
0.005 (TYP)  
0.127 (TYP)  
D
±
±
0.465 0.004 11.80 0.10  
E
±
±
0.315 0.004 8.00 0.10  
e
0.020 (TYP) 0.50 (TYP)  
HD  
L
±
±
13.40 0.20.  
0.528 0.008  
±
±
0.0197 0.004 0.50 0.10  
L1  
y
Θ
±
±
0.0315 0.004 0.8 0.10  
0.003 (MAX) 0.076 (MAX)  
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
36 ball 6mm × 8mm TFBGA Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
13  
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
ORDERING INFORMATION  
LY62W1024 U V - WW XX Y Z  
Z : Packing Type  
Blank : Tube or Tray  
T : Tape Reel  
Y : Temperature Range  
Blank : (Commercial) 0°C ~ 70°C  
E : (Extended) -20°C ~ +80°C  
I : (Industrial) -40°C ~ +85°C  
XX : Power Type  
LL : Ultra Low Power  
SL : Special Ultra Low Power  
WW : Access Time(Speed)  
V : Lead Information  
L : Green Package  
U : Package Type  
S : 32-pin 450 mil SOP  
P : 32-pin 600 mil P-DIP  
L : 32-pin 8 mm x 20 mm TSOP-I  
R : 32-pin 8 mm x 13.4 mm STSOP  
G : 36-ball 6 mm x 8 mm TFBGA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
14  
®
LY62W1024  
128K X 8 BIT LOW POWER CMOS SRAM  
Rev. 1.4  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
15  
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