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LY530ALTR

型号：

LY530ALTR

描述：

MEMS惯性传感器单轴模拟和数字输出偏航率陀螺仪[ MEMS inertial sensor single-axis analog and digital output yaw rate gyroscope ]

品牌：

STMICROELECTRONICS[ ST ]

页数：

30 页

PDF大小：

579 K

下载PDF手册
LY530AL  
MEMS inertial sensor  
single-axis analog and digital output yaw rate gyroscope  
Preliminary Data  
Features  
■ 2.7 V to 3.6 V single supply operation  
■ Low power consumption  
■ Embedded power-down  
■
300ꢀ/sec full scale  
■ Absolute analog rate output  
2
■ I C/SPI digital output interface  
■ Integrated low-pass filters  
■ Additional high pass filter for digital output  
■ Embedded self-test  
LGA-16 (5x5x1.5mm)  
■ High shock survivability  
®
■ ECOPACK RoHS and “Green” compliant  
(see Section 7)  
The output of LY530AL has a full scale of 300 ꢀ/s  
and is capable of measuring rates with a -3 dB  
bandwidth up to 88 Hz.  
Description  
The LY530AL is a low-power single-axis yaw rate  
sensor. It includes a sensing element and an IC  
interface able to provide the measured angular  
rate to the external world through an analog  
The LY530AL is available in a plastic land grid  
array (LGA) package and can operate within a  
temperature range from -40 ꢀC to +85 ꢀC.  
2
output voltage and I C/SPI digital interfaces.  
The LY530AL belongs to a family of products  
suitable for a variety of applications, including:  
The sensing element, capable of detecting the  
yaw rate, is manufactured using a dedicated  
micromachining process developed by ST to  
produce inertial sensors and actuators on silicon  
wafers.  
– Gaming and virtual reality input devices  
– Motion control with MMI (man-machine  
interface)  
– Image stabilization for digital video and  
digital still cameras  
– GPS navigation systems  
– Appliances and robotics  
The IC interface is manufactured using a CMOS  
process that allows a high level of integration to  
design a dedicated circuit which is trimmed to  
better match the sensing element characteristics.  
Table 1.  
Device summary  
Order code  
Temperature range (°C)  
Package  
Packing  
LY530AL  
-40 to +85  
-40 to +85  
LGA-16 (5x5x1.5)  
LGA-16 (5x5x1.5)  
Tray  
LY530ALTR  
Tape and reel  
September 2008  
Rev 1  
1/30  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
30  
Contents  
LY530AL  
Contents  
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.1  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8  
2.1  
2.2  
2.3  
2.4  
Mechanical characteristics (analog output) . . . . . . . . . . . . . . . . . . . . . . . . 8  
Mechanical characteristics (digital output) . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2.4.1  
2.4.2  
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
2.5  
2.6  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
2.6.1  
2.6.2  
2.6.3  
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
3
4
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
3.1  
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
4.1  
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
4.1.1  
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
4.2  
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
4.2.1  
4.2.2  
4.2.3  
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
5
6
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
6.1  
6.2  
6.3  
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
CTRL_REG (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
FILTER_CFG_REG (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
2/30  
LY530AL  
Contents  
6.4  
6.5  
6.6  
6.7  
OUTPUT_SEL_REG (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
STATUS_REG(27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
OUT_CONV_H(28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
OUT_CONV_L(29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
7
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
3/30  
List of tables  
LY530AL  
List of tables  
Table 1.  
Table 2.  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Mechanical characteristics @ Vdd = 3.3 V, T = 25 ꢀC unless otherwise noted . . . . . . . . . . 8  
Mechanical characteristics @ Vdd = 3.3 V, T = 25 ꢀC unless otherwise noted . . . . . . . . . . 8  
Electrical characteristics @ Vdd =3.3 V, T=25 ꢀC unless otherwise noted. . . . . . . . . . . . . 10  
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
PLL low-pass filter components’ values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19  
Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19  
Registers addresses map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
CTRL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
FILTER_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
FILTER_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
High pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Low pass filter pole -3dB frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
OUTPUT_SEL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
OUTPUT_SEL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Filtering selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Forbidden combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
STATUS_REG(27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
STATUS_REG(27h) description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
OUT_CONV_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
OUT_CONV_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Table 9.  
Table 10.  
Table 11.  
Table 12.  
Table 13.  
Table 14.  
Table 15.  
Table 16.  
Table 17.  
Table 18.  
Table 19.  
Table 20.  
Table 21.  
Table 22.  
Table 23.  
Table 24.  
Table 25.  
Table 26.  
Table 27.  
Table 28.  
Table 29.  
Table 30.  
Table 31.  
Table 32.  
Table 33.  
4/30  
LY530AL  
List of figures  
List of figures  
Figure 1.  
Figure 2.  
Figure 3.  
Figure 4.  
Figure 5.  
Figure 6.  
Figure 7.  
Figure 8.  
Figure 9.  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
I2C slave timing diagram (4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
LY530AL electrical connections and external components values. . . . . . . . . . . . . . . . . . . 15  
Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 10. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Figure 12. LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
5/30  
Block diagram and pin description  
LY530AL  
1
Block diagram and pin description  
Figure 1.  
Block diagram  
ANALOG OUTPUT  
ACTIVE  
LOW-PASS  
FILTER  
CS  
CHARGE  
AMPLIFIER  
DEMODULATOR  
I2C  
SCL/SPC  
SDA/SDO/SDI  
SDO  
CONTROL  
LOGIC  
Sens+  
SWITCHED  
CAPACITOR  
LOW-PASS  
FILTER  
A/D  
CONVERTER  
+Ω  
SPI  
z
Sens-  
ANALOG  
CONDITIONING  
Feedback+  
TRANS-  
IMPEDANCE  
AMPLIFIER  
Feedback-  
Drive-  
AUTOMATIC  
GAIN  
CONTROL  
VOLTAGE  
GAIN  
AMPLIFIER  
Drive+  
PHASE  
TRIMMING  
CIRCUITS  
SELF TEST  
REFERENCE  
CLOCK  
GENERATOR  
1.1  
Pin description  
Figure 2.  
Pin connection  
+Ω  
z
14  
16  
SDA_SDI_SDO  
13  
1
5
FILTVDD  
VCONT  
SDO  
DR  
CACT  
CS  
ANALOG OUTPUT  
IF_DIS  
SCL / SPC  
9
6
8
(TOP VIEW)  
DIRECTION OF THE  
DETECTABLE  
ANGULAR RATE  
(BOTTOM VIEW)  
6/30  
LY530AL  
Block diagram and pin description  
Digital function  
Table 2.  
Pin #  
Pin description  
Pin Name  
Analog function  
1
2
3
FILTVDD  
VCONT  
CACT  
PLL filter connection pin #2  
PLL filter connection pin #1  
Active filter capacitor  
PLL filter connection pin #2  
PLL filter connection pin #1  
Active filter capacitor  
ANALOG  
OUTPUT  
4
Rate signal output voltage  
Leave unconnected  
5
6
IF_DIS  
GND  
Leave unconnected  
0V supply voltage  
Digital Interface Selection (See Table 19)  
0V supply voltage  
Self-test (logic 0: normal mode;  
logic 1: self-test)  
7
8
9
ST  
PD  
Leave unconnected  
Power-down (logic 0: normal  
mode; logic 1: power-down mode)  
Connect to Vdd  
SCL  
SPC  
I2C Serial Clock (SCL)  
SPI Serial Port Clock (SPC)  
Leave unconnected  
SPI enable  
10  
11  
12  
CS  
DR  
Leave unconnected  
Leave unconnected  
I2C/SPI mode selection (1: I2C mode; 0: SPI mode)  
DataReady  
Leave unconnected or connect to SPI Serial data output (4-wire mode only)  
SDO  
Vdd  
I2C less significant bit of the device address  
I2C Serial Data (SDA)  
SPI Serial Data Input (SDI)  
3-wire Interface Serial Data Output  
Leave unconnected or connect to  
Vdd  
13  
SDA_SDI_SDO  
14  
15  
16  
Res  
Connect to Vdd  
Connect to Vdd  
VDDD  
VDDA  
Digital side Vdd supply  
Analog side Vdd supply  
Digital side Vdd supply  
Analog side Vdd supply  
7/30  
Mechanical and electrical specifications  
LY530AL  
2
Mechanical and electrical specifications  
2.1  
Mechanical characteristics (analog output)  
(1)  
Table 3.  
Symbol  
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted  
Parameter  
Test condition  
Min.  
Typ.(2)  
Max.  
Unit  
FS  
So  
Measurement range  
Sensitivity  
300  
3.3  
ꢀ/s  
mV/ ꢀ/s  
Sensitivity change vs.  
temperature  
Zero-rate level(3)  
SoDr  
Voff  
From -40 ꢀC to +85 ꢀC  
From -40 ꢀC to +85 ꢀC  
4
1.65  
5
%
V
Zero-rate level change  
vs. temperature  
OffDr  
ꢀ/s  
NL  
Non linearity(4)  
-3dB bandwidth(5)(6)  
Best fit straight line  
CACT = 10 nF  
0.8  
88  
% FS  
Hz  
BW  
ꢀ/s /  
Hz  
Rn  
Rate noise density  
0.1  
Self-test output  
Vt  
+300  
300  
4.5  
mV  
ms  
voltage change(7)  
Sup  
Fres  
Start-up time  
Settling to 5 ꢀ/s  
Sensing element  
resonant frequency  
kHz  
Operating  
temperature range  
Top  
Wh  
-40  
+85  
ꢀC  
Product weight  
160  
mg  
1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5.  
2. Typical specifications are not guaranteed  
3. Zero rate level is absolute with respect to power supply  
4. Specified by design  
5. The product is capable of sensing angular rates extending from DC to the selected bandwidth  
6. User selectable by external capacitor CACT  
7. “Self-test output voltage change” is defined as Vout(Vst = logic 1) - Vout(Vst = logic 0)  
2.2  
Mechanical characteristics (digital output)  
(1)  
Table 4.  
Symbol  
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted  
Parameter  
Test condition  
Min.  
Typ.(2)  
Max.  
Unit  
So  
Voff  
Sensitivity  
1.55  
0
LSb/ ꢀ/s  
LSb  
Zero-rate level(3)  
Output data rate  
ODR  
1
kHz  
8/30  
LY530AL  
Mechanical and electrical specifications  
(1)  
Table 4.  
Symbol  
Mechanical characteristics @ Vdd = 3.3 V, T = 25 °C unless otherwise noted  
Parameter  
Test condition  
Min.  
Typ.(2)  
Max.  
Unit  
Self-test output  
change(4)  
Vt  
230  
LSb  
Sensing element  
resonant frequency  
Fres  
4.5  
kHz  
Operating  
temperature range  
Top  
Wh  
-40  
+85  
ꢀC  
Product weight  
160  
mg  
1. The product is factory calibrated at 3.3 V. The operational power supply range is specified in Table 5.  
2. Typical specifications are not guaranteed  
3. The product is capable of sensing angular rates extending from DC to the selected bandwidth  
4. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on OUTPUT_SEL_REG=1) OUTPUT[LSb](Self-test bit on  
.
OUTPUT_SEL_REG=0)  
9/30  
Mechanical and electrical specifications  
LY530AL  
2.3  
Electrical characteristics  
(1)  
Table 5.  
Symbol  
Electrical characteristics @ Vdd =3.3 V, T=25 °C unless otherwise noted  
Parameter  
Supply voltage  
Test condition  
Min.  
Typ.(2)  
Max.  
Unit  
Vdd  
2.7  
3.3  
4.8  
5.5  
3.6  
V
Idd_A  
Idd_D  
Supply current (analog)  
Supply current (digital)  
PD pin connected to GND  
mA  
mA  
Supply current in  
power-down mode  
IddPdn  
VST  
PD pin connected to Vdd  
1
µA  
Logic 0 level  
Logic 1 level  
Logic 0 level  
Logic 1 level  
0
0.2*Vdd  
Vdd  
Self-test input  
(Analog use)  
V
0.8*Vdd  
0
0.2*Vdd  
Vdd  
Power-down input  
(Analog use)  
VPD  
V
0.8*Vdd  
Active low-pass filter  
capacitor  
CACT  
10  
nF  
OVS  
Output voltage swing(3)  
Capacitive load drive(3)  
Iout = 100µA  
0.4  
0.4  
Vdd-0.4  
10  
V
CLOAD  
nF  
Operating temperature  
range  
Top  
-40  
+85  
ꢀC  
1. The product is factory calibrated at 3.3 V  
2. Typical specifications are not guaranteed  
3. Referred to ANALOG OUTPUT pin #6  
10/30  
LY530AL  
Mechanical and electrical specifications  
2.4  
Communication interface characteristics  
2.4.1  
SPI - serial peripheral interface  
Subject to general operating conditions for Vdd and Top.  
Table 6.  
SPI slave timing values  
Value(1)  
Symbol  
Parameter  
Unit  
Min  
Max  
tc(SPC)  
SPI clock cycle  
100  
ns  
fc(SPC)  
tsu(CS)  
th(CS)  
tsu(SI)  
th(SI)  
SPI clock frequency  
CS setup time  
10  
MHz  
5
8
CS hold time  
SDI input setup time  
SDI input hold time  
5
15  
ns  
tv(SO)  
th(SO)  
tdis(SO)  
SDO valid output time  
SDO output hold time  
SDO output disable time  
50  
50  
6
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not  
tested in production  
(2)  
Figure 3. SPI slave timing diagram  
CS  
(3)  
(3)  
(3)  
(3)  
(3)  
(3)  
tc(SPC)  
tsu(CS)  
th(CS)  
SPC  
SDI  
tsu(SI)  
th(SI)  
LSB IN  
MSB IN  
tdis(SO)  
tv(SO)  
th(SO)  
MSB OUT  
LSB OUT  
(3)  
(3)  
SDO  
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port  
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up  
resistors  
11/30  
Mechanical and electrical specifications  
2
LY530AL  
2.4.2  
I C - Inter IC control interface  
Subject to general operating conditions for Vdd and Top.  
2
Table 7.  
I C slave timing values  
I2C Standard mode(1)  
I2C Fast mode (1)  
Symbol  
Parameter  
Unit  
KHz  
µs  
Min  
0
Max  
Min  
0
Max  
f(SCL)  
tw(SCLL)  
tw(SCLH)  
tsu(SDA)  
th(SDA)  
SCL clock frequency  
SCL clock low time  
SCL clock high time  
SDA setup time  
100  
400  
4.7  
4.0  
250  
1.3  
0.6  
100  
ns  
µs  
0(2)  
3.45  
0(2)  
0.9  
SDA data hold time  
(3)  
tr(SDA) r(SCL)  
tf(SDA) f(SCL)  
th(ST)  
tsu(SR)  
t
SDA and SCL rise time  
SDA and SCL fall time  
START condition hold time  
1000  
300  
20 + 0.1Cb  
ns  
(3)  
t
300  
300  
20 + 0.1Cb  
0.6  
4
Repeated START condition  
setup time  
4.7  
4
0.6  
0.6  
1.3  
µs  
tsu(SP)  
STOP condition setup time  
Bus free time between STOP  
and START condition  
tw(SP:SR)  
4.7  
1. Data based on standard I2C protocol requirement, not tested in production  
2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to  
bridge the undefined region of the falling edge of SCL  
3. Cb = total capacitance of one bus line, in pF  
2
(4)  
Figure 4. I C slave timing diagram  
REPEATED  
START  
START  
tsu(SR)  
START  
tw(SP:SR)  
SDA  
SCL  
tsu(SDA)  
th(SDA)  
tf(SDA)  
tr(SDA)  
STOP  
tsu(SP)  
th(ST) tw(SCLL)  
tw(SCLH)  
tr(SCL)  
tf(SCL)  
4. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports  
12/30  
LY530AL  
Mechanical and electrical specifications  
2.5  
Absolute maximum ratings  
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage  
to the device. This is a stress rating only and functional operation of the device under these  
conditions is not implied. Exposure to maximum rating conditions for extended periods may  
affect device reliability.  
Table 8.  
Symbol  
Absolute maximum ratings  
Ratings  
Maximum value  
Unit  
Vdd  
Vin  
Supply voltage  
-0.3 to 6  
-0.3 to Vdd +0.3  
3000 g for 0.5 ms  
10000 g for 0.1 ms  
-40 to +125  
V
V
Input voltage on any control pin (PD, ST)  
AUNP  
Acceleration (not powered)  
TSTG  
ESD  
Storage temperature range  
ꢀC  
kV  
Electrostatic discharge protection  
2 (HBM)  
This is a mechanical shock sensitive device, improper handling can cause permanent  
damage to the part  
This is an ESD sensitive device, improper handling can cause permanent damage to  
the part  
13/30  
Mechanical and electrical specifications  
LY530AL  
2.6  
Terminology  
2.6.1  
Sensitivity  
A yaw rate gyroscope is a Z-axis rate device that produces a positive-going output value for  
counterclockwise rotation around the axis normal to the package top. Sensitivity describes  
the gain of the sensor and can be determined by applying a defined angular velocity to it.  
This value changes very little over temperature and also very little over time.  
2.6.2  
2.6.3  
Zero-rate level  
Zero-rate level describes the actual output value if there is no angular rate present.Zero-rate  
level of precise MEMS sensors is, to some extent, a result of stress to the sensor and  
therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit  
board or after exposing it to extensive mechanical stress. This value changes very little over  
temperature and also very little over time.  
Self-test  
Self-test allows to test the mechanical and electric part of the sensor, allowing the seismic  
mass to be moved by means of an electrostatic test-force. If the device is used as analog  
component the Self-test function is off when the ST pin is connected to GND. When the ST  
pin is tied to Vdd, an actuation force is applied to the sensor, emulating a definite Coriolis  
force. In this case the sensor output will exhibit a voltage change in its DC level which is also  
depending on the supply voltage.  
For the digital use of the device, the self test function is enabled acting on ST_bit inside  
OUTPUT_SEL_REG(23h).  
When ST is active, the device output level is given by the algebraic sum of the signals  
produced by the velocity acting on the sensor and by the electrostatic test-force. If the output  
signals change within the amplitude specified in Table 3, then the mechanical element is  
working properly and the parameters of the interface chip are within the defined  
specification.  
14/30  
LY530AL  
Application hints  
3
Application hints  
Figure 5.  
LY530AL electrical connections and external components values  
+Ω  
z
C2  
9nF  
9.5kOhm  
R1  
450nF  
VDDA VDDD GND  
GND  
GND  
GND  
C1  
100 nF  
10 µF  
100 nF  
10 µF  
16  
14  
SDA_SDI_SDO  
1
5
13  
9
Optional  
SDO  
DR  
Low-pass filter  
CACT  
LY530AL  
(Top View)  
ROPT  
CS  
VoutYAW  
0.4nF  
COPT  
SCL/SPC  
CLOAD  
6
8
GND  
GND  
GND  
IF_DIS  
Digital signals  
Power supply decoupling capacitors (100 nF ceramic or polyester + 10 µF Aluminum)  
should be placed as near as possible to the device (common design practice).  
VDDA(pin 16) and VDDD(pin 15) lines have been kept separated to avoid switching noise  
coupling on the analog side.  
The LY530AL allows to band limit the output rate response through the use of two first-order  
on-chip filters: a switched capacitor low-pass filter, with 400Hz -3dB bandwidth, in  
combination with an active low-pass filter. The active filter -3 dB nominal frequency (f ) is  
tA  
set through an internal resistor R  
and the external capacitor C  
(added between  
ACT  
ACT  
CACT pin #3 and ANALOG OUTPUT pin #4), by the formula:  
1
f
= --------------------------------------------------  
tA  
2π ⋅ RACT ⋅ CACT  
The value of the internal resistor R  
is 180 kΩ, while the external capacitor C  
is used to  
ACT  
ACT  
select the signal bandwidth. The sensed frequency range spans from DC up to the selected  
bandwidth.  
In order to further reduce high-frequency noise, the LY530AL supports an additional optional  
low-pass filter on ANALOG OUTPUT pin #4 (Figure 5). The cutoff frequency (f ) is given by  
tP  
the formula:  
15/30  
Application hints  
LY530AL  
1
f
= ----------------------------------------------------  
tP  
2π ⋅ R  
⋅ C  
OPT  
OPT  
The LY530AL IC includes a PLL (phase locked loop) circuit to synchronize driving and  
sensing interfaces. Capacitors and resistors must be added at the FILTVDD and VCONT  
pins (as shown in Figure 5) to implement a second-order low-pass filter. Table 9  
summarizes the PLL low-pass filter components’ values.  
Table 9.  
PLL low-pass filter components’ values  
Component  
Value  
C1  
C2  
R1  
450 nF 10%  
9 nF 10%  
9.5 kΩ 10%  
3.1  
Soldering information  
®
The LGA package is compliant with the ECOPACK , RoHS and “Green” standard.  
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.  
Leave “Pin 1 Indicator” unconnected during soldering.  
Land pattern and soldering recommendations are available at www.st.com/mems.  
16/30  
LY530AL  
Digital interfaces  
4
Digital interfaces  
2
The registers embedded inside the LY530AL may be accessed through both the I C and SPI  
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire  
interface mode.  
2
The serial interfaces are mapped onto the same pins. To select/exploit the I C interface, CS  
line must be tied high (i.e connected to Vdd_IO).  
Table 10. Serial interface pin description  
Pin name  
Pin description  
SPI enable  
CS  
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)  
I2C Serial Clock (SCL)  
SCL/SPC  
SDA/SDI/SDO  
SDO  
SPI Serial Port Clock (SPC)  
I2C Serial Data (SDA)  
SPI Serial Data Input (SDI)  
3-wire Interface Serial Data Output (SDO)  
SPI Serial Data Output (SDO)  
I2C less significant bit of the device address  
4.1  
I2C serial interface  
2
2
The LY530AL I C is a bus slave. The I C is employed to write data into registers whose  
content can also be read back.  
2
The relevant I C terminology is given in the table below.  
2
Table 11. I C terminology  
Term  
Description  
The device which sends data to the bus  
Transmitter  
Receiver  
The device which receives data from the bus  
The device which initiates a transfer, generates clock signals and terminates a  
transfer  
Master  
Slave  
The device addressed by the master  
2
There are two signals associated with the I C bus: the Serial Clock Line (SCL) and the serial  
data line (SDA). The latter is a bidirectional line used for sending and receiving the data  
to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor  
embedded inside the LY530AL. When the bus is free both the lines are high.  
2
2
The I C interface is compliant with fast mode (400 kHz) I C standards as well as with the  
normal mode.  
17/30  
Digital interfaces  
2
LY530AL  
4.1.1  
I C operation  
The transaction on the bus is started through a START (ST) signal. A START condition is  
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After  
this has been transmitted by the Master, the bus is considered busy. The next byte of data  
transmitted after the start condition contains the address of the slave in the first 7 bits and  
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to  
the slave. When an address is sent, each device in the system compares the first seven bits  
after a start condition with its address. If they match, the device considers itself addressed  
by the Master.  
The Slave ADdress (SAD) associated to the LY530AL is 110100xb. SDO pin can be used to  
modify less significant bit of the device address. If SDO pin is connected to voltage supply  
LSb is ‘1’ (address 1101001b) else if SDO pin is connected to ground LSb value is ‘0’  
(address 1101000b). This solution permits to connect and address two different gyroscopes  
2
to the same I C bus.  
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line  
during the acknowledge pulse. The receiver must then pull the data line LOW so that it  
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which  
has been addressed is obliged to generate an acknowledge after each byte of data  
received.  
2
The I C embedded inside the LY530AL behaves like a slave device and the following  
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a  
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7  
LSb represent the actual register address while the MSB enables address auto increment. If  
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented  
to allow multiple data read/write.  
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated  
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’  
(Write) the Master will transmit to the slave with direction unchanged. Table explains how  
the SAD+Read/Write bit pattern is composed, listing all the possible configurations.  
Table 12. SAD+Read/Write patterns  
Command  
SAD[6:1]  
SAD[0] = SDO  
R/W  
SAD+R/W  
Read  
Write  
Read  
Write  
110100  
110100  
110100  
110100  
0
0
1
1
1
0
1
0
11010001 (39h)  
11010000 (38h)  
11010011 (3Bh)  
11010010 (3Ah)  
Table 13. Transfer when Master is writing one byte to slave  
Master  
Slave  
ST  
SAD + W  
SUB  
DATA  
SP  
SAK  
SAK  
SAK  
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LY530AL  
Digital interfaces  
Table 14. Transfer when Master is writing multiple bytes to slave  
Master  
Slave  
ST  
SAD + W  
SUB  
DATA  
DATA  
SP  
SAK  
SAK  
SAK  
SAK  
Table 15. Transfer when Master is receiving (reading) one byte of data from slave  
Master ST SAD + W  
Slave  
SUB  
SR SAD + R  
NMAK SP  
SAK  
SAK  
SAK  
DATA  
Table 16. Transfer when Master is receiving (reading) multiple bytes of data from slave  
Master ST SAD+W  
Slave  
SUB  
SR SAD+R  
MAK  
MAK  
NMAK SP  
SAK  
SAK  
SAK DATA  
DATA  
DATA  
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number  
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit  
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed  
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait  
state. Data transfer only continues when the receiver is ready for another byte and releases  
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to  
receive because it is performing some real time function) the data line must be left HIGH by  
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line  
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be  
terminated by the generation of a STOP (SP) condition.  
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-  
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the  
address of first register to be read.  
In the presented communication format MAK is Master Acknowledge and NMAK is No  
Master Acknowledge.  
4.2  
SPI bus interface  
The LY530AL SPI is a bus slave. The SPI allows to write and read the registers of the  
device.  
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.  
19/30  
Digital interfaces  
Figure 6.  
CS  
LY530AL  
Read & write protocol  
SPC  
SDI  
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0  
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0  
RW  
MS  
AD5 AD4 AD3 AD2 AD1 AD0  
SDO  
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of  
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is  
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and  
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the  
falling edge of SPC and should be captured at the rising edge of SPC.  
Both the Read Register and Write Register commands are completed in 16 clock pulses or  
in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two  
falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling  
edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just  
before the rising edge of CS.  
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)  
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.  
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.  
When 1, the address will be auto incremented in multiple read/write commands.  
bit 2-7: address AD(5:0). This is the address field of the indexed register.  
bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb  
first).  
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb  
first).  
In multiple read/write commands further blocks of 8 clock periods will be added. When MS  
bit is 0 the address used to read/write data remains the same for every block. When MS bit  
is 1 the address used to read/write data is incremented at every block.  
The function and the behavior of SDI and SDO remain unchanged.  
20/30  
LY530AL  
Digital interfaces  
4.2.1  
SPI read  
Figure 7.  
SPI read protocol  
CS  
SPC  
SDI  
RW  
MS  
AD5 AD4 AD3 AD2 AD1 AD0  
SDO  
DO7DO6 DO5DO4 DO3DO2 DO1DO0  
The SPI Read command is performed with 16 clock pulses. Multiple byte read command is  
performed adding blocks of 8 clock pulses at the previous one.  
bit 0: READ bit. The value is 1.  
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple  
reading.  
bit 2-7: address AD(5:0). This is the address field of the indexed register.  
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb  
first).  
bit 16-... : data DO(...-8). Further data in multiple byte reading.  
Figure 8.  
Multiple bytes SPI read protocol (2 bytes example)  
CS  
SPC  
SDI  
RW  
MS AD5 AD4 AD3 AD2 AD1 AD0  
SDO  
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8  
4.2.2  
SPI write  
Figure 9.  
SPI write protocol  
CS  
SPC  
SDI  
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0  
RW  
MS AD5 AD4 AD3 AD2 AD1 AD0  
21/30  
Digital interfaces  
LY530AL  
The SPI Write command is performed with 16 clock pulses. Multiple byte write command is  
performed adding blocks of 8 clock pulses at the previous one.  
bit 0: WRITE bit. The value is 0.  
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple  
writing.  
bit 2 -7: address AD(5:0). This is the address field of the indexed register.  
bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device  
(MSb first).  
bit 16-... : data DI(...-8). Further data in multiple byte writing.  
Figure 10. Multiple bytes SPI write protocol (2 bytes example)  
CS  
SPC  
SDI  
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15DI14DI13DI12DI11DI10DI9 DI8  
RW  
MS  
AD5 AD4 AD3 AD2 AD1 AD0  
4.2.3  
SPI read in 3-wires mode  
3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in  
CTRL_REG2.  
Figure 11. SPI read protocol in 3-wires mode  
CS  
SPC  
SDI/O  
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0  
RW  
MS AD5 AD4 AD3 AD2 AD1 AD0  
The SPI Read command is performed with 16 clock pulses:  
bit 0: READ bit. The value is 1.  
bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple  
reading.  
bit 2-7: address AD(5:0). This is the address field of the indexed register.  
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb  
first).  
Multiple read command is also available in 3-wires mode.  
22/30  
LY530AL  
Register mapping  
5
Register mapping  
The table given below provides a listing of the 8 bit registers embedded in the device and  
the related addresses:  
Table 17. Registers addresses map  
Register address  
Name  
Type  
Default  
Comment  
Hex  
Binary  
Reserved (do not modify)  
WHO_AM_I  
00-0E  
0F  
Reserved  
Dummy register  
Reserved  
r
000 1111 11010001  
Reserved (do not modify)  
CTRL_REG  
10-1F  
20  
rw  
010 0000 00000000  
010 0001  
Reserved (do not modify)  
FILTER_CFG_REG  
OUTPUT_SEL_REG  
Reserved (do not modify)  
Reserved (do not modify)  
Reserved (do not modify)  
STATUS_REG  
21  
Reserved  
rw  
rw  
22  
010 0010  
Loaded at boot  
23  
010 0011 00000000  
001 1000  
24  
Reserved  
Reserved  
Reserved  
25  
001 1001  
26  
001 1010  
r
r
r
27  
010 0111 00000000  
010 1000  
OUT_CONV_H  
28  
OUT_CONV_L  
29  
010 1001  
Registers marked as “Reserved” or not listed must not be changed. The writing to those  
registers may cause permanent damages to the device.  
23/30  
Register description  
LY530AL  
6
Register description  
The device contains a set of registers which are used to control its behavior and to retrieve  
angular rate data. The registers address, made of 7 bits, is used to identify them and to write  
the data through serial interface.  
6.1  
WHO_AM_I (0Fh)  
Table 18. WHO_AM_I register  
1
1
0
1
0
0
0
1
Device identification register.  
This register contains the device identifier that for LY530AL is set to D1h  
6.2  
CTRL_REG (20h)  
Table 19. CTRL_REG register  
TUD_SDO  
DIG_en  
0(1)  
IF_SEL  
BDU  
alg  
BOOT  
SIM  
1. ‘0’ is the default value. This value must not be changed  
Table 20. CTRL_REG description  
TUD_SDO Pull Up disable for SDO pin. Default value: 0  
(0: Pull Up connected; 1: Pull Up disabled)  
DIG_en  
IF_SEL  
BDU  
Power Down bit. Default value: 0  
(0: Device is in power down mode; 1: Divice is in normal mode)  
Interface selection. Default value: 0  
(0: both interfaces available; 1: IF_DIS pin value selects the interface)  
Block data update. Default value: 0  
(0: continuos update; 1: update inhibited)  
alg  
Data alignment selection bit. Default value: 0  
(0: 16 bit left justified; 1: 10 bit right justified)  
BOOT  
SIM  
Reboot of memory content. Default value: 0  
(0: normal mode; 1: memory reboot)  
SPI serial interface mode selection bit. Default value: 0  
(0: 4-wire mode; 1:3-wire mode)  
TUD_SDO: When this bit is set to ‘1’ the Pull Up on SDO pin is disabled.  
DIG_en: When this bit is set to ‘1’ the device is in normal mode. When DIG_en bit is ‘0’ the  
device is in power down mode.  
IF_SEL: Setting this bit to ‘1’ the voltage value applied to IF_DIS pin selects one of the two  
digital interfaces (‘1’ for I2C only, ‘0’ for SPI only).  
24/30  
LY530AL  
Register description  
BDU: This bit is used to inhibit output registers update until both upper and lower parts are  
read. In default mode (BDU=’0’) the output registers values are updated continuosly. It is  
recommended to set BDU bit to ‘1’ if the reading is not faster than the output data rate.  
alg: This bit permits to decide between 16 bits left justified (default value) and 10 bits right  
justified representation of data coming from the device. In this last case the most significant  
bits are replaced by the bit representing the sign.  
BOOT bit is used to refresh the content of internal registers stored in the flash memory  
block. At the device power up the content of the flash memory block is transferred to the  
internal registers related to trimming functions to permit a good behavior of the device itself.  
If for any reason the content of trimming registers was changed it is sufficient to use this bit  
to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied  
inside corresponding internal registers and it is used to calibrate the device. These values  
are factory trimmed and they are different for every gyroscope. They permit a good behavior  
of the device and normally they have not to be changed. At the end of the boot process the  
BOOT bit is set again to ‘0’.  
SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire  
interface mode is selected. The data coming from the device are sent to SDO pin. In 3-wire  
interface mode output data are sent to SDA/SDI/SDO pin.  
6.3  
FILTER_CFG_REG (22h)  
Table 21. FILTER_CFG_REG register  
HP_BW1  
HP_BW0  
LP_BW2  
LP_BW1  
LP_BW0  
0 (1)  
0
0
1. 0 is the default value loaded at boot. This value must not be changed.  
Table 22. FILTER_CFG_REG description  
HP_BW(1-0)  
High pass filter pole frequency selection  
LP_BW(2-0)  
Low pass filter pole frequency selection  
Table 23. High pass filter pole -3dB frequency selection  
HP_BW[1:0]  
Pole frequency [Hz]  
00  
01  
10  
11  
1.25  
0.31  
0.15  
0.08  
Table 24. Low pass filter pole -3dB frequency selection  
LP_BW[2:0]  
Pole frequency [Hz]  
000  
001  
010  
115  
46.1  
21.3  
25/30  
Register description  
Table 24. Low pass filter pole -3dB frequency selection (continued)  
LY530AL  
LP_BW[2:0]  
Pole frequency [Hz]  
011  
100  
101  
110  
111  
10.3  
5.1  
2.5  
1.2  
0.6  
6.4  
OUTPUT_SEL_REG (23h)  
Table 25. OUTPUT_SEL_REG register  
X
X
ST_bit  
X
X
OUT2  
OUT1  
OUT0  
Table 26. OUTPUT_SEL_REG description  
When Dig_en is set to ‘1’, ST_bit enables Selft Test function. Default value: 0  
(0: no selft test activated; 1: self test enabled  
ST_bit  
OUT2-0  
Output data filtering selection  
Table 27. Filtering selection  
OUTPUT_SEL_REG[2:0]  
Filter type  
000  
001  
011  
100  
101  
111  
no filtering  
high pass  
2 x high pass  
low pass  
high pass + low pass  
2 x high pass + low pass  
Table 28. Forbidden combinations  
FILTER_CFG_REG[2:0]  
OUTPUT_SEL_REG[2:0]  
101  
101  
100  
100  
111  
111  
111  
100  
111  
101  
101  
100  
26/30  
LY530AL  
Register description  
6.5  
STATUS_REG(27h)  
Table 29. STATUS_REG(27h) register  
X(1)  
X
X
X
X
ow  
davbH  
davbL  
1. Undefined value  
Table 30. STATUS_REG(27h) description  
ow  
Digital data overrun. When ‘1’, output registers have been updated before being read.  
When this bit is ‘1’, new data is available on OUT_CONV_H (high part)  
When this bit is ‘1’, new data is available on OUT_CONV_L (low part)  
davbH  
davbL  
6.6  
6.7  
OUT_CONV_H(28h)  
Table 31. OUT_CONV_H register  
DOH7  
DOH6  
DOH5  
DOH4  
DOH3  
DOH2  
DOH1  
DOH0  
These bits are the high part of digital output expressed as 2’s complement number. For data  
alignment see alg bit in CTRL_REG(20h) (Table 20).  
OUT_CONV_L(29h)  
Table 32. OUT_CONV_L register  
DOL7  
DOL6  
DOL5  
DOL4  
DOL3  
DOL2  
DOL1  
DOL0  
These bits are the lowpart of digital output expressed as 2’s complement number. For data  
alignment see alg bit in CTRL_REG(20h) (Table 20).  
27/30  
Package information  
LY530AL  
7
Package information  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a lead-free second level interconnect. The category of  
second level interconnect is marked on the inner box label, in compliance with JEDEC  
Standard JESD97. The maximum ratings related to soldering conditions are also marked on  
®
the inner box label. ECOPACK is an ST trademark.  
®
ECOPACK specifications are available at: www.st.com.  
Figure 12. LGA-16: mechanical data and package dimensions  
A1  
A2  
A3  
C
1.46  
0.16  
1.5  
1.6  
0.057 0.059 0.063  
1.33  
0.052  
0.2  
0.3  
5
0.24 0.006 0.008 0.009  
0.012  
D1  
E1  
L
4.85  
4.85  
5.15 0.191 0.197 0.203  
5
5.15 0.191 0.197 0.203  
0.8  
3.2  
1.6  
0.031  
0.126  
0.062  
L1  
M
M1  
M2  
N
2.15 2.175 2.20 0.085 0.086 0.087  
1.625  
2.175  
2.4  
0.064  
0.086  
LGA-16 (5x5x1.6mm)  
Land Grid Array Package  
N1  
T1  
T2  
R
0.094  
0.031  
0.8  
0.475  
1.2  
0.5  
0.525 0.019 0.020 0.021  
1.6  
0.047  
0.063  
S
0.1  
0.15  
0.05  
0.1  
0.004  
0.006  
0.002  
0.004  
h
k
j
7887555A  
28/30  
LY530AL  
Revision history  
8
Revision history  
Table 33. Document revision history  
Date  
Revision  
Changes  
03-Sep-2008  
1
Initial release  
29/30  
LY530AL  
Please Read Carefully:  
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the  
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any  
time, without notice.  
All ST products are sold pursuant to ST’s terms and conditions of sale.  
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no  
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this  
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UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED  
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void  
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any  
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.  
Information in this document supersedes and replaces all information previously supplied.  
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.  
© 2008 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
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www.st.com  
30/30  
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