Application Information
The most common circuit controlled by the LM3000 is a non-
isolated, synchronous buck regulator. The buck regulator
steps down the input voltage and has a duty ratio D of:
Where η is the estimated converter efficiency.
The following is a design example selecting components for
the Typical Application Schematic of Figure 24. The circuit is
designed for two outputs of 3.3V at 8A and 1.2V at 15A from
an input voltage of 6V to 18V. This circuit is typical of a ‘brick’
module and has a height requirement of 6.5mm or less. Other
assumptions used to aid in circuit design are that the expected
load is a small microprocessor or ASIC with fast load tran-
sients, and that the type of MOSFETs used are in SO-8 or its
equivalent packages such as PowerPAK®, PQFN and LFPAK
(LFPAK-i).
Where QGD is the high-side FET Miller charge with a VDS
swing between 0 to VIN; CISS is the input capacitance of the
high-side MOSFET in its off state with VDS = VIN. α and β are
fitting coefficient numbers, which are usually between 0.5 to
1, depending on the board level parasitic inductances and re-
verse recovery of the low-side power MOSFET body diode.
Under ideal condition, setting α = β = 0.5 is a good starting
point. Other variables are defined as:
IL_VL = IOUT - 0.5 x ΔIL
IL_PK = IOUT + 0.5 x ΔIL
SWITCHING FREQUENCY
The selection of switching frequency is based on the tradeoff
between size, cost and efficiency. In general, a lower fre-
quency means larger, more expensive inductors and capac-
itors. A higher switching frequency generally results in a
smaller but less efficient solution, because the power MOS-
FET gate capacitances must be charged and discharged
more often in a given amount of time. For this application a
frequency of 500 kHz is selected. 500 kHz is a good compro-
mise between the size of the inductor and MOSFETs, tran-
sient response and efficiency. Following the equation given
for RFRQ in the Frequency Setting section, for 500 kHz oper-
ation a 42.2 kΩ 1% resistor is used.
RG_ON = 8.5 + RG_INT + RG_EXT
RG_OFF = 2.8 + RG_INT + RG_EXT
Switching loss is calculated for the high-side FET only. 8.5
and 2.8 represent the LM3000 high-side driver resistance in
the transient region. RG_INT is the gate resistance of the high-
side FET, and RG_EXT is the external gate resistance if appli-
cable. RG_EXT may be used to damp out excessive parasitic
ringing at the switch node.
MOSFETS
Selection of the power MOSFETs is governed by a tradeoff
between size, cost and efficiency. Buck regulators that use a
controller IC and discrete MOSFETs tend to be most efficient
for output currents of 4A to 20A.
For this example, the maximum drain-to-source voltage ap-
plied to either MOSFET is 18V. The maximum drive voltage
at the gate of the high-side MOSFET is 5V, and the maximum
drive voltage for the low-side MOSFET is 5V. The selected
MOSFET must be able to withstand 18V plus any ringing from
drain to source, and be able to handle at least 5V plus ringing
from gate to source. If the duty cycle of the converter is small,
then the high-side MOSFET should be selected with a low
gate charge in order to minimize switching loss whereas the
bottom MOSFET should have a low RDSONto minimize con-
duction loss.
Losses in the high-side FET can be broken down into con-
duction loss, gate charge loss and switching loss. Conduc-
tion, or I2R loss is approximately:
PCOND_HI = D x (IOUT2 x RDS(on)_HI x 1.3)
(High-side FET)
PCOND_LO = D x (IOUT2 x RDS(on)_LO x 1.3)
(Low-side FET)
In the above equations the factor 1.3 accounts for the in-
crease in MOSFET RDS(on) due to self heating. Alternatively,
the 1.3 can be ignored and the RDS(on) of the MOSFET esti-
mated using the RDS(on) vs. Temperature curves in the MOS-
FET datasheets.
For a typical input voltage of 12V and output currents of 8A
and 12A, the MOSFET selections for the design example are
HAT2168 for the high-side MOSFET and RJK0330DPB for
the low-side MOSFET.
The gate charge loss results from the current driving the gate
capacitance of the power MOSFETs, and is approximated as:
A 3Ω resistor for RCBT is added in series with the VDR regu-
lator output, as shown in Figure 24. This helps to control the
MOSFET turn-on and ringing at the switch node, without af-
fecting the MOSFET turn-off.
PDR = VIN x (QG_HI + QG_LO) x fSW
Where QG_HI and QG_LO are the total gate charge of the high-
side and low-side FETs respectively at the typical 5V driver
voltage. Gate charge loss differs from conduction and switch-
ing losses in that the majority of dissipation occurs in the
LM3000.
To improve efficiency, 3A, 40V Schottky diodes are placed
across the low-side MOSFETs. The external Schottky diodes
have a much lower forward voltage than the MOSFET body
diode, and help to minimize the loss due to the body diode
recovery characteristic.
The switching loss occurs during the brief transition period as
the FET turns on and off, during which both current and volt-
age are present in the channel of the FET. This can be
approximated as the following:
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