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LZ21N3

型号：

LZ21N3

描述：

1月2日式隔行彩色CCD传感器面积有2个140的k个像素[ 1/2-type Interline Color CCD Area Sensor with 2 140 k Pixels ]

品牌：

SHARP[ SHARP ELECTRIONIC COMPONENTS ]

页数：

19 页

PDF大小：

154 K

下载PDF手册
LZ21N3  
1/2-type Interline Color CCD Area  
Sensor with 2 140 k Pixels  
LZ21N3  
DESCRIPTION  
PIN CONNECTIONS  
The LZ21N3 is a 1/2-type (8.08 mm) solid-state  
image sensor that consists of PN photo-diodes  
and CCDs (charge-coupled devices). With  
approximately 2 140 000 pixels (1 704 horizontal x  
1 255 vertical), the sensor provides a stable high-  
resolution color image.  
20-PIN HALF-PITCH WDIP  
TOP VIEW  
OD  
GND  
OFD  
PW  
1
2
3
4
5
6
7
8
9
20 OS  
19 GND  
18 NC5  
17 NC4  
16 ØV1A  
15 ØV1B  
14 ØV2  
FEATURES  
• Optical size : 8.08 mm (aspect ratio 4 : 3)  
• Interline scan format  
ØRS  
• Square pixel  
NC1  
NC2  
ØH1  
• Number of effective pixels : 1 650 (H) x 1 250 (V)  
• Number of optical black pixels  
– Horizontal : 2 front and 52 rear  
– Vertical : 3 front and 2 rear  
• Number of dummy bits  
13 ØV3A  
12 ØV3B  
11 ØV4  
NC3  
ØH2 10  
– Horizontal : 28  
– Vertical : 2  
• Pixel pitch : 3.95 µm (H) x 3.95 µm (V)  
• Mg, G, Cy, and Ye complementary color mosaic  
filters  
(WDIP020-P-0500)  
• Supports monitoring mode  
• Low fixed-pattern noise and lag  
• No burn-in and no image distortion  
• Blooming suppression structure  
• Built-in output amplifier  
PRECAUTIONS  
• The exit pupil position of lens should be 30 to 50  
mm from the top surface of the CCD.  
• Refer to "PRECAUTIONS FOR CCD AREA  
SENSORS" for details.  
• Built-in overflow drain voltage circuit and reset  
gate voltage circuit  
• Variable electronic shutter  
• Package :  
20-pin half-pitch WDIP [Plastic]  
(WDIP020-P-0500)  
Row space : 12.20 mm  
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in  
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.  
1
LZ21N3  
PIN DESCRIPTION  
SYMBOL  
PIN NAME  
Output transistor drain  
OD  
OS  
Output signals  
ØRS  
Reset transistor clock  
Vertical shift register clock  
Horizontal shift register clock  
Overflow drain  
ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4  
ØH1, ØH2  
OFD  
PW  
P-well  
GND  
Ground  
NC  
1
, NC  
2
, NC  
3
, NC  
4, NC  
5
No connection  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Output transistor drain voltage  
Overflow drain voltage  
(TA = +25 ˚C)  
UNIT NOTE  
V
SYMBOL  
VOD  
VOFD  
VØRS  
VØV  
RATING  
0 to +15  
Internal output  
Internal output  
VPW to +15  
–0.3 to +12  
–24 to 0  
0 to +15  
–40 to +85  
–20 to +70  
V
V
1
2
Reset gate clock voltage  
Vertical shift register clock voltage  
Horizontal shift register clock voltage  
Voltage difference between P-well and vertical clock  
Voltage difference between vertical clocks  
Storage temperature  
V
V
V
VØH  
VPW-VØV  
VØV-VØV  
TSTG  
V
3
˚C  
˚C  
Ambient operating temperature  
TOPR  
NOTES :  
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is  
applied below 22 Vp-p.  
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is  
applied below 8 Vp-p.  
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be  
below 22 V.  
2
LZ21N3  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
Ambient operating temperature  
Output transistor drain voltage  
Overflow drain clock p-p level  
Ground  
SYMBOL  
MIN.  
TYP. MAX. UNIT NOTE  
TOPR  
VOD  
VØOFD  
25.0  
13.0  
19.5  
0.0  
˚C  
V
V
12.5  
18.6  
13.5  
20.9  
1
2
GND  
V
P-well voltage  
VPW  
–8.0  
VØVL  
V
VØV1AL, VØV1BL, VØV2L  
VØV3AL, VØV3BL, VØV4L  
VØV1AI, VØV1BI, VØV2I  
VØV3AI, VØV3BI, VØV4I  
VØV1AH, VØV1BH  
VØV3AH, VØV3BH  
VØH1L, VØH2L  
VØH1H, VØH2H  
VØRS  
LOW level  
–7.35 –7.0 –6.65  
0.0  
V
V
V
Vertical shift  
register clock  
INTERMEDIATE level  
HIGH level  
12.5  
13.0  
13.5  
Horizontal shift  
register clock  
LOW level  
HIGH level  
Reset gate clock p-p level  
–0.05  
4.5  
4.5  
0.0  
4.8  
4.8  
0.05  
5.5  
5.5  
V
V
V
1
fØV1A, fØV1B, fØV2  
fØV3A, fØV3B, fØV4  
fØH1, fØH2  
Vertical shift register clock frequency  
7.87  
kHz  
Horizontal shift register clock frequency  
Reset gate clock frequency  
17.94  
17.94  
MHz  
MHz  
fØRS  
NOTES :  
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.  
2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected  
to VL of V driver IC.  
* To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on PW first and then turn on other powers  
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.  
3
LZ21N3  
CHARACTERISTICS (Drive method : 1/30 s frame accumulation)  
(TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".  
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)  
PARAMETER  
Standard output voltage  
Photo response non-uniformity  
SYMBOL  
VO  
PRNU  
MIN.  
TYP. MAX. UNIT NOTE  
150  
mV  
%
2
3
10  
450  
320  
530  
400  
0.5  
0.5  
180  
–89  
mV  
mV  
mV  
mV  
mV  
dB  
%
4
5
1, 6  
1, 7  
8
9
10  
11  
Saturation output voltage  
VSAT  
Dark output voltage  
Dark signal non-uniformity  
Sensitivity  
Smear ratio  
Image lag  
VDARK  
DSNU  
R
SMR  
AI  
3.0  
2.0  
140  
–82  
1.0  
Blooming suppression ratio  
Output transistor drain current  
ABL  
IOD  
1 000  
4.0  
8.0  
mA  
NOTES :  
• Within the recommended operating conditions of VOD,  
VOFD of the internal output satisfies with ABL larger than  
1 000 times exposure of the standard exposure conditions,  
and VSAT larger than 320 mV.  
6. The average output voltage under non-exposure  
conditions.  
7. The image area is divided into 10 x 10 segments under  
non-exposure conditions. DSNU is defined by (Vdmax –  
Vdmin), where Vdmax and Vdmin are the maximum and  
minimum values of each segment's voltage respectively.  
8. The average output voltage when a 1 000 lux light  
source with a 90% reflector is imaged by a lens of F4,  
f50 mm.  
9. The sensor is exposed only in the central area of V/10  
square with a lens at F4, where V is the vertical image  
size. SMR is defined by the ratio of the output voltage  
detected during the vertical blanking period to the  
maximum output voltage in the V/10 square.  
10. The sensor is exposed at the exposure level  
corresponding to the standard conditions. AI is defined  
by the ratio of the output voltage measured at the 1st  
field during the non-exposure period to the standard  
output voltage.  
11. The sensor is exposed only in the central area of V/10  
square, where V is the vertical image size. ABL is  
defined by the ratio of the exposure at the standard  
conditions to the exposure at a point where blooming is  
observed.  
1. TA = +60 ˚C  
2. The average output voltage under uniform illumination.  
The standard exposure conditions are defined as when  
Vo is 150 mV.  
3. The image area is divided into 10 x 10 segments under  
the standard exposure conditions. Each segment's  
voltage is the average output voltage of all pixels within  
the segment. PRNU is defined by (Vmax – Vmin)/Vo,  
where Vmax and Vmin are the maximum and minimum  
values of each segment's voltage respectively.  
4. The image area is divided into 10 x 10 segments. Each  
segment's voltage is the average output voltage of all  
pixels within the segment. VSAT is the minimum  
segment's voltage under 10 times exposure of the  
standard exposure conditions. The operation of OFDC is  
high. (for still image capturing)  
5. The image area is divided into 10 x 10 segments. Each  
segment's voltage is the average output voltage of all  
pixels within the segment. VSAT is the minimum  
segment's voltage under 10 times exposure of the  
standard exposure conditions. The operation of OFDC is  
low.  
4
LZ21N3  
PIXEL STRUCTURE  
OPTICAL BLACK  
(2 PIXELS)  
OPTICAL BLACK  
(2 PIXELS)  
OPTICAL BLACK  
(52 PIXELS)  
1 650 (H) x 1 250 (V)  
1 pin  
OPTICAL BLACK  
(3 PIXELS)  
COLOR FILTER ARRAY  
(1, 1 250)  
(1 650, 1 250)  
Pin arrangement  
of the vertical  
readout clock  
V3B Ye Cy Ye Cy Ye Cy  
Ø
Ye Cy  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
ØV1B G Mg G Mg G Mg  
ØV3A Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1A G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
ØV3A Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1A G Mg G Mg G Mg  
ØV3B Ye Cy Ye Cy Ye Cy  
ØV1B G Mg G Mg G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy  
G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
Ye Cy Ye Cy  
G Mg G Mg  
(1, 1)  
(1 650, 1)  
5
LZ21N3  
TIMING CHART  
TIMING CHART EXAMPLE  
Pulse diagram in more detail is shown in figures qto tafter the next page.  
Field accumulation mode Frame accumulation Frame accumulation mode  
mode at first  
Field accumulation Field accumulation  
mode at first  
mode  
q
q'  
q
w
e
r
t
q
q'  
1
1
263  
525 1  
263  
525 1  
656  
656  
656 1  
263  
525 1  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
(at OFD shutter operation)  
OFDC  
OS  
Field accumulation mode  
Not for use  
(NOTE 1)  
Frame accumulation mode  
Not for use Field accumulation  
..  
(Number of  
vertical line)  
..  
(3, 8, 13,  
..  
..  
...  
...  
)
(3, 8, 13, ) (3, 8, 13,  
)
(1, 3, , 1247, 1249) (2, 4, , 1248, 1250)(NOTE 2)  
mode (3, 8, 13, )  
NOTES :  
1. Do not use these signals immediately after field accumulation mode is transferred to frame  
accumulation mode for still image capturing.  
2. Do not use these signals immediately after frame accumulation mode is transferred to field  
accumulation mode for monitoring image.  
* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.  
6
LZ21N3  
q VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡  
Shutter speed  
1/30 s  
257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFDC  
ØOFD  
1203  
1213  
1223  
1233  
1243  
1198  
1208  
1218  
1228  
1238  
1248  
OB1  
3
8
13 18  
YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy  
GMg YeCy GMg YeCy  
OS  
q' VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡  
Shutter speed  
1/30 s  
519 520 521 522 523 524 525  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFDC  
ØOFD  
1193  
1203  
1213  
1223  
1228  
1233  
1238  
1243  
1198  
1208  
1218  
1248  
OB1  
3
8
13 18  
GMg YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy  
GMg YeCy GMg YeCy  
OS  
7
LZ21N3  
w VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/15 s  
519 520 521 522 523 524 525  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFDC  
ØOFD  
1198  
1208  
1218  
1228  
1238  
1248  
1193  
1203  
1213  
1223  
1233  
1243  
GMg YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy GMg YeCy  
OS  
Not for use  
* Do not use the frame signals immediately after accumulation mode is transferred to frame  
accumulation mode.  
e VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡  
…
…
…
618 619 620 621 622 623 624  
655 656  
1
2
9
10 11 12 13 14 15 16 17 18 19 20 21  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
Charge swept transfer (1 368 stages)  
OFDC  
ØOFD  
OB2  
1
3
5
GMg GMg GMg  
OS  
Not for use  
* Do not use the frame signals immediately after field accumulation mode is transferred to frame  
accumulation mode.  
8
LZ21N3  
r VERTICAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡  
…
…
638 639 640 641 642 643 644 645 646  
656  
1
2
9
10 11 12 13 14 15 16 17 18 19 20 21  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
Charge swept transfer (684 stages)  
OFDC  
ØOFD  
1241  
1245  
1249  
OB1  
1243  
1247  
OB1 OB3  
2
4
OS  
GMg GMg GMg GMg GMg  
YeCy YeCy  
Not for use  
t VERTICAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/15 s  
…
640 641 642 643 644  
656  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFDC  
ØOFD  
1246  
1250  
1244  
1248  
OB2  
OS  
YeCy YeCy YeCy YeCy  
9
LZ21N3  
READOUT TIMING ¿FIELD ACCUMULATION MODE¡  
2280, 1  
228  
2280, 1  
228  
HD  
732 852  
932  
92 212  
212  
ØV1A  
ØV1B  
ØV2  
172 292  
52 252  
1012  
292  
1052 1172  
892  
252  
ØV3A  
ØV3B  
ØV4  
132 332  
972  
332  
6.7 µs  
40.9 µs (732 bits)  
(120 bits)  
6.7 µs  
58.8 µs (1 052 bits)  
(120 bits)  
* Keep over 2.2 µs when vertical transfer clock pulse is overlapping.  
e
READOUT TIMING ¿FRAME ACCUMULATION MODE¡  
2280, 1  
228  
2280, 1  
228  
732 852  
932  
92 212  
172 292  
52 252  
212  
ØV1A  
ØV1B  
1012  
292  
252  
ØV2  
892  
ØV3A  
ØV3B  
132 332  
972  
332  
ØV4  
6.7 µs  
40.9 µs (732 bits)  
(120 bits)  
r
HD2280, 1  
228  
2280, 1  
228  
212  
92 212  
172 292  
932  
ØV1A  
ØV1B  
1012  
292  
ØV2  
1052 1172  
52 252  
132 332  
252  
332  
892  
ØV3A  
ØV3B  
972  
ØV4  
6.7 µs  
(120 bits)  
58.8 µs (1 052 bits)  
* Keep over 2.2 µs when vertical transfer clock pulse is overlapping.  
10  
LZ21N3  
HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-1  
1 clk = 55.8 ns (= 1/17.9 MHz)  
52  
92  
132  
172  
212  
228 252  
292  
332  
2280, 1  
HD  
ØH1  
ØH2  
ØRS  
OS  
40 clk  
(= 2.2 µs)  
πππ1650  
OB (52)  
Double transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
Triple transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
192  
272  
OFD  
11  
LZ21N3  
HORIZONTAL TRANSFER TIMING ¿FIELD ACCUMULATION MODE¡-2  
1 clk = 55.8 ns (= 1/17.9 MHz)  
332  
372  
412  
452  
492  
532  
572  
600  
HD  
ØH1  
ØH2  
ØRS  
OS  
PRE SCAN (28)  
OB (2)  
OUTPUT (1 650) 1πππππππ  
Double transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
Triple transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFD  
12  
LZ21N3  
HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-1  
1 clk = 55.8 ns (= 1/17.9 MHz)  
2280, 1  
52  
92  
132  
172  
212  
228 252  
292  
332  
HD  
ØH1  
ØH2  
ØRS  
OS  
..  
40 clk (= 2.2 µs)  
1650  
OB (52)  
Standard transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
192  
272  
OFD  
13  
LZ21N3  
HORIZONTAL TRANSFER TIMING ¿FRAME ACCUMULATION MODE¡-2  
1 clk = 55.8 ns (= 1/17.9 MHz)  
600  
332  
372  
412  
452  
492  
532  
572  
HD  
ØH1  
ØH2  
ØRS  
OS  
PRE SCAN (28)  
OB (2)  
OUTPUT (1 650) 1πππππππ  
Standard transfer  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
OFD  
14  
LZ21N3  
CHARGE SWEPT TRANSFER TIMING ¿e¡  
621H  
1
622H 623H • • • • • 655H 656H 1H 2H 3H • • • • • 11H 12H 13H  
228  
HD  
2
42 82 122 162  
2242  
2262  
2242  
2262  
ØV1A  
ØV1B  
22 62 102 142  
42 82 122 162  
22 62 102 142  
ØV2  
2
ØV3A  
ØV3B  
ØV4  
1
2
3
4
• • • • • • •  
1366 1367 1368  
* Keep over 1.1 µs when vertical transfer clock pulse of charge swept transfer is overlapping.  
CHARGE SWEPT TRANSFER TIMING ¿r¡  
645H  
1
646H 647H • • • • • 655H 656H 1H 2H 3H • • • • • 11H 12H 13H  
228  
HD  
2
42 82 122 162  
2242  
2262  
2242  
2262  
ØV1A  
ØV1B  
22 62 102 142  
42 82 122 162  
22 62 102 142  
ØV2  
2
ØV3A  
ØV3B  
ØV4  
1
2
3
4
• • • • • • •  
682  
683  
684  
* Keep over 1.1 µs when vertical transfer clock pulse of charge swept transfer is overlapping.  
15  
LZ21N3  
SYSTEM CONFIGURATION EXAMPLE  
+
OS  
OD  
GND  
NC5  
NC4  
ØV1A  
ØV1B  
ØV2  
GND  
OFD  
PW  
ØRS  
NC1  
NC2  
ØH1  
ØV3A  
ØV3B  
ØV4  
NC3  
ØH2  
POFD  
VMb  
VL  
VOFDH  
VH3BX  
OFDX  
V2X  
+
V2  
V4  
V1X  
NC  
V3B  
V3A  
V1B  
V1A  
VMa  
VH  
VH1AX  
V3X  
VDD  
+
GND  
VH3AX  
V4X  
VH1BX  
+
16  
PACKAGES FOR CCD AND CMOS DEVICES  
PACKAGE  
(Unit : mm)  
20 WDIP (WDIP020-P-0500)  
Center of effective imaging area  
and center of package  
±0.075  
6.90  
±0.40  
0.40  
20  
11  
¬
MAX.  
Rotation error of die : ¬ = 1.0˚  
CCD  
(◊ 1 : Effective imaging area)  
(◊ 2 : Lid's size)  
1
10  
±0.10  
12.20  
±0.10  
13.00  
(◊2)  
Refractive index : nd = 1.5  
0.02  
±0.10  
13.80  
(◊1)  
A
A
Glass Lid  
CCD  
Package  
A'  
0.02  
(◊1)  
0.04  
TYP.  
TYP.  
TYP.  
±0.10  
0.25  
0.30  
0.64  
P-1.27  
A'  
+0.30  
–0  
12.20  
0.20 M  
17  
PRECAUTIONS FOR CCD AREA SENSORS  
PRECAUTIONS FOR CCD AREA SENSORS  
(In the case of plastic packages)  
1. Package Breakage  
– The leads of the package are fixed with  
package body (plastic), so stress added to a  
lead could cause a crack in the package  
body (plastic) in the jointed part of the lead.  
In order to prevent the package from being broken,  
observe the following instructions :  
1) The CCD is a precise optical component and  
the package material is ceramic or plastic.  
Therefore,  
Glass cap  
Package  
ø Take care not to drop the device when  
mounting, handling, or transporting.  
Lead  
Fixed  
ø Avoid giving a shock to the package.  
Especially when leads are fixed to the socket  
or the circuit board, small shock could break  
the package more easily than when the  
package isn’t fixed.  
Stand-off  
2) When applying force for mounting the device or  
any other purposes, fix the leads between a  
joint and a stand-off, so that no stress will be  
given to the jointed part of the lead. In addition,  
when applying force, do it at a point below the  
stand-off part.  
3) When mounting the package on the housing,  
be sure that the package is not bent.  
– If a bent package is forced into place  
between a hard plate or the like, the pack-  
age may be broken.  
4) If any damage or breakage occurs on the sur-  
face of the glass cap, its characteristics could  
deteriorate.  
(In the case of ceramic packages)  
– The leads of the package are fixed with low  
melting point glass, so stress added to a  
lead could cause a crack in the low melting  
point glass in the jointed part of the lead.  
Therefore,  
ø Do not hit the glass cap.  
ø Do not give a shock large enough to cause  
distortion.  
ø Do not scrub or scratch the glass surface.  
– Even a soft cloth or applicator, if dry, could  
cause dust to scratch the glass.  
Low melting point glass  
Lead  
2. Electrostatic Damage  
As compared with general MOS-LSI, CCD has  
lower ESD. Therefore, take the following anti-static  
measures when handling the CCD :  
Fixed  
1) Always discharge static electricity by grounding  
the human body and the instrument to be used.  
To ground the human body, provide resistance  
of about 1 M$ between the human body and  
the ground to be on the safe side.  
Stand-off  
2) When directly handling the device with the  
fingers, hold the part without leads and do not  
touch any lead.  
18  
PRECAUTIONS FOR CCD AREA SENSORS  
3) To avoid generating static electricity,  
a. do not scrub the glass surface with cloth or  
plastic.  
ø The contamination on the glass surface  
should be wiped off with a clean applicator  
soaked in Isopropyl alcohol. Wipe slowly and  
gently in one direction only.  
b. do not attach any tape or labels.  
c. do not clean the glass surface with dust-  
cleaning tape.  
– Frequently replace the applicator and do not  
use the same applicator to clean more than  
one device.  
4) When storing or transporting the device, put it in  
a container of conductive material.  
◊ Note : In most cases, dust and contamination  
are unavoidable, even before the device  
is first used. It is, therefore, recommended  
that the above procedures should be  
taken to wipe out dust and contamination  
before using the device.  
3. Dust and Contamination  
Dust or contamination on the glass surface could  
deteriorate the output characteristics or cause a  
scar. In order to minimize dust or contamination on  
the glass surface, take the following precautions :  
1) Handle the CCD in a clean environment such  
as a cleaned booth. (The cleanliness level  
should be, if possible, class 1 000 at least.)  
2) Do not touch the glass surface with the fingers.  
If dust or contamination gets on the glass  
surface, the following cleaning method is  
recommended :  
4. Other  
1) Soldering should be manually performed within  
5 seconds at 350 °C maximum at soldering iron.  
2) Avoid using or storing the CCD at high tem-  
perature or high humidity as it is a precise  
optical component. Do not give a mechanical  
shock to the CCD.  
ø Dust from static electricity should be blown  
off with an ionized air blower. For anti-  
electrostatic measures, however, ground all  
the leads on the device before blowing off  
the dust.  
3) Do not expose the device to strong light. For  
the color device, long exposure to strong light  
will fade the color of the color filters.  
19  
厂商 型号 描述 页数 下载

YAGEO

 		LZ200M0150ST [ Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 200V, 20% +Tol, 20% -Tol, 150uF, Through Hole Mount ] 1 页

YAGEO

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YAGEO

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ETC

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ETC

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YEASHIN

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EBMPAPST

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SHARP

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