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OV7141

型号：

OV7141

描述：

OV7640彩色CMOS VGA （ 640 ×480 ）的CameraChip OV7141黑白CMOS VGA （ 640 ×480 ）的CameraChip[ OV7640 Color CMOS VGA (640 x 480) CAMERACHIP OV7141 B&W CMOS VGA (640 x 480) CAMERACHIP ]

品牌：

ETC[ ETC ]

页数：

20 页

PDF大小：

291 K

下载PDF手册
Advanced Information  
Preliminary Datasheet  
mni isionTM  
O
TM  
OV7640 Color CMOS VGA (640 x 480) CAMERACHIP  
TM  
OV7141 B&W CMOS VGA (640 x 480) CAMERACHIP  
General Description  
Applications  
•
•
•
Cellular and Picture Phones  
Toys  
The OV7640 (color) and OV7141 (black and white)  
TM  
CAMERACHIPS  
are low voltage CMOS image sensors  
that provide the full functionality of a single-chip VGA  
(640 x 480) camera and image processor in a small  
footprint package. The OV7640/OV7141 provides  
full-frame, sub-sampled or windowed 8-bit images in a  
wide range of formats, controlled through OmniVision’s  
Serial Camera Control Bus (SCCB) interface.  
PC Multimedia  
Key Specifications  
Array Size 640 x 480 (VGA)  
Core 2.5VDC + 10%  
Analog 2.5VDC + 4%  
I/O 2.25V to 3.3V  
Power Supply  
This product family has an image array capable of  
operating at up to 30 frames per second (fps) with  
complete user control over image quality, formatting and  
output data transfer. All required image processing  
functions, including exposure control, gamma, white  
balance, color saturation, hue control and more, are also  
programmable through the SCCB interface. In addition,  
OmniVision CAMERACHIPs use proprietary sensor  
technology to improve image quality by reducing or  
eliminating common lighting/electrical sources of image  
contamination such as fixed pattern noise, smearing,  
blooming, etc. to produce a clean, fully stable color image.  
40 mW (30 fps, including  
Power  
Requirements  
Active  
I/O power)  
Standby 30 μW  
Temperature  
Range  
Operation -10°C to 70°C  
Stable Image 0°C to 50°C  
• YUV/YCbCr 4:2:2  
Output Formats (8-bit) • RGB 4:2:2  
• Raw RGB Data  
Lens Size 1/4"  
VGA 30 fps  
Maximum Image  
Transfer Rate  
QVGA 60 fps  
B&W 3.0 V/Lux-sec  
Sensitivity  
Color 1.12 V/Lux-sec  
S/N Ratio 46 dB  
Dynamic Range 62 dB  
Features  
Scan Mode Progressive/Interlaced  
•
High sensitivity for low-light operation  
Maximum Exposure Interval 523 x t  
Gamma Correction 0.45  
ROW  
•
•
•
2.5V operating voltage for embedded portable  
applications  
Standard Serial Camera Control Bus (SCCB)  
interface  
VGA, QVGA (sub-sampled) and Windowed outputs  
with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and  
YCbCr (4:2:2) formats  
Pixel Size 5.6 μm x 5.6 μm  
Dark Current 30 mV/s  
Well Capacity 60 Ke  
Fixed Pattern Noise < 0.03% of V  
PEAK-TO-PEAK  
Image Area 3.6 mm x 2.7 mm  
Package Dimensions 11.43 mm x 11.43 mm  
Figure 1 OV7640/OV7141 Pin Diagram  
•
Automatic image control functions including:  
Automatic Exposure Control (AEC), Automatic Gain  
Control (AGC), Automatic White Balance (AWB),  
Automatic Brightness Control (ABC), Automatic  
Band Filter (ABF) for 60Hz noise and Automatic  
Black-Level Calibration (ABLC)  
4
3
2
1
28  
27  
26  
PWDN  
NC  
5
6
25  
24  
23  
22  
21  
20  
19  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
•
Image quality controls including color saturation,  
hue, gamma, sharpness (edge enhancement),  
anti-blooming and zero smearing  
VREF  
VDD_C  
VSYNC  
HREF  
PCLK  
7
8
OV7640/OV7141  
Ordering Information  
9
10  
11  
Product  
Package  
PLCC-28  
PLCC-28  
OV7640 (Color)  
OV7141 (B&W)  
12  
13  
14  
15  
16  
17  
18  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
1
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Functional Description  
Figure 2 shows the functional block diagram of the OV7640/OV7141 image sensor. The OV7640/OV7141 includes:  
•
•
•
•
•
•
•
Image Sensor Array (640 x 480 resolution)  
Timing Generator  
Analog Processing Block  
A/D Converters  
Output Formatter  
Digital Video Port  
SCCB Interface  
Figure 2 OV7640/OV7141 Functional Block Diagram  
Analog Processing  
R
Output  
Formatter  
G
B
MUX  
MUX  
A/D  
A/D  
Gain  
WB  
Saturation  
Hue  
Data  
Formatting  
Y
Windowing  
Gamma  
Cb  
Brightness  
Cr  
Image Array  
(640 x 480)  
Control  
Registers  
Digital Video  
Port  
(To all circuits)  
Y[7:0]  
Column Sense Amps  
Timing Generator  
RESET  
PWDN  
SCCB  
Interface  
VREF  
1.0 μf  
CLK  
HREF  
PCLK  
VSYNC  
SIO_C  
SIO_D  
2
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Functional Description  
mni ision  
O
Image Sensor Array  
A/D Converters  
The OV7640/OV7141 CAMERACHIPS has an active image  
array size of 640 columns x 480 rows (307,200 pixels).  
However, the full array contains 652 columns and 486  
rows, with the extra 6 rows used for black-level calibration  
(“Optical Black”) and color interpolation information.  
Figure 3 shows a cross-section of the image sensor array.  
After the Analog Processing Block, the color channel data  
signal is fed to two 8-bit Analog-to-Digital (A/D) converters  
via the multiplexers, one for the Y/G channel and one  
shared by the CrCb/BR channels. These A/D converters  
operate at speeds up to 12MHz, and are fully  
synchronous to the pixel rate (actual conversion rate is  
related to the frame rate).  
Figure 3 Image Sensor Array  
In addition to the A/D conversion, this block also has the  
following functions:  
Microlens  
•
•
•
Digital Black-Level Calibration (BLC)  
Optional U/V channel delay  
Additional A/D range controls  
Color Filter  
In general, the combination of the A/D Range Multiplier  
and A/D Range Control sets the A/D range and maximum  
value to allow the user to adjust the final image brightness  
as a function of the individual application.  
Photo Diode  
Timing Generator  
In general, the timing generator controls these functions:  
Output Formatter  
•
Array control and frame generation (VGA and QVGA  
outputs)  
This block controls all output and data formatting required  
prior to sending the image out.  
•
•
•
•
Internal timing signal generation and distribution  
Frame rate timing  
Automatic Exposure Control (AEC)  
External timing outputs (VSYNC, HREF and PCLK)  
Digital Video Port  
These two bits increase I / I drive current and can be  
OL OH  
adjusted as a function of the customer’s loading:  
Analog Processing Block  
This block performs all analog image functions including:  
SCCB Interface  
•
•
•
Automatic Gain Control (AGC)  
Automatic White Balance (AWB)  
Image quality controls including:  
– Color saturation  
The Serial Camera Control Bus (SCCB) interface controls  
the CAMERACHIP operation. Refer to OmniVision  
Technologies Serial Camera Control Bus (SCCB)  
Specification for detailed usage of the serial control port.  
– Hue  
– Gamma  
– Sharpness (edge enhancement)  
– Anti-blooming  
– Zero smearing  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
3
OV7640/OV7141  
Pin Description  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Table 1  
Pin Description  
Pin Number  
Name  
Pin Type  
Function/Description  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VSS_A  
VDD_A  
NC  
Ground  
Analog ground  
Analog VDD  
V
DD  
—
No connection  
No connection  
NC  
—
Input  
—
PWDN  
NC  
Sets device to power down standby mode  
No connection  
VREF  
VDD_C  
VSYNC  
HREF  
PCLK  
VDD_IO  
CLK  
V
Internal voltage reference (2.3V). Connect to ground through 1μF capacitor  
Core VDD  
REF  
V
DD  
Output  
Output  
Output  
Vertical sync output  
HREF output  
Pixel clock output  
V
I/O VDD  
DD  
Input  
—
External clock  
NC  
No connection  
RESET  
NC  
Input  
—
Clears all registers and resets them to their default values.  
No connection  
VSS_D  
Y7  
Ground  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
I/O  
Digital ground  
Digital video output bit[7]  
Digital video output bit[6]  
Digital video output bit[5]  
Digital video output bit[4]  
Digital video output bit[3]  
Digital video output bit[2]  
Digital video output bit[1]  
Digital video output bit[0]  
SCCB serial interface clock  
SCCB serial interface data I/O  
No connection  
Y6  
Y5  
Y4  
Y3  
Y2  
Y1  
Y0  
SIO_C  
SIO_D  
NC  
—
4
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Electrical Characteristics  
mni ision  
O
Electrical Characteristics  
Table 2  
Absolute Maximum Ratings  
Ambient Storage Temperature  
-40ºC to +125ºC  
V
V
V
3V  
DD-A  
DD-C  
DD-IO  
Supply Voltages (with respect to Ground)  
3V  
4V  
All Input/Output Voltages (with respect to Ground)  
Lead Temperature, Surface-mount process  
ESD Rating, Human Body model  
-0.3V to VDD_IO+1V  
+230ºC  
2000V  
NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may  
result in permanent device damage.  
Table 3  
Symbol  
DC Characteristics (0°C < T < 70°C)  
A
Parameter  
DC supply voltage – Analog  
DC supply voltage – Core  
DC supply voltage – I/O  
Active (Operating) Current  
Standby Current  
Condition  
Min  
2.40  
2.25  
2.25  
Typ  
2.5  
2.5  
—
Max  
2.60  
2.75  
3.3  
Unit  
V
V
V
V
—
—
DD-A  
V
DD-C  
—
V
DD-IO  
a
b
I
I
I
See Note  
15  
1
mA  
mA  
μA  
V
DDA  
DDS-SCCB  
DDS-PWDN  
See Note  
CMOS  
Standby Current  
10  
V
Input voltage HIGH  
0.7 x V  
IH  
IL  
DD-IO  
DD-IO  
V
Input voltage LOW  
0.3 x V  
V
DD-IO  
DD-IO  
CMOS  
OH OL  
V
V
Output voltage HIGH  
0.9 x V  
8
V
OH  
OL  
(I / I  
)
Output voltage LOW  
Output current HIGH  
0.1 x V  
V
c
I
I
I
See Note  
mA  
mA  
μA  
OH  
Output current LOW  
15  
OL  
L
Input/Output Leakage  
GND to V  
1
DD-IO  
a.  
VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V  
I
DDA = ¦{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps, no I/O loading  
b.  
c.  
VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V  
DDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby  
Standard Output Loading = 25pF, 1.2K: to 3V  
I
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
5
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Table 4  
Symbol  
Functional Characteristics  
Functional and AC Characteristics (0°C < T < 70°C)  
A
Parameter  
Min  
Typ  
Max  
Unit  
A/D  
A/D  
Differential Non-Linearity  
+ 1/2  
+ 1  
LSB  
LSB  
dB  
Integral Non-Linearity  
Range  
AGC  
21  
12  
Red/Blue Adjustment Range  
dB  
Inputs (PWDN, CLK, RESET)  
Input Clock Frequency  
10  
100  
45  
24  
42  
50  
27  
37  
55  
1
MHz  
ns  
f
t
t
t
t
CLK  
Input Clock Period  
CLK  
Clock Duty Cycle  
%
CLK:DC  
S:RESET  
S:REG  
Setting time after software/hardware reset  
Settling time for register change (10 frames required)  
ms  
ms  
300  
SCCB (SIO_C and SIO_D - see Figure 4)  
Clock Frequency  
400  
900  
KHz  
μs  
ns  
ns  
μs  
ns  
ns  
μs  
ns  
ns  
ns  
ns  
f
t
t
t
t
t
t
t
t
t
t
t
SIO_C  
Clock Low Period  
1.3  
600  
100  
1.3  
600  
600  
0
LOW  
Clock High Period  
HIGH  
SIO_C low to Data Out valid  
Bus free time before new START  
START condition Hold time  
START condition Setup time  
Data-in Hold time  
AA  
BUF  
HD:STA  
SU:STA  
HD:DAT  
SU:DAT  
SU:STO  
Data-in Setup time  
100  
600  
STOP condition Setup time  
SCCB Rise/Fall times  
Data-out Hold time  
300  
5
t
R, F  
50  
DH  
Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 5, Figure 6, and Figure 7)  
PCLK[p] to Data-out Valid  
Y[7:0] Setup time  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
PDV  
15  
8
SU  
Y[7:0] Hold time  
HD  
PCLK[p] to HREF[n]  
PCLK[p] to HREF[p]  
0
5
5
PHH  
PHL  
0
xꢀꢀV  
:
V
= V  
= 2.5V, V  
= 3.3V  
DD  
DD-A  
DD-C  
DD-IO  
xꢀꢀRise/Fall Times: I/O:  
5ns, Maximum  
SCCB: 300ns, Maximum  
AC  
Conditions:  
xꢀꢀInput Capacitance: 10pf  
xꢀꢀOutput Loading: 25pF, 1.2K: to 3V  
xꢀꢀf 24MHz  
:
CLK  
6
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Timing Specifications  
mni ision  
O
Timing Specifications  
Figure 4 SCCB Timing Diagram  
tF  
tR  
tHIGH  
tLOW  
SIO_C  
tHD:STA  
tHD:DAT  
tSU:DAT  
tSU:STA  
tSU:STO  
SIO_D  
IN  
tBUF  
tAA  
tDH  
SIO_D  
OUT  
Figure 5 Row Output Timing Diagram  
tPCLK  
PCLK  
tPHL  
tPHL  
(Row Data)  
HREF  
tSU  
tHD  
Last Byte First Byte  
tPDV  
Last Byte  
Y[7:0]  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
7
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Figure 6 VGA Frame Timing Diagram  
525 tROW  
VSYNC  
3 tROW  
11 tROW  
31 tROW  
764 tPCLK  
HREF  
Y[7:0]  
640 tPCLK  
124 tPCLK  
(Invalid Data)  
(Invalid Data)  
Row 0  
Row 1  
Row 2  
Last Row  
Figure 7 QVGA Frame Timing Diagram  
262.5 t ROW  
VSYNC  
3 tROW  
9 tROW  
10.5 tROW  
382 tPCLK  
HREF  
Y[7:0]  
320 tPCLK  
62 tPCLK  
(Invalid Data)  
(Invalid Data)  
Row 0  
Row 1  
Row 2  
Last Row  
Note: As the RGB, YUV and YCbCr formats use the Bayer pattern for interpolation, the first row transferred out on the Y[7:0]  
bus will be invalid, as there is no row above Row #1 to provide the 'pair data' required. Because of this, the OV7640  
does not enable the HREF signal during the first row read (shown above in the 'invalid data' zone).  
8
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Timing Specifications  
mni ision  
O
Figure 8 RGB 565 Output Timing Diagram  
tPCLK  
PCLK  
tPHL  
tPHL  
(Row Data)  
HREF  
tSU  
tHD  
Last Byte First Byte  
tPDV  
Last Byte  
Y[7:0]  
First Byte  
Second Byte  
Y[7]  
R4  
G2  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
G0  
B4  
R0  
G5  
G3  
B0  
Figure 9 RGB 555 Output Timing Diagram  
tPCLK  
PCLK  
tPHL  
tPHL  
(Row Data)  
HREF  
tSU  
tHD  
Last Byte First Byte  
tPDV  
Last Byte  
Y[7:0]  
First Byte  
Second Byte  
X
G2  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
Y[7]  
Y[6]  
Y[5]  
Y[4]  
Y[3]  
Y[2]  
Y[1]  
Y[0]  
R4  
G0  
B4  
R0  
G4  
G3  
B0  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
9
OV7640/OV7141  
Register Set  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Table 5 provides a list and description of the Device Control registers contained in the OV7640/OV7141. For all register  
Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7640/OV7141 are 42 for write and  
43 for read.  
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
AGC – Gain control gain setting  
00  
GAIN  
00  
RW  
• Range: [00] to [FF]  
AWB – Blue channel gain setting  
• Range: [00] to [FF]  
01  
02  
BLUE  
RED  
80  
RW  
RW  
Note: This function is not available on the B&W OV7141.  
AWB – Red channel gain setting  
• Range: [00] to [FF]  
80  
84  
Note: This function is not available on the B&W OV7141.  
Image Format – Color saturation value  
Bit[7:4]: Saturation value  
•
Range: [0] to [F]  
03  
04  
SAT  
RW  
RW  
Bit[3:0]: Reserved  
Note: This function is not available on the B&W OV7141.  
Image Format – Color hue control  
Bit[7:6]: Reserved  
Bit[5]:  
Hue Enable  
HUE  
34  
Bit[4:0]: Hue setting  
Note: This function is not available on the B&W OV7141.  
AWB – Red/Blue Pre-Amplifier gain setting  
Bit[7:4]: Red channel pre-amplifier gain setting  
•
Range: [0] to [F]  
05  
06  
CWF  
BRT  
3E  
80  
RW  
RW  
Bit[3:0]: Blue channel pre-amplifier gain setting  
Range: [0] to [F]  
•
Note: This function is not available on the B&W OV7141.  
ABC – Brightness setting  
• Range: [00] to [FF]  
07-09  
0A  
RSVD  
PID  
XX  
76  
48  
XX  
41  
–
R
Reserved  
Product ID number (Read only)  
Product version number (Read only)  
Reserved  
0B  
VER  
R
0C-0F  
10  
RSVD  
AECH  
–
RW  
Exposure Value  
10  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Register Set  
mni ision  
O
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
Data Format and Internal Clock  
Bit[7:6]: Data Format – HSYNC/VSYNC Polarity  
00: HSYNC = NEG VSYNC = POS  
01: HSYNC = NEG VSYNC = NEG  
10: HSYNC = POS VSYNC = POS  
11: HSYNC = POS VSYNC = POS  
11  
CLKRC  
00  
RW  
POS  
NEG  
Bit[5:0]: Internal Clock Pre-Scalar  
•
Range: [0 0000] to [F FFFF]  
Common Control A  
Bit[7]:  
SCCB – Register Reset  
0: No change  
1: Reset all registers to default values  
Output Format – Mirror Image Enable  
Reserved  
Data Format – YUV formatting  
0: Y U Y V Y U Y V  
Bit[6]:  
Bit[5]:  
Bit[4]:  
12  
COMA  
14  
RW  
1: U Y V Y U Y V Y (default)  
Output Format – Output Channel Select A  
0: YUV/YCbCr  
1: RGB/Raw RGB  
AWB – Enable  
Bit[3]:  
Bit[2]:  
Bit[1:0]: Reserved  
Note: This function is not available on the B&W OV7141.  
Common Control B  
Bit[7:5]: Reserved  
Bit[4]:  
Bit[3]:  
Bit[2]:  
Bit[1]:  
Bit[0]:  
Data Format – ITU-656 Format Enable  
Reserved  
SCCB – Tri-State Enable – Y[7:0]  
AGC – Enable  
13  
COMB  
A3  
RW  
AEC – Enable  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
11  
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
Common Control C  
Bit[7:6]: Reserved  
Bit[5]:  
Output Format – Resolution  
0: VGA (640x480)  
1: QVGA (320x240)  
Reserved  
Data Format – HREF Polarity  
0: HREF Positive  
Bit[4]:  
Bit[3]:  
1: HREF Negative  
14  
COMC  
04  
RW  
POS  
NEG  
Bit[2:0]: Reserved  
Common Control D  
Bit[7]:  
Data Format – Output Flag Bit Disable  
0: Frame = 254 data bits (00/FF = Reserved flag bits)  
1: Frame = 256 data bits  
Bit[6]:  
Data Format – Y[7:0]-PCLK Reference Edge  
0: Y[7:0] data out on PCLK falling edge  
1: Y[7:0] data out on PCLK rising edge  
15  
COMD  
00  
RW  
Bit[5:1]: Reserved  
Bit[0]: Data Format – UV Sequence Exchange  
0: V Y U Y V Y U Y  
1: U Y V Y U Y V Y  
Note: Bit[0] is not programmable on the B&W OV7141.  
16  
17  
18  
19  
1A  
RSVD  
HSTART  
HSTOP  
VSTRT  
VSTOP  
XX  
1A  
BA  
03  
–
Reserved  
RW  
RW  
RW  
RW  
Output Format – Horizontal Frame (HREF Column) Start  
Output Format – Horizontal Frame (HREF Column) Stop  
Output Format – Vertical Frame (Row) Start  
F3  
Output Format – Vertical Frame (Row) Stop  
Data Format – Pixel Delay Select  
(Delays timing of the Y[7:0] data relative to HREF in pixel units)  
1B  
PSHFT  
00  
RW  
• Range: [00] (No delay) to [FF] (256 pixel delay)  
Manufacturer ID Byte – High (Read only = 0x7F)  
Manufacturer ID Byte – Low (Read only = 0xA2)  
Reserved  
1C  
1D  
1E  
MIDH  
MIDL  
RSVD  
7F  
A2  
XX  
R
R
–
12  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Register Set  
mni ision  
O
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
Output Format – Format Control  
Bit[7:5]: Reserved  
Bit[4]:  
Output Format – RGB:565 Enable  
Note: Bit[4] is not programmable on the B&W OV7141.  
1F  
FACT  
01  
RW  
Bit[3]:  
Bit[2]:  
Reserved  
Output Format – RGB:555 Enable  
Note: Bit[2] is not programmable on the B&W OV7141.  
Bit[1:0]: Reserved  
Common Control E  
Bit[7]:  
Bit[6]:  
Bit[5]:  
Bit[4]:  
Reserved  
AEC – Digital Averaging Enable  
Reserved  
20  
COME  
C0  
RW  
Image Quality – Edge Enhancement Enable  
Bit[3:1]: Reserved  
Bit[0]:  
Y[7:0] 2X I / I Enable  
OL OH  
21-23  
24  
RSVD  
AEW  
AEB  
XX  
10  
–
Reserved  
RW  
RW  
AGC/AEC – Stable Operating Region – Upper Limit  
AGC/AEC – Stable Operating Region – Lower Limit  
25  
8A  
Common Control F  
Bit[7:3]: Reserved  
Bit[2]:  
Data Format – Output Data MSB/LSB Swap Enable  
26  
COMF  
A2  
RW  
RW  
(LSB o MSB (Y[7]) and MSB o LSB (Y[0])  
Bit[1:0]: Reserved  
Common Control G  
Bit[7:5]: Reserved  
Bit[4]:  
Color Matrix – RGB Crosstalk Compensation Enable  
(Used to increase each color filter’s efficiency)  
Note: Bit[4] is not programmable on the B&W OV7141.  
Bit[3:2]: Reserved  
27  
COMG  
E2  
Bit[1]:  
Data Format – Output Full Range Enable  
0: Output Range = [10] to [F0] (224 bits)  
1: Output Range = [01] to [FE] (254/256 bits)  
Reserved  
Bit[0]:  
Common Control H  
Bit[7]:  
Bit[6]:  
Bit[5]:  
Output Format – RGB Output Select  
0: RGB  
1: Raw RGB  
Device Select  
0: OV7640  
28  
COMH  
20  
RW  
1: OV7141  
Output Format – Scan Select  
0: Interlaced  
1: Progressive  
Bit[4:0]: Reserved  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
13  
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
Common Control I  
Bit[7:2]: Reserved  
29  
COMI  
00  
R
Bit[1:0]: Device Version (Read-only)  
Output Format – Frame Rate Adjust High  
Bit[7]:  
Data Format – Frame Rate Adjust Enable  
Bit[6:5]: Data Format – Frame Rate Adjust Setting MSB  
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]  
A/D – UV Channel ‘2 Pixel Delay’ Enable  
2A  
FRARH  
00  
RW  
Bit[4]:  
Note: Bit[4] is not programmable on the B&W OV7141.  
Bit[3:0]: Reserved  
Data Format – Frame Rate Adjust Setting LSB  
2B  
2C  
FRARL  
RSVD  
00  
RW  
–
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]  
XX  
Reserved  
Common Control J  
Bit[7:3]: Reserved  
2D  
COMJ  
81  
RW  
Bit[2]:  
AEC – Band Filter Enable  
Bit[1:0]: Reserved  
2E-5F  
60  
RSVD  
SPCB  
XX  
06  
–
Reserved  
Signal Process Control B  
RW  
Bit[7]:  
AGC – 1.5x Multiplier (Pre-amplifier) Enable  
Bit[6:0]: Reserved  
61-6B  
6C  
RSVD  
RMCO  
XX  
11  
–
Reserved  
Color Matrix – RGB Crosstalk Compensation – R Channel  
RW  
Note: This function is not available on the B&W OV7141.  
Color Matrix – RGB Crosstalk Compensation – G Channel  
6D  
GMCO  
01  
RW  
Note: This function is not available on the B&W OV7141.  
Color Matrix – RGB Crosstalk Compensation– B Channel  
6E  
BMCO  
RSVD  
06  
RW  
–
Note: This function is not available on the B&W OV7141.  
Reserved  
6F-70  
XX  
Common Mode Control L  
Bit[7]:  
Bit[6]:  
Bit[5]:  
Bit[4]:  
Reserved  
Data Format – PCLK output gated by HREF Enable  
Data Format – Output HSYNC on HREF Pin Enable  
Reserved  
71  
72  
COML  
00  
10  
RW  
RW  
Bit[3:2]: Data Format – HSYNC Rising Edge Delay MSB  
Bit[1:0]: Data Format – HSYNC Falling Edge Delay MSB  
Data Format – HSYNC Rising Edge Delay LSB  
HSDYR  
HSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0]  
• Range 000 to 762 pixel delays  
14  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Register Set  
mni ision  
O
Table 5  
SCCB Register List  
Address Register  
Default  
(Hex)  
(Hex)  
Name  
R/W  
Description  
Data Format – HSYNC Falling Edge Delay LSB  
73  
HSDYF  
50  
20  
RW  
HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]  
• Range 000 to 762 pixel delays  
Common Mode Control M  
Bit[7]:  
Reserved  
Bit[6:5]: AGC – Maximum Gain Select  
00: +6 dB  
74  
COMM  
RW  
01: +12 dB  
10: +6 dB  
11: +18 dB  
Bit[4:0]: Reserved  
Common Mode Control N  
75  
76  
COMN  
COMO  
02  
00  
RW  
RW  
Bit[7]:  
Bit[6:0]: Reserved  
Output Format – Vertical Flip Enable  
Common Mode Control O  
Bit[7:6]: Reserved  
Bit[5]:  
Bit[4:3]: Reserved  
Standby Mode Enable  
Bit[2]:  
SCCB – Tri-State Enable – VSYNC, HREF and PCLK  
Bit[1:0]: Reserved  
77-7D  
7E  
RSVD  
AVGY  
XX  
00  
–
Reserved  
AEC – Digital Y/G Channel Average  
(Automatically updated by AGC/AEC, user can only read the values)  
RW  
AEC – Digital R/V Channel Average  
(Automatically updated by AGC/AEC, user can only read the values)  
7F  
80  
AVGR  
AVGB  
00  
00  
RW  
RW  
Note: This function is not available on the B&W OV7141.  
AEC – Digital B/U Channel Average  
(Automatically updated by AGC/AEC, user can only read the values)  
Note: This function is not available on the B&W OV7141.  
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
15  
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
Package Specifications  
The OV7640/OV7141 uses a 28-pin plastic package. Refer to Figure 10 for package information, Table 6 for package  
dimensions, and Figure 11 for the array center on the chip.  
Figure 10 OV7640OV7141 Plastic Package Specifications  
.093 .004  
.450 SQ .004  
.350 SQ .006  
.042 .002  
.028 .002  
.300 .004  
.075 .004  
.050 TYP  
.275 SQ .004  
.050 .004  
5
11  
8
7
5
11  
12  
4
.012 x 45o  
12  
4
.022 .002  
9
6
.001 to .005 TYP  
Pin 1  
Index  
.010 x 45o Chamfer  
Pin 1 Index  
.406  
.004  
1
1
1
28  
28  
28  
20  
23  
18  
26  
18  
26  
19  
25  
21  
19  
22  
25  
.009 R REF  
TYP  
.035  
MIN.  
.025 .003  
TYP  
.085  
TYP  
.028 .002  
(Metallized)  
Table 6  
OV7640/OV7141 Plastic Package Dimensions  
Dimensions  
Millimeters (mm)  
11.43 + 0.10 SQ  
2.35 + 0.1  
Inches (in.)  
Package Size  
Package Height  
Substrate Height  
Cavity Size  
.450 + .004 SQ  
.093 + .004  
.028 + .002  
.275 + .004 SQ  
.042 + .002  
.025 x .085  
0.70 + 0.05  
7.00 + 0.10 SQ  
1.07 + 0.05  
Castellation Height  
Pin #1 Pad Size  
0.64 x 2.16  
Pad Size  
0.64 x 1.27  
.025 x .050  
Pad Pitch  
1.27 + 0.10  
.050 + .004  
.075 + .004  
.300 + .004  
.406 + .004 SQ  
.022 + .002  
Package Edge to First Lead Center  
End-to-End Pad Center-Center  
Glass Size  
1.90 + 0.10  
7.62 + 0.10  
10.30 + 0.10 SQ  
0.55 + 0.05  
Glass Height  
16  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Package Specifications  
mni ision  
O
Sensor Array Center  
Figure 11 OV7640/OV7141 Sensor Array Center  
Pin 1  
3.6512 mm  
Array Center  
(0.2273, 0.1222)  
2.7328 mm  
Die Y-Centerline  
Image Array  
OV7640/OV7141 Die  
Die X-Centerline  
Positional Tolerances  
Die shift (x,y) = 0.15 mm (6 mils) max.  
Die tilt = 1 degrees max.  
Die rotation = 3 degrees max.  
Due to the lens inversion, in order for the image to be right-side up, the OV7640/OV7140  
must be mounted Pin 1 down.  
NOTES:  
Picture is for reference only, not to scale.  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
17  
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
IR Reflow Ramp Rate Requirements  
Figure 12 IR Reflow Ramp Rate Requirements  
Typical Dwell Time = 10Sec  
230oC  
220oC  
o
Maximum Dwell Time > 215 = 30Sec  
210oC  
200oC  
190oC  
180oC  
170oC  
160oC  
150oC  
140oC  
130oC  
o
Ramp Rate: 50/minute  
o
Ramp Rate: 10/minute  
25oC  
60S  
120S  
180S  
240S  
Note:  
All temperatures = 10oC  
All times show the fastest allowable ramp rate  
18  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
Package Specifications  
mni ision  
O
Note:  
• All information shown herein is current as of the revision and publication date. Please refer  
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all  
documentation.  
• OmniVision Technologies, Inc. reserves the right to make changes to their products or to  
discontinue any product or service without further notice (It is advisable to obtain current product  
documentation prior to placing orders).  
• Reproduction of information in OmniVision product documentation and specifications is  
permissible only if reproduction is without alteration and is accompanied by all associated  
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible  
or liable for any information reproduced.  
• This document is provided with no warranties whatsoever, including any warranty of  
merchantability, non-infringement, fitness for any particular purpose, or any warranty  
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision  
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary  
rights, relating to use of information in this document. No license, expressed or implied, by  
estoppels or otherwise, to any intellectual property rights is granted herein.  
• ‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade,  
product or service names referenced in this release may be trademarks or registered trademarks of  
their respective holders. Third-party brands, names, and trademarks are the property of their  
respective owners.  
For further information, please feel free to contact OmniVision at info@ovt.com.  
OmniVision Technologies, Inc.  
Sunnyvale, CA USA  
(408) 733-3030  
Version 1.4, March 6, 2003  
Proprietary to OmniVision Technologies  
19  
OV7640/OV7141  
CMOS VGA (640 x 480) CAMERACHIP™  
mni ision  
O
20  
Proprietary to OmniVision Technologies  
Version 1.4, March 6, 2003  
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