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OV09121-C00A

型号:

OV09121-C00A

描述:

OV9625彩色CMOS SXGA ( 1.3兆像素)的CameraChip OV9121黑白CMOS SXGA ( 1.3兆像素)的CameraChip[ OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP ]

品牌:

ETC[ ETC ]

页数:

30 页

PDF大小:

362 K

Advanced Information  
Preliminary Datasheet  
mni isionTM  
O
TM  
OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP  
OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP  
TM  
General Description  
Applications  
Digital still cameras  
PC camera/dual mode  
Video conference applications  
Machine vision  
Security cameras  
Biometrics  
The OV9625 (color) and OV9121 (black and white) are  
high-performance 1.3 mega-pixel CAMERACHIPS  
digital still image and video camera products.  
TM  
for  
Both devices incorporate a 1280 x 1024 (SXGA) image  
array and an on-chip 10-bit A/D converter capable of  
operating at up to 15 frames per second (fps) at full  
resolution and an improved micro lens design to decrease  
shading. Proprietary sensor technology utilizes advanced  
algorithms to cancel Fixed Pattern Noise (FPN), eliminate  
smearing, and drastically reduce blooming. The control  
registers allow for flexible control of timing, polarity, and  
CameraChip operation, which, in turn, allows the engineer  
a great deal of freedom in product design.  
Key Specifications  
SXGA 1280 x 1024  
Array Size  
VGA 640 x 480  
Core 2.5VDC + 10%  
Analog 3.3VDC + 10%  
I/O 3.3VDC + 10%  
Active < 50 mA  
Power Supply  
Power  
Requirements  
Standby < 10 µA  
Output Formats (10-bit) Raw RGB Data  
Lens Size 1/2"  
Features  
Max. Image  
SXGA 15 fps  
VGA 30 fps  
Optical Black Level Calibration (BLC)  
Transfer Rate  
Improved micro lens design to decrease shading  
Video or snapshot operations  
Programmable/Auto Exposure and Gain Control  
Programmable/Auto White Balance Control  
Horizontal and vertical sub-sampling (4:2 and 4:2)  
Programmable image windowing  
Variable frame rate control  
On-chip R/G/B channel and luminance average  
counter  
Sensitivity 1.0 V/Lux-sec  
S/N Ratio 54 dB  
Dynamic Range 60 dB (due to ADC limitations)  
Scan Mode Progressive  
Gamma Correction N/A  
SXGA Up to 1050:1  
VGA Up to 500:1  
Electronics  
Exposure  
Pixel Size 5.2 µm x 5.2 µm  
Dark Current 28 mV/s  
Fixed Pattern Noise < 0.03% of V  
PEAK-TO-PEAK  
Image Area 6.66 mm x 5.32 mm  
Package Dimensions .560 in. x .560 in.  
Internal/External frame synchronization  
SCCB slave interface  
Power-on reset and power-down mode  
Figure 1 OV9625/OV9121 Pin Diagram  
Ordering Information  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
PCLK 31  
D5 32  
18 ASUB  
17 AGND  
16 AVDD  
15 VcCHG  
14 FSIN  
Product  
Package  
D6 33  
OV09625-C00A (Color, SXGA,  
VGA)  
CLCC-48  
D7 34  
D8 35  
OV09121-C00A (B&W with  
microlens, SXGA, VGA)  
D9 36  
13 VGA  
CLCC-48  
OV9625/OV9121  
DOVDD 37  
DOGND 38  
HREF 39  
CHSYNC 40  
VSYNC 41  
NC 42  
12 EXPSTB  
11 SCCB_E  
10 RESET  
9
8
7
NC  
FREX  
PWDN  
43  
44  
45  
46  
47  
48  
1
2
3
4
5
6
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
1
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Functional Description  
Figure 2 shows the functional block diagram of the OV9625/OV9121 image sensor. The OV9625/OV9121 includes:  
Image Sensor Array (1280 x 1024 resolution)  
Gain Control  
Channel Balance  
10-Bit Analog-to-Digital Converter  
Black Level Compensation  
SCCB Interface  
Digital Video Port  
Timing Generator  
Figure 2 Functional Block Diagram  
D[9:0]  
PCLK  
Digital  
Video  
Port  
Channel  
Balance  
10-Bit  
A/D  
Black Level  
Compensation  
AMP  
HREF  
Column Sense Amps  
HSYNC  
VSYNC  
Image Array  
Gain  
(1312 x 1036)  
Control  
Balance  
Control  
Control  
Register  
Bank  
SCCB Slave  
Interface  
PLL  
Timing Generator and Control Logic  
XCLK  
RESET  
PWDN  
FSI  
VGA  
FREX  
EXPSTB SIO_C SIO_D SCCB_E  
2
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Functional Description  
mni ision  
O
Image Sensor Array  
10-Bit Analog-to-Digital Converter  
The OV9625/OV9121 sensor is a 1/2-inch format CMOS  
imaging device. The sensor contains 1,359,232 pixels.  
Figure 3 shows the active regions of sensor array.  
The balanced signal then will be digitized by the on-chip  
10-bit ADC. It can operate at up to 12 MHz, and is fully  
synchronous to the pixel clock. The actual conversion rate  
is determined by the frame rate.  
Figure 3 Sensor Array Region  
Column  
R
Black Level Compensation  
o
w
0
1
2
3
4
5
6
7
8
9
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
Dummy  
Dummy  
Dummy  
Dummy  
After the pixel data has been digitized, black level  
calibration can be performed before the data is output.  
The black level calibration block subtracts the average  
signal level of optical black pixels to compensate for the  
dark current in the pixel output. Black level calibration can  
be disabled by the user.  
Optical  
Black  
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
Dummy  
Dummy  
Dummy  
Dummy  
10  
11  
Windowing  
1024  
Active  
Lines  
OV9625/OV9121 allows the user to define window size or  
region of interest (ROI), as required by the application.  
Window size setting (in pixels) ranges from 2 x 4 to  
1280 x 1024 (SXGA) or 2 x 2 to 640 x 480 (VGA), and can  
be anywhere inside the 1312 x 1036 boundary. Note that  
modifying window size or window position does not alter  
the frame or pixel rate. The windowing control merely  
alters the assertion of the HREF signal to be consistent  
with the programmed horizontal and vertical ROI. The  
default window size is 1280 x 1024. See Figure 4 and  
registers HREFST, HREFEND, VSTRT, VEND, and  
COMM for details. The maximum output window size is  
1292 columns by 1024 rows.  
1032  
1033  
1034  
1035  
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
B
G
B
G
G
R
G
R
Dummy  
Dummy  
The color filters are Bayer pattern. The primary color  
BG/GR array is arranged in line-alternating fashion. Of the  
1,359,232 pixels, 1,310,720 are active. The other pixels  
are used for black level calibration and interpolation.  
The sensor array design is based on a field integration  
read-out system with line-by-line transfer and an  
electronic shutter with a synchronous pixel read-out  
scheme.  
Note that after writing to register COMH (0x12) to change  
the sensor mode, registers related to the sensor’s  
cropping window will be reset back to its default value.  
Gain Control  
When the column sample/hold circuit has sampled one  
row of pixels, the pixel data will shift out one-by-one into  
an analog amplifier. The amplifier gain can either be  
programmed by the user or controlled by the internal  
automatic gain control circuit (AGC). The gain adjustment  
range is 0-24 dB.  
Figure 4 Windowing  
Column  
Start  
Column  
End  
HREF  
Column  
R
o
w
Channel Balance  
Row Start  
Row End  
The amplified signals are then balanced with a channel  
balance block. In this block, Red/Blue channel gain is  
increased or decreased to match Green channel  
luminance level and gamma correction is performed. The  
adjustment range is 54 dB. This function can be done  
manually by the user or with the internal automatic white  
balance controller (AWB).  
Display  
Window  
Sensor Array  
Boundary  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
3
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Sub-sampling Mode  
Slave Operation Mode  
Default resolution for the OV9625/OV9121 is 1280 x 1024  
pixels, with all active pixels being output (see Figure 5).  
The OV9625/OV9121 can be programmed to output in  
640 x 480 (VGA) sized images for applications where  
higher resolution image capture is not required.  
The OV9625/OV9121 can be programmed to operate in  
slave mode (default is master mode).  
When used as a slave device, the OV9625/OV9121  
changes the HSYNC and VSYNC outputs to input pins for  
use as horizontal and vertical synchronization input  
triggers supplied by the master device. The master device  
must provide the following signals:  
Figure 5 Pixel Array  
1.  
2.  
3.  
System clock MCLK to XCLK1 pin  
Column #  
Horizontal sync MHSYNC to CHSYNC pin  
Vertical frame sync MVSYNC to VSYNC pin  
i
i+1 i+2 i+3 i+4 i+5 i+6 i+7 i+8 i+9  
n
B
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
n+1  
G
B
G
B
G
B
G
See Figure 7 for slave mode connections and Figure 8 for  
detailed timing considerations. In this mode, the clock for  
all devices should be the same. Otherwise, the devices  
will suffer from flickering at line frequency.  
n+2  
n+3  
Row #  
n+4  
n+5  
n+6  
n+7  
Figure 7 Slave Mode Connection  
D[9:0]  
For VGA resolution, the following sub-sampling method is  
available:  
CHSYNC  
VSYNC  
XCLK1  
MHSYNC  
MVSYNC  
MCLK  
Progressive Sub-sampling  
The entire array is sub-sampled for maximal image  
quality. Both horizontal and vertical pixels are  
sub-sampled to an aspect ration of 4:2 as illustrated in  
Figure 6.  
OV9625  
(OV9121)  
Master  
Device  
Figure 8 Slave Mode Timing  
Figure 6 Sub-Sampling Mode  
Tframe  
VSYNC  
Column  
TVS  
Tline  
Tclk  
THS  
HSYNC  
MCLK  
Row  
n
B
G
G
R
B
G
G
R
B
G
G
R
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
NOTE:  
1) THS > 6 Tclk, Tvs > Tline  
2) Tline = 1520 x Tclk (SXGA); Tline = 800 x Tclk (VGA)  
3) Tframe = 1050 x Tline (SXGA); Tframe = 500 x Tline (VGA)  
B
G
G
R
B
G
G
R
B
G
G
R
Channel Average Calculator  
Skipped Pixels  
OV9625/OV9121 provides average output level data for  
the R/G/B channels along with frame-averaged luminance  
level. Access to the data is via the serial control port.  
Average values are calculated from 128 pixels per line (64  
in VGA).  
4
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Functional Description  
mni ision  
O
Two methods of power-down or standby operation are  
available with the OV9625/OV9121.  
Reset  
The RESET pin (pin 10) is active high. There is an internal  
pull-down (weak) resistor in the sensor so the default  
status of the RESET pin is low.  
Hardware power-down may be selected by pulling  
the PWDN pin (pin 7) high (+3.3VDC). When this  
occurs, the OV9625/OV9121 internal device clock is  
halted and all internal counters are reset. The current  
draw is less than 10 µA in this standby mode.  
Software power-down can be effected by setting the  
COMC[4] register bit high. Standby current will be  
less then 1 mA when in software power-down. All  
register content is maintained in standby mode.  
Figure 9 RESET Timing Diagram  
RESET  
1ms  
4096 External Clock  
There are two ways for a sensor reset:  
SCCB Interface  
1.  
Hardware reset - Pulling the RESET pin high and  
keeping it high for at least 1 ms. As shown in  
Figure 9, after a reset has been initiated, the sensor  
will be most stable after the period shown as 4096  
External Clock.  
OV9625/OV9121 provides an on-chip SCCB serial control  
port that allows access to all internal registers, for  
complete control and monitoring of OV9625/OV9121  
operation.  
2.  
Software reset - Writing 0x80 to register 0x12 (see  
“COMH” on page 20) for a software reset. If a  
software reset is used, a reset operation done twice  
is recommended to make sure the sensor is stable  
and ready to access registers. When performing a  
software reset twice, the second reset should be  
initiated after the 4096 External Clock period as  
shown in Figure 9.  
Refer to OmniVision Technologies Serial Camera Control  
Bus (SCCB) Specification for detailed usage of the SCCB  
interface.  
Video Output  
RGB Raw Data Output  
Power-Down Mode  
The OV9625 CAMERACHIP offers 10-bit RGB raw data  
output.  
The PWDN pin (pin 7) is active high. There is an internal  
pull-down (weak) resistor in the sensor so the default  
status of the PWDN pin is low.  
B&W Output  
Figure 10 PWDN Timing Diagram  
The OV9121 offers 10-bit luminance signal data output.  
PWDN  
Sensor Power Down  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
5
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Digital Video Port  
MSB/LSB Swap  
Line/Pixel Timing  
The OV9625/OV9121 digital video port can be  
programmed to work in either master or slave mode.  
In both master and slave modes, pixel data output is  
synchronous with PCLK (or MCLK if port is a slave),  
HREF and VSYNC. The default PCLK edge for valid data  
is the negative edge but may be programmed with register  
COMK[4] (see “COMK” on page 22) for the positive edge.  
Basic line/pixel output timing is illustrated in Figure 14 and  
Figure 15.  
OV9625/OV9121 has a 10-bit digital video port. The MSB  
and LSB can be swapped with the control registers.  
Figure 11 shows some examples of connections with  
external devices.  
Figure 11 Connection Examples  
To minimize image capture circuitry and conserve  
memory space, PCLK output can be programmed with  
register COMK[5] (see “COMK” on page 22) to be  
qualified by the active video period as defined by the  
HREF signal. See Figure 12 for details.  
MSB D9  
D8  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
LSB D9  
D8  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D7  
D7  
D6  
D6  
D5  
D5  
Figure 12 PCLK Output Only at Valid Pixels  
D4  
D4  
D3  
D3  
PCLK  
PCLK active edge negative  
D2  
D2  
HREF  
D1  
D1  
PCLK  
PCLK active edge positive  
LSB D0  
MSB D0  
VSYNC  
OV9625  
(OV9121)  
External  
Device  
OV9625  
(OV9121)  
External  
Device  
Default 10-bit Connection  
Swap 10-bit Connection  
Pixel Output Pattern  
Table 1 shows the output data order from the  
OV9625/OV9121. The data output sequence following the  
MSB D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
LSB D9  
D8  
first HREF and after VSYNC is: B  
G
B
G
0,0  
0,1 0,2  
0,3  
1,0  
B
R
G
1,2  
. After the second HREF, the output is G  
0,1278 0,1279  
1,1  
D7  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
G
R
G
R
…, etc. If the  
1,3  
1,1278  
1,1279  
D6  
D6  
OV9625/OV9121 is programmed to output VGA  
resolution data, horizontal and vertical sub-sampling will  
occur. The default output sequence for the first line of  
D5  
D5  
D4  
D4  
output will be: B  
G
B
G
… B  
G . The  
0,0 0,1 0,4 0,5  
0,1276 0,1277  
D3  
D3  
second line of output will be: G  
R
G
R
… G  
1,0 1,1 1,4 1,5 1,1276  
R
.
1,1277  
D2  
D2  
D1  
D1  
Table 1  
Data Pattern  
LSB D0  
MSB D0  
R/C  
0
1
2
3
. . .  
. . .  
. . .  
. . .  
. . .  
1278  
1279  
OV9625  
(OV9121)  
External  
Device  
OV9625  
(OV9121)  
External  
Device  
0
1
2
3
B
G
B
G
B
G
R
G
R
0,0  
0,1  
1,1  
0,2  
0,3  
1,3  
2,3  
3,3  
0,1278  
0,1279  
1,1279  
2,1279  
3,1279  
Default 8-bit Connection  
Swap 8-bit Connection  
G
R
R
G
R
G
R
G
1,0  
2,0  
1,2  
2,2  
1,1278  
2,1278  
B
G
B
B
2
G
G
G
3,1278  
3,0  
3,1  
3,2  
.
.
.
.
1022  
1023  
B
G
B
G
R
B
G
R
1022,0  
1022,1  
1022,2  
1022,3  
1022,1278  
1022,1279  
G
R
G
G
1023,1278  
1023,0  
1023,1  
1023,2  
1023,3  
1023,1279  
6
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Functional Description  
mni ision  
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Timing Generator  
Frame Rate Timing  
In general, the timing generator controls the following  
functions:  
Default frame timing is illustrated in Figure 16 and  
Figure 17. Refer to Table 2 for the actual pixel rate at  
different frame rates.  
Frame Exposure Mode Timing  
Frame Rate Timing  
Frame Rate Adjust  
Table 2  
Frame and Pixel Rates  
Frame Rage (fps)  
15  
10  
7.5  
6
5
Frame Exposure Mode Timing  
PCLK (MHz)  
24  
16  
12  
9.6  
8
OV9625/OV9121 supports frame exposure mode.  
Typically the frame exposure mode must work with the aid  
of an external shutter.  
NOTE: Based on 24 MHz external clock and internal PLL  
on, frame rate is adjusted by the main clock divide method.  
The frame exposure pin, FREX (pin 8) is the frame  
exposure mode enable pin and EXPSTB (pin 12) serves  
as the exposure start trigger for the sensor. There are two  
ways to set Frame Exposure mode:  
Frame Rate Adjust  
OV9625/OV9121 offers three methods of frame rate  
adjustment.  
Control both FREX and EXPSTB pins - Frame  
Exposure mode can be set by pulling both FREX and  
EXPSTB pins high at the same time (see Figure 19).  
1.  
2.  
3.  
Clock prescaler (see “CLKRC” on page 20)  
By changing the system clock divide ratio, the frame  
rate and pixel rate will change together. This  
method can be used for dividing the frame/pixel rate  
by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate.  
Control FREX only and keep EXPSTB low - In this  
case, the pre-charge time is tline and sensor  
exposure time is the period after pre-charge until the  
shutter closes (see Figure 18).  
Line adjustment (see “COML” on page 24 and see  
“FRARL” on page 25)  
By adding dummy pixel timing in each line, the  
frame rate can be changed while leaving the pixel  
rate as is.  
When the external master device asserts the FREX pin  
high, the sensor array is quickly pre-charged and stays in  
reset mode until the EXPSTB pin is pulled low by the  
external master (sensor exposure time can be defined as  
the period between EXPSTB low to shutter close). After  
the FREX pin is pulled low, the video data stream is then  
clocked to the output port in a line-by-line manner. After  
completing one frame of data output, OV9625/OV9121  
will output continuous live video data unless in single  
frame transfer mode. Figure 18 and Figure 19 show the  
detailed timing for this mode.  
Vertical sync adjustment  
By adding dummy line periods to the vertical sync  
period (see “ADDVSL” on page 25 and see  
“ADDVSH” on page 25), the frame rate can be  
altered while the pixel rate remains the same.  
After changing registers COML (0x2A) and FRARL (0x2B)  
to adjust the dummy pixels, it is necessary to write to  
register COMH (0x12) or CLKRC (0x11) to reset the  
counter. Generally, OmniVision suggests users write to  
register COMH (0x12) (to change the sensor mode) as the  
last one. However, if you want to adjust the cropping  
window, it is necessary to write to those registers after  
changing register COMH (0x12). To use COMH to reset  
the counter, it is necessary to generate a pulse on  
resolution control register bit COMH[6].  
For frame exposure, register AEC (0x10) must be set to  
0xFF and register GAIN (0x00) should be no larger than  
0x10 (maximum 2x gain).  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
7
OV9625/OV9121  
Pin Description  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
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Table 3  
Pin Description  
Name  
SVDD  
Pin Number  
Pin Type  
Power  
Function/Description  
3.3 V power supply for the pixel array  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
VrHIGH  
NBIT  
Analog  
Analog  
Power  
Sensor high reference - bypass to ground using a 0.1 µF capacitor  
Sensor bit line reference - bypass to ground using a 0.1 µF capacitor  
3.3 V power supply for the sensor array decoder  
Ground for the sensor array decoder  
DEVDD  
DEGND  
VrLOW  
PWDN  
FREX  
Power  
Analog  
Sensor low reference - bypass to ground using a 0.1 µF capacitor  
Power down mode enable, active high  
a
Input (0)  
Input (0)  
Snapshot trigger, used to activate a snapshot sequence  
No connection  
NC  
RESET  
SCCB_E  
Input (0)  
Input (0)  
Chip reset, active high  
SCCB interface enable, active low  
Snapshot exposure start trigger  
12  
13  
EXPSTB  
VGA  
Input (0)  
Input (0)  
0:  
1:  
Sensor starts exposure - only effective in snapshot mode  
Sensor stays in reset mode  
Sensor Resolution Selection  
0:  
1:  
SXGA resolution (1280 x 1024)  
VGA resolution (640 x 480)  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
FSIN  
VcCHG  
AVDD  
AGND  
ASUB  
VrAD2  
ADVDD  
ADGND  
DVDD  
DGND  
D0  
Input (0)  
Analog  
Power  
Power  
Power  
Analog  
Power  
Power  
Power  
Power  
Output  
Output  
Output  
Output  
Output  
Frame synchronization input  
Sensor reference - bypass to ground using a 1 µF capacitor  
3.3 V power supply for analog circuits  
Ground for analog circuits  
Ground for analog circuit substrate  
A/D converter reference - bypass to ground using a 0.1 µF capacitor  
3.3 V power supply for A/D converter  
Ground for A/D converter  
2.5 V power supply for digital circuits  
Ground for digital circuits  
Digital video output bit[0]  
D1  
Digital video output bit[1]  
D2  
Digital video output bit[2]  
D3  
Digital video output bit[3]  
D4  
Digital video output bit[4]  
8
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Pin Description  
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Table 3  
Pin Description (Continued)  
Pin Number  
Name  
XCLK1  
Pin Type  
Input  
Function/Description  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
Crystal clock input  
XCLK2  
PCLK  
D5  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Power  
Power  
Output  
Output  
Output  
Crystal clock output  
Pixel clock output  
Digital video output bit[5]  
Digital video output bit[6]  
Digital video output bit[7]  
Digital video output bit[8]  
Digital video output bit[9]  
D6  
D7  
D8  
D9  
DOVDD  
DOGND  
HREF  
CHSYNC  
VSYNC  
NC  
3.3 V power supply for digital video port  
Ground for digital video port  
Horizontal reference output  
Horizontal synchronization output when chip is in master mode.  
Vertical synchronization output when chip is in master mode.  
No connection  
NC  
No connection  
NC  
No connection  
SIO_D  
SIO_C  
VcCHG  
SGND  
I/O  
SCCB serial interface data I/O  
Input  
SCCB serial interface clock input  
Sensor reference - bypass to ground using a 1 µF capacitor  
Ground for pixel array.  
Analog  
Power  
a.  
Input (0) represents an internal pull-down low resistor.  
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9
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
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Electrical Characteristics  
Table 4  
Absolute Maximum Ratings  
Ambient Storage Temperature  
-40ºC to +125ºC  
V
V
V
3.3V  
2.5V  
3.3V  
DD-A  
DD-C  
DD-IO  
Supply Voltages (with respect to Ground)  
All Input/Output Voltages (with respect to Ground)  
Lead Temperature, Surface-mount process  
ESD Rating, Human Body model  
-0.3V to V  
+230ºC  
2000V  
+1V  
DD-IO  
NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may  
result in permanent device damage.  
Table 5  
Symbol  
Supply  
DC Characteristics (0°C < T < 70°C)  
A
Parameter  
Min  
Typ  
Max  
Unit  
V
V
V
Supply voltage (DEVDD, ADVDD, AVDD, SVDD)  
Supply voltage (DOVDD)  
Supply voltage (DVDD)  
3.0  
3.0  
3.3  
3.3  
2.5  
40  
1
3.6  
3.6  
V
V
DD-A  
DD-IO  
DD-C  
DD1  
2.25  
2.75  
60  
V
I
I
I
Active (Operating) Current  
Standby Current  
mA  
mA  
µA  
DD2  
Standby Current  
10  
DD3  
Digital Inputs  
V
Input voltage LOW  
Input voltage HIGH  
Input capacitor  
0.8  
10  
V
V
IL  
V
2
IH  
C
pF  
IN  
Digital Outputs (standard loading 25 pF, 1.2 Kto 3 V)  
V
Output voltage HIGH  
Output voltage LOW  
2.4  
V
V
OH  
OL  
V
0.6  
1
SCCB Inputs  
V
SIO_C and SIO_D  
SIO_C and SIO_D  
-0.5  
2.5  
0
V
V
IL  
V
3.3  
V
+ 0.5  
DD  
IH  
10  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Electrical Characteristics  
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Table 6  
Symbol  
ADC Parameters  
AC Characteristics (T = 25°C, V = 3V)  
A
DD  
Parameter  
Min  
Typ  
Max  
Unit  
B
Analog bandwidth  
DC differential linearity error  
12  
0.5  
1
MHz  
LSB  
LSB  
ms  
DLE  
ILE  
DC integral linearity error  
Settling time for hardware reset  
Settling time for software reset  
<1  
<1  
ms  
Settling time for VGA/XSGA mode change  
Settling time for register setting  
<1  
ms  
<300  
ms  
Table 7  
Timing Characteristics  
Parameter  
Symbol  
Min  
8
Typ  
24  
Max  
Unit  
Oscillator and Clock Input  
f
Frequency (XCLK1, XCLK2)  
Clock input rise/fall time  
Clock input duty cycle  
48  
2
MHz  
ns  
OSC  
t , t  
r
f
45  
50  
55  
%
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OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
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Timing Specifications  
Figure 13 SCCB Timing Diagram  
tF  
tR  
tHIGH  
tLOW  
SIO_C  
tHD:STA  
tHD:DAT  
tSU:DAT  
tSU:STA  
tSU:STO  
SIO_D  
IN  
tBUF  
tAA  
tDH  
SIO_D  
OUT  
SCCB_E  
Table 8  
Symbol  
SCCB Timing Specifications  
Parameter  
Min  
Typ  
Max  
Unit  
Clock Frequency  
400  
KHz  
f
t
t
t
t
t
t
t
t
t
t
t
SIO_C  
Clock Low Period  
1.3  
600  
100  
1.3  
600  
600  
0
s  
ns  
ns  
s  
ns  
ns  
s  
ns  
ns  
ns  
ns  
LOW  
Clock High Period  
HIGH  
SIO_C low to Data Out valid  
Bus free time before new START  
START condition Hold time  
START condition Setup time  
Data-in Hold time  
900  
AA  
BUF  
HD:STA  
SU:STA  
HD:DAT  
SU:DAT  
SU:STO  
Data-in Setup time  
100  
600  
STOP condition Setup time  
SCCB Rise/Fall times  
Data-out Hold time  
300  
t
R, F  
50  
DH  
12  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Timing Specifications  
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Figure 14 SXGA Line/Pixel Output Timing  
tp  
tpr  
tpf  
PCLK or  
MCLK  
tdphf  
tdphr  
HREF  
thd  
tsu  
Invalid  
Data  
P1279  
P0  
P1  
P2  
P1278  
P1279  
D[9:0]  
tdpd  
Figure 15 VGA Line/Pixel Output Timing  
tp  
tpr  
tpf  
PCLK or  
MCLK  
tdphf  
tdphr  
HREF  
thd  
tsu  
Invalid  
Data  
P639  
P0  
P1  
P2  
P638  
P639  
D[9:0]  
tdpd  
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OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
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Figure 16 SXGA Frame Timing  
1050 x tline  
VSYNC  
4 x tline  
12396tp  
tline = 1520tp  
240tp  
21284tp  
HREF  
1280tp  
Row 0  
D[9:0]  
Invalid Data  
P0 - P1279  
Row 1  
Row 2  
Row 1023  
Figure 17 VGA Frame Timing  
500 x tline  
VSYNC  
4 x tline  
6558tp  
tline = 800tp  
160tp  
6402tp  
HREF  
640tp  
D[9:0]  
Invalid Data  
P0 - P639  
Row 0  
Row 1  
Row 2  
Row 479  
The specifications shown in Table 9 apply for DVDD = +2.5V, DOVDD = +3.3V, T = 25°C, sensor working at 15 fps,  
A
external loading = 30 pF.  
Table 9  
Pixel Timing Specification  
Symbol  
Parameter  
PCLK period  
Min  
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
20.83  
p
PCLK rising time  
10  
5
pr  
PCLK falling time  
pf  
PCLK negative edge to HREF rising edge  
PCLK negative edge to HREF negative edge  
PCLK negative edge to data output delay  
Data bus setup time  
0
0
5
5
5
dphr  
dphf  
dpd  
su  
0
15  
8
Data bus hold time  
hd  
14  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Timing Specifications  
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Figure 18 Frame Exposure Timing with EXPSTB Staying Low  
Shutter Open  
Shutter  
FREX  
tline  
Sensor  
Exposure Time  
Sensor Timing  
Precharge  
tdfvr  
tdfvf  
tdvsc  
tdvh  
VSYNC  
tdhv  
HREF  
D[9:0]  
No following live video  
frame if set to transfer  
single frame  
Row X  
Row 0  
Row 1  
Row 1199  
Figure 19 Frame Exposure Timing with EXPSTB Asserted  
Shutter Open  
Shutter  
FREX  
tdes  
tdef  
EXPSTB  
Sensor Timing  
VSYNC  
tpre  
Exposure Time  
tdvsc  
Sensor  
Precharge  
tdfvr  
tdfvf  
tdvh  
tdhv  
HREF  
D[9:0]  
No following live video  
frame if set to transfer  
single frame  
Row X  
Row 0  
Row 1  
Row 1199  
Table 10  
Frame Exposure Timing Specifications  
Symbol  
Min  
Typ  
1520 (SXGA)  
800 (VGA)  
4
Max  
Unit  
tp  
tline  
tp  
tvs  
tline  
tp  
tdfvr  
tdfvf  
tdvsc  
8
9
4
2
tline  
tline  
tp  
21044 (SXGA)  
6402 (VGA)  
tdhv  
tdvh  
tdes  
tp  
12396 (SXGA)  
6558 (VGA)  
tp  
tp  
1500 (SXGA)  
780 (VGA)  
tp  
tp  
NOTE 1) FREX must stay high long enough to ensure the entire sensor has been reset.  
2) Shutter must be closed no later then 3040tp (1600tp for VGA) after VSYNC falling edge.  
Version 1.3, September 15, 2003  
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OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
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OV9625/OV9121 Light Response  
Figure 20 OV9625/OV9121 Light Response  
Normalized Spectrum Response  
200  
180  
160  
140  
120  
100  
80  
60  
40  
20  
0
Wavelength (nm)  
R
G
B
Monochrome Response  
1.00  
0.90  
0.80  
0.70  
0.60  
0.50  
0.40  
0.30  
0.20  
0.10  
0.00  
Wavelength  
16  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
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Register Set  
Table 11 provides a list and description of the Device Control registers contained in the OV9625/OV9121. The device slave  
addresses are 60 for write and 61 for read.  
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
AGC – Gain Control  
Bit[7:6]: Reserved  
Bit[5:0]: Gain control gain setting  
Range: 1x to 8x  
00  
GAIN  
00  
RW  
Set COMI[0] = 0 (see “COMI” on page 21) to disable AGC  
Blue gain control MSB, 8 bits (LSB 2 bits in COMA[3:2], see “COMA” on  
page 17)  
01  
02  
BLUE  
RED  
80  
80  
RW  
RW  
Note: This function is not available on the B&W OV9121.  
Red gain control MSB, 8 bits (LSB 2 bits in COMA[1:0], see “COMA” on  
page 17)  
Note: This function is not available on the B&W OV9121.  
Common Control A  
Bit[7:4]: AWB update threshold  
Bit[3:2]: BLUE channel lower 2 bits gain control  
Bit[1:0]: RED channel lower 2 bits gain control  
03  
COMA  
40  
RW  
Note: This function is not available on the B&W OV9121.  
Common Control B  
Bit[7,4]: AWB – Update speed select  
00: Slow  
01: Slowest  
10: Fast  
11: Fast  
Bit[6:5]: AWB – Step select  
00: 1023 steps  
01: 255 steps  
04  
COMB  
00  
RW  
10: 511 steps  
11: 255 steps  
Bit[3]:  
Reserved  
Bit[2:0]: AEC lower 3 bits, AEC[2:0] (see “AEC” on page 19 for  
most significant 8 bits, AEC[10:3])  
05  
06  
07  
08  
BAVG  
GbAVG  
GrAVG  
RAVG  
00  
00  
00  
00  
RW  
RW  
RW  
RW  
B Channel Average  
G Channel Average - picked G pixels in the same line with B pixels.  
G Channel Average - picked G pixels in the same line with R pixels.  
R Channel Average  
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OV9625/OV9121  
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Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Common Control C  
Bit[7:5]: Reserved  
Bit[4]:  
Sleep or power-down mode enable  
0: Normal  
1: Sleep mode  
Bit[3:2]: Crystal oscillator output current  
09  
COMC  
0C  
RW  
00: Weakest  
11: Strongest  
Bit[1:0]: Output Drive Select  
00: Weakest  
01: Double capability  
10: Double capability  
11: Triple drive current  
0A  
0B  
PIDH  
PIDL  
96  
R
R
Product ID Number MSB (Read only)  
Product ID Number LSB (Read only)  
Common Control D  
B1  
Bit[7]:  
Bit[6]:  
Reserved  
Swap MSB and LSB at the output port  
Bit[5:2]: Reserved  
Bit[1]:  
Sensor precharge voltage selection  
0C  
COMD  
28  
RW  
0: Selects internal reference as precharge voltage  
1: Selects SVDD as precharge voltage  
Snapshot option  
Bit[0]:  
0: Enable live video output after snapshot sequence  
1: Output single frame only  
Common Control E  
Bit[7]:  
Bit[6]:  
Reserved  
Anti-blooming control  
0: Anti-blooming ON  
1: Anti-blooming OFF  
Bit[5:3]: Reserved  
Bit[2]:  
Clock output power-down pin status  
0: Maintain internal default states at power-down  
0D  
COME  
00  
RW  
1: Tri-state the VSYNC and CHSYNC pins upon  
power-down  
Bit[1]:  
Bit[0]:  
Reserved  
Digital port output  
0: Enable data port output  
1: Disable data port output  
18  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
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Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Common Control F  
Bit[7]: System clock selection  
0: Use 24 MHz system clock  
1: Use 48 MHz system clock  
Bit[6:3]: Reserved  
Bit[2]:  
Port output range selection  
0E  
COMF  
01  
RW  
0: Output data range is [001] to [3FE]  
1: Output data range is [000] to [3FF]  
Reserved  
Bit[1]:  
Bit[0]:  
AEC option  
0: Disable this function  
1: Enable larger AEC step increase with correct  
exposure time  
Common Control G  
Bit[7]:  
Optical black output selection  
0: Disable  
1: Enable  
Bit[6]:  
Black level calibrate selection  
0: Use electrical black reference  
1: Use optical black pixels to calibrate  
Bit[5:4]: Reserved  
Bit[3]:  
Channel offset adjustment  
0: Disable offset adjustment  
1: Enable offset adjustment, B/Gb/Gr/R channel offset  
levels stored in registers RBIAS (see “BBIAS” on  
page 24), GbBIAS (see “GbBIAS” on page 24),  
GrBIAS (see “GrBIAS” on page 24) and RBIAS (see  
“RBIAS” on page 25).  
0F  
COMG  
47  
RW  
Bit[2]:  
Bit[1]:  
Bit[0]:  
Data range selection  
0: Data range limited to [010] to [3F0]  
1: Full range  
ADC black level calibration bias selection  
0: 040  
1: 010  
ADC black level calibration enable  
0: Disable  
1: Enable  
Automatic Exposure Control Most Significant 8 bits for AEC[10:3] (least  
significant 3 bits, AEC[2:0], in register COMB[2:0] - see “COMB” on  
page 17).  
AEC[10:0]: Exposure time  
10  
AEC  
43  
RW  
T
= t  
x AEC[10:0]  
LINE  
EX  
Set COMI[2] = 0 (see “COMI” on page 21) to disable the AEC.  
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Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Clock Rate Control  
Bit[7]:  
Internal PLL ON/OFF selection  
0: PLL disabled  
1: PLL enabled  
Bit[6]:  
Digital video port master/slave selection  
0: Master mode, sensor provides PCLK  
11  
CLKRC  
00  
RW  
1: Slave mode, external PCLK input from XCLK1 pin  
Bit[5:0]: Clock divider  
CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)  
Common Control H  
Bit[7]:  
SRST  
1: Initiates soft reset. All register are set to factory  
default values after which the chip resumes normal  
operation  
Bit[6]:  
Bit[5]:  
Resolution selection  
0: SXGA  
1: VGA  
Average luminance value pixel counter ON/OFF  
0: OFF  
1: ON  
Reserved  
12  
COMH  
20  
RW  
Bit[4]:  
Bit[3]:  
Master/slave selection  
0: Master mode  
1: Slave mode  
Window output selection  
0: Output only pixels defined by window registers  
1: Output all pixels  
Color bar test pattern  
0: OFF  
Bit[2]:  
Bit[1]:  
Bit[0]:  
1: ON  
Reserved  
20  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
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Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Common Control I  
Bit[7]:  
Bit[6]:  
Bit[5]:  
Bit[4]:  
AEC speed selection  
0: Normal  
1: Faster AEC correction  
AEC speed/step selection  
0: Small steps (slow)  
1: Big steps (fast)  
Banding filter ON/OFF  
0: OFF  
1: ON, set minimum exposure to 1/120s  
Banding filter option  
0: Set to 0, if system clock is 48 MHz and the PLL is  
13  
COMI  
07  
RW  
ON.  
1: Set to 1, if system clock is 24 MHz and the PLL is ON  
or if the system clock is 48 MHz and the PLL is OFF.  
Bit[3]:  
Bit[2]:  
Reserved  
AGC auto/manual control selection  
0: Manual  
1: Auto  
Bit[1]:  
Bit[0]:  
AWB auto/manual control selection  
0: Manual  
1: Auto  
Exposure control  
0: Manual  
1: Auto  
Common Control J  
Bit[7:6]: AGC gain ceiling  
00: 2x  
01: 4x  
10: 8x  
11: 8x  
Bit[5:4]: Reserved  
Bit[3]:  
Auto banding filter  
0: Banding filter is always ON/OFF depending on  
COMI[5] setting (see “COMI” on page 21)  
1: Automatically disable banding filter if light is low  
VSYNC drop option  
0: VSYNC is always output  
1: VSYNC is dropped if frame data is dropped  
Frame data drop option  
14  
COMJ  
76  
RW  
Bit[2]:  
Bit[1]:  
0: Disable data drop  
1: Drop data frame if exposure is not within tolerance.  
In AEC mode, data is normally dropped when data is  
out of range  
Bit[0]:  
Freeze current Exposure and Gain values  
0: Normal  
1: Freeze  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
21  
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Common Control K  
Bit[7]:  
Bit[6]:  
Bit[5]:  
Bit[4]:  
Bit[3]:  
CHSYNC pin output swap  
0: CHSYNC  
1: HREF  
HREF pin output swap  
0: HREF  
1: CHSYNC  
PCLK output selection  
0: PCLK always output  
1: PCLK output qualified by HREF  
PCLK edge selection  
0: Data valid on PCLK falling edge  
1: Data valid on PCLK rising edge  
HREF output polarity  
0: Output positive HREF  
15  
COMK  
00  
RW  
1: Output negative HREF, HREF negative for data valid  
Bit[2]:  
Bit[1]:  
Reserved  
VSYNC polarity  
0: Positive  
1: Negative  
HSYNC polarity  
0: Positive  
1: Negative  
Bit[0]:  
16  
17  
RSVD  
XX  
Reserved  
Horizontal Window Start Most Significant 8 bits, LSB in register  
COMM[1:0] (see “COMM” on page 26).  
HREFST[9:0]: Selects the beginning of the horizontal window,  
each LSB represents two pixels. Adjustment steps  
must be 2 pixels.  
1D  
(13 in  
VGA)  
HREFST  
RW  
Note:  
1. HFREFST[9:0] should be less than HREFEND[9:0].  
2. For maximum output window size of 1292x1024, minimum value of  
this register is 0x1C.  
Horizontal Window end most significant 8 bits, LSB in register  
COMM[3:2] (see “COMM” on page 26).  
HREFEND[9:0]: Selects the end of the horizontal window, each  
LSB represents two pixels. Adjustment steps  
must be 2 pixels.  
BD  
(63 in  
VGA)  
18  
HREFEND  
RW  
Note:  
1. HREFEND[9:0] should be larger than HREFST[9:0].  
2. For maximum output window size of 1292x1024, maximum value of  
this register is 0xBD.  
22  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Vertical Window line start most significant 8 bits, LSB in register  
COMM[4] (see “COMM” on page 26).  
Bit[8:0]: Selects the start of the vertical window, each LSB  
represents four scan lines in SXGA or two scan lines in  
VGA.  
01  
(02 in  
VGA)  
19  
VSTRT  
RW  
Note:  
1. VSTRT[8:0] should be less than VEND[8:0].  
2. For maximum output window size of 1292x1024, minimum value of  
this register is 0x01.  
Vertical Window line end most significant 8 bits, LSB in register  
COMM[5] (see “COMM” on page 26).  
Bit[8:0]: Selects the end of the vertical window, each LSB  
represents four scan lines in SXGA and two scan lines in  
VGA.  
81  
(7A in  
VGA)  
1A  
1B  
VEND  
RW  
RW  
Note:  
1. VEND[8:0] should be larger than VSTRT[8:0].  
2. For maximum output window size of 1292x1024, maximum value of  
this register is 0x81.  
Pixel Shift  
Bit[7:0]: Pixel delay count. Provides a method to fine tune the  
output timing of the pixel data relative to the HREF pulse.  
It physically shifts the video data output time in units of  
pixel clock counts. The largest delay count is [FF] and is  
equal to 255 x PCLK.  
PSHFT  
00  
1C  
1D  
MIDH  
MIDL  
RSVD  
7F  
A2  
XX  
R
R
Manufacturer ID Byte – High (Read only = 0x7F)  
Manufacturer ID Byte – Low (Read only = 0xA2)  
Reserved  
1E-1F  
B Channel Offset Adjustment - auto controlled by internal circuit if  
COMG[0] = 1 (see “COMG” on page 19)  
Bit[7]:  
Offset direction  
0: Add BOFF[6:0]  
1: Subtract BOFF[6:0]  
20  
21  
22  
BOFF  
GbOFF  
GrOFF  
10  
0F  
EF  
RW  
RW  
RW  
Bit[6:0]: B channel offset adjustment value  
Gb Channel Offset Adjustment - auto controlled by internal circuit if  
COMG[0] = 1 (see “COMG” on page 19)  
Bit[7]:  
Offset direction  
0: Add GbOFF[6:0]  
1: Subtract GbOFF[6:0]  
Bit[6:0]: Gb channel offset adjustment value  
Gr Channel Offset Adjustment - auto controlled by internal circuit if  
COMG[0] = 1 (see “COMG” on page 19)  
Bit[7]:  
Offset direction  
0: Add GrOFF[6:0]  
1: Subtract GrOFF[6:0]  
Bit[6:0]: Gr channel offset adjustment value  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
23  
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
R Channel Offset Adjustment - auto controlled by internal circuit if  
COMG[0] = 1 (see “COMG” on page 19)  
Bit[7]:  
Offset direction  
0: Add ROFF[6:0]  
23  
ROFF  
EF  
RW  
1: Subtract ROFF[6:0]  
Bit[6:0]: R channel offset adjustment value  
Luminance Signal High Range for AEC/AGC Operation  
24  
25  
AEW  
AEB  
A0  
88  
RW  
RW  
AEC/AGC values will decrease in auto mode when average  
luminance is greater than AEW[7:0]  
Luminance Signal Low Range for AEC/AGC Operation  
AEC/AGC values will increase in auto mode when average  
luminance is less than AEB[7:0].  
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC  
fast mode (COMI[7] = 1, see “COMI” on page 21)  
Bit[7:4]: High threshold  
Bit[3:0]: Low threshold  
AEC/AGC may change in larger steps when luminance average is  
greater than VV[7:4] or less than VV[3:0].  
26  
27  
28  
29  
VV  
F4  
80  
80  
80  
RW  
RW  
RW  
RW  
B Channel Offset Manual Adjustment Value - effective only when  
COMG[3] = 1 (see “COMG” on page 19).  
Bit[7]:  
Offset direction  
BBIAS  
GbBIAS  
GrBIAS  
0: Add BBIAS[6:0]  
1: Subtract BBIAS[6:0]  
Bit[6:0]: B channel offset adjustment value  
Gb Channel Offset Manual Adjustment Value - effective only when  
COMG[3] = 1 (see “COMG” on page 19).  
Bit[7]:  
Offset direction  
0: Add GbBIAS[6:0]  
1: Subtract GbBIAS[6:0]  
Bit[6:0]: Gb channel offset adjustment value  
Gr Channel Offset Manual Adjustment Value - effective only when  
COMG[3] = 1 (see “COMG” on page 19).  
Bit[7]:  
Offset direction  
0: Add GrBIAS[6:0]  
1: Subtract GrBIAS[6:0]  
Bit[6:0]: Gr channel offset adjustment value  
Common Control L  
Bit[7]:  
Line interval adjustment. Interval adjustment value is in  
COML[6:5] and FRARL[7:0] (see “FRARL” on page 25).  
0: Disabled  
1: Enabled  
2A  
COML  
00  
RW  
Bit[6:5]: Line interval adjust value MSB 2 bits  
Bit[4]: Reserved  
Bit[3:2]: HSYNC timing end point adjustment MSB 2 bits  
Bit[1:0]: HSYNC timing start point adjustment MSB 2 bits  
24  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Line Interval Adjustment Value LSB 8 bits  
2B  
2C  
FRARL  
RBIAS  
00  
80  
RW  
The frame rate will be adjusted by changing the line interval. Each LSB  
will add 2/1520 T  
frame period.  
in SXGA and 2/800 T  
in VGA mode to the  
frame  
frame  
R Channel Offset Manual Adjustment Value - effective only when  
COMG[3] = 1 (see “COMG” on page 19).  
Bit[7]:  
Offset direction  
RW  
0: Add RBIAS[6:0]  
1: Subtract RBIAS[6:0]  
Bit[6:0]: R channel offset adjustment value  
VSYNC Pulse Width LSB 8 bits  
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC  
2D  
2E  
ADDVSL  
ADDVSH  
00  
00  
RW  
RW  
output width is 4 x t . Each LSB count will add 1 x t  
line  
line  
to the VSYNC active period.  
VSYNC Pulse width MSB 8 bits  
Bit[7:0]: Line periods added to VSYNC width. Default VSYNC  
output width is 4 x t . Each MSB count will add  
line  
256 x t  
to the VSYNC active period.  
line  
Luminance Average  
This register will auto update when COMH[5] = 1 (see “COMH” on  
page 20). Average Luminance is calculated from the B/Gb/Gr/R  
channel average as follows:  
2F  
YAVG  
00  
RW  
(BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] +RAVG[7:0])/4  
HSYNC Position and Width Start Point Lower 8 bits  
30  
31  
HSDY  
HEDY  
08  
30  
RW  
RW  
This register and COML[1:0] (see “COML” on page 24) define the  
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel  
period.  
HSYNC Position and Width End Point Lower 8 bits  
This register and COML[3:2] (see “COML” on page 24) define the  
HSYNC start position, each LSB will shift HSYNC start point by 1 pixel  
period.  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
25  
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
Common Control M  
Bit[7:6]: Reserved  
Bit[5]:  
Vertical window end position LSB (MSBs in register  
VEND[7:0] - see “VEND” on page 23)  
Bit[4]:  
Vertical window start position LSB (MSBs in register  
VSTRT[7:0] - see “VSTRT” on page 23)  
0A  
(0Ffor  
VGA)  
32  
COMM  
RW  
Bit[3:2]: Horizontal window end position LSBs (MSBs in register  
HREFST[7:0] - see “HREFEND” on page 22)  
Bit[1:0]: Horizontal window start position LSBs (MSBs in register  
HREFST[7:0] - see “HREFST” on page 22)  
Note: For maximum output window size of 1292x1024, value of this  
register should be 0x0D.  
Current Control  
Bit[7:6]: Sensor current control  
00: Minimum  
11: Maximum  
Sensor current range control  
Bit[5]:  
Bit[4]:  
Bit[3]:  
Bit[2]:  
Bit[1]:  
Bit[0]:  
0:  
1:  
CHLF[7:6] current control at normal range  
CHLF[7:6] current at half range  
Sensor current double ON/OFF  
0:  
1:  
Normal  
Double current  
Sensor buffer current control  
33  
CHLF  
28  
RW  
0:  
1:  
Normal  
Half current  
Column buffer current control  
0:  
1:  
Normal  
Half current  
Analog DSP current control  
0:  
1:  
Normal  
Half current  
ADC current control  
0:  
1:  
Normal  
Half current  
34  
35  
RSVD  
VBLM  
XX  
90  
Reserved  
RW  
Reference Voltage Control  
Sensor Precharge Voltage Control  
Bit[7]:  
Reserved  
Bit[6:4]: Sensor precharge voltage control  
000: Lowest voltage  
36  
VCHG  
17  
RW  
111: Highest voltage  
Bit[3:0]: Sensor array common reference control  
000: Lowest voltage  
111: Highest voltage  
26  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Register Set  
mni ision  
O
Table 11  
Device Control Register List  
Address  
(Hex)  
Register  
Name  
Default  
(Hex)  
R/W  
Description  
ADC Reference Control  
Bit[7:4]: Reserved  
Bit[3]:  
ADC input signal range  
0:  
1:  
Input signal x 1  
Input signal x 0.7  
37  
ADC  
04  
RW  
Bit[2:0]: ADC range control  
000: Minimum  
111: Maximum  
Analog Common Control  
Bit[7]:  
Analog gain control  
0:  
1:  
Normal  
Gain increase 1.5x  
38  
ACOM  
12  
RW  
Bit[6]:  
Analog black level calibration control  
0:  
1:  
Analog BLC ON  
Analog BLC OFF  
Bit[5:0]: Reserved  
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
27  
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Package Specifications  
The OV9625/OV9121 uses a 48-pin ceramic package. Refer to Figure 21 for package information and Figure 22 for the array  
center on the chip.  
Figure 21 OV9625/OV9121 Package Specifications  
.088 ± .011  
.560 SQ + .012 / - .005  
.430 SQ ± .005  
.065 ± .007  
.030 ± .002  
.015 ± .002  
.020 ± .002  
.440 ± .005  
.06 + .010 / - .005  
.040 TYP  
.040 ± .003  
30  
.350 SQ ± .005  
31  
42  
42  
43  
31  
.032 MIN  
43  
42  
31  
30  
43  
30  
.022 ± .004  
.001 to .005 TYP  
.488  
± .004  
48  
1
48  
1
48  
1
0.0287  
Pin 1  
Index  
Image  
Plane  
.012 TYP  
REF  
6
7
19  
.020 TYP  
6
19  
6
19  
7
18  
18  
18  
R .0075  
(48 PLCS)  
7
.085 TYP  
R .0075  
(4 CORNERS)  
Table 12  
OV9625/OV9121 Package Dimensions  
Dimensions  
Millimeters (mm)  
Inches (in.)  
.560 + .012 / - .005 SQ  
.088 + .011  
Package Size  
14.22 + 0.30 / -0.13 SQ  
2.23 + 0.28  
Package Height  
Substrate Height  
Cavity Size  
0.51 + 0.05  
.020 + .002  
8.89 + 0.13 SQ  
1.14 + 0.13  
.350 + .005 SQ  
.045 + .005  
Castellation Height  
Pin #1 Pad Size  
Pad Size  
0.51 x 2.16  
.020 x .085  
0.51 x 1.02  
.020 x .040  
Pad Pitch  
1.02 + 0.08  
.040 + .003  
Package Edge to First Lead Center  
End-to-End Pad Center-Center  
Glass Size  
1.524 + 0.25 / -0.13  
11.18 + 0.13  
.06 + .010 / - .005  
.440 + .005  
12.40 + 0.10 SQ / 13.00 + 0.10 SQ  
0.55 + 0.05  
.488 + .004 SQ / .512 + .004 SQ  
.022 + .002  
Glass Height  
28  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
Package Specifications  
mni ision  
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Sensor Array Center  
Figure 22 OV9625/OV9121 Sensor Array Center  
Package  
Package Center  
(0, 0)  
Die  
Sensor  
Array  
Positional Tolerances  
Die shift (x,y) = 0.15 mm (6 mils) max.  
Die tilt = 1 degrees max.  
Die rotation = 3 degrees max.  
1
Pin 1  
Array Center  
(15.7 µm, -271.6 µm)  
(0.62 mil, -10.69 mil)  
Important:  
Most optical systems invert and mirror the image so the chip is usually  
mounted on the board with pin 1 (SVDD) down as shown.  
NOTE: Picture is for reference only, not to scale.  
Version 1.3, September 15, 2003  
Proprietary to OmniVision Technologies  
29  
OV9625/OV9121  
CMOS SXGA (1.3 MPixel) CAMERACHIP™  
mni ision  
O
Note:  
• All information shown herein is current as of the revision and publication date. Please refer  
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all  
documentation.  
• OmniVision Technologies, Inc. reserves the right to make changes to their products or to  
discontinue any product or service without further notice (It is advisable to obtain current product  
documentation prior to placing orders).  
• Reproduction of information in OmniVision product documentation and specifications is  
permissible only if reproduction is without alteration and is accompanied by all associated  
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible  
or liable for any information reproduced.  
• This document is provided with no warranties whatsoever, including any warranty of  
merchantability, non-infringement, fitness for any particular purpose, or any warranty  
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision  
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary  
rights, relating to use of information in this document. No license, expressed or implied, by  
estoppels or otherwise, to any intellectual property rights is granted herein.  
• ‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade,  
product or service names referenced in this release may be trademarks or registered trademarks of  
their respective holders. Third-party brands, names, and trademarks are the property of their  
respective owners.  
For further information, please feel free to contact OmniVision at info@ovt.com.  
OmniVision Technologies, Inc.  
1341 Orleans Drive  
Sunnyvale, CA USA  
(408) 542-3000  
30  
Proprietary to OmniVision Technologies  
Version 1.3, September 15, 2003  
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