OX9160
OXFORD SEMICONDUCTOR LTD.
5 LOCAL BUS
5.1 Overview
strobe LBWR#, in Intel-type interfaces. For Motorola-type
interfaces, LBWR# is re-defined to perform read/write
control signal (LBRDWR#) and the chip-select signals
(LBCS[3:0]#) are re-defined to data-strobe (LBDS[3:0]#).
The OX9160 incorporates a bridge from PCI to the Local
bus. It allows card developers to easily migrate legacy
soluations to PCI.
A reference cycle is defined, as two PCI clock cycles after
the master asserts the IRDY# signal for the first time within
a frame. In general, all the local bus control signals change
state in the first cycle after the reference cycle, with offsets
to provide suitable setup and hold times for common
peripheral devices. However, all the timings can be
increased / decreased independently in multiples of PCI
clock cycles. This feature enables the card designer to
override the length of read or write operations, the address
and chip-select set-up and hold timing, and the data bus
hold timing so that add-in cards can be configured to suit
different speed peripheral devices connected to the Local
bus. The designer can also program the data bus to remain
in the high impedance state or actively drive the bus during
idle periods.
When Mode[1:0] is ‘00’, the Local bus is comprised of a bi-
directional 8-bit data bus, an 8-bit address bus, up to four
chip selects, and a number of control signals that allow for
easy interfacing to standard peripherals. It also provides
twelve active-high or active-low interrupt inputs.
When Mode[1:0] is ‘11’, the Local bus is comprised of a bi-
directional 32-bit data bus, a 12-bit address bus, up to four
chip selects, and the same control signals and interrupts as
in 8-bit mode.
The local bus is configured by LT1 and LT2 (see sections
4.4.3 & 4.4.4) in the Local Configuration Register space. By
programming these registers the card developer can alter
the characteristics of the local bus to suit the
characteristics of the peripheral devices being used.
The local bus will always return to an idle state, where no
chip-select (data-strobe in Motorola mode) signal is active,
between adjacent accesses. During read cycles the local
bus interface latches data from the bus on the rising edge
of the clock where LBRD# (LBDS[3:0]# in Motorola mode)
goes high. Card designers should ensure that their
peripherals provide the OX9160 with the specified data set-
up and hold times with respect to this clock edge.
5.2 Operation
The local bus can be accessed via I/O and memory space,
at addresses defined by BAR 0 and BAR 1 of configuration
space. The mapping to the devices will vary with the
application, but the bus is fully configurable to facilitate
simple development.
The local bus cannot accept burst transfers from the PCI
bus. If a burst transfer is attempted the PCI interface will
signal 'disconnect with data' on the first data phase. The
local bus does accept 'fast back-to-back' transactions from
PCI.
The operation of the local bus is synchronised to the PCI
bus clock. A buffered PCI clock signal is output on pin
LBCLK if it has been enabled by setting LT2[30].
A PCI target must complete the transaction within 16 PCI
clock cycles from assertion of the FRAME# signal,
otherwise it should signal a retry. During a read operation
from the Local bus, OX9160 waits for master-ready signal
(IRDY#) and computes the number of remaining cycles to
the de-assertion of the read control signal. If the total
number of PCI clock cycles for that frame is greater than
16 clock cycles, OX9160 will post a retry. The master
would normally return immediately and complete the
operation in the following frame.
The eight bit bi-directional pins LBD[7:0] (LBD[31:0] in 32-
bit mode) drive the output data onto the bus during local
bus write cycles. For reads, the device latches the data
read from these pins at the end of the cycle.
The local bus address is placed on pins LBA[7:0]
(LBA[11:0] in 32-bit mode) at the start of each local bus
cycle and will remain latched until the start of the
subsequent cycle. If the maximum allowable block size
(256 bytes) is allocated to the local bus in I/O space, then
as access in I/O space is byte aligned, AD[7:0] are
asserted on LBA[7:0]. If a smaller address range is
selected, the corresponding upper address lines will be set
to logic zero.
The control bus is comprised of up to four chip-select
signals LBCS[3:0]#, a read strobe LBRD# and a write
Data Sheet Revision 1.22
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