PX3511D
thresholds outlined in the Electrical Specifications determine
when the lower and upper gates are enabled.
As an example, suppose two IRLR7821 FETs are chosen as
the upper MOSFETs. The gate charge, Q , from the data
G
sheet is 10nC at 4.5V (V ) gate-source voltage. Then the
GS
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
Q
is calculated to be 53nC for PVCC = 12V. We will
GATE
assume a 200mV droop in drive voltage over the PWM
cycle. We find that a bootstrap capacitance of at least
0.267µF is required.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM input through the body diode of the controller’s PWM
output when the power-up and/or power-down sequence of
bias supplies of the driver and PWM controller are required.
1.6
1.4
1.2
1.
Power-On Reset (POR) Function
0.8
0.6
During initial startup, the VCC voltage rise is monitored.
Once the rising VCC voltage exceeds 6.4V (typically),
operation of the driver is enabled and the PWM input signal
takes control of the gate drives. If VCC drops below the
falling threshold of 5.0V (typically), operation of the driver is
disabled.
Q
= 100nC
GATE
0.4
50nC
0.2
0.0
20nC
Pre-POR Overvoltage Protection
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Prior to VCC exceeding its POR level, the upper gate is held
low and the lower gate is controlled by the overvoltage
protection circuits. The PHASE is connected to the gate of
the low side MOSFET (LGATE), which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during startup, normal, or shutdown conditions. For
complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
ΔV (V)
BOOT_CAP
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The PX3511D provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The PX3511D
ties the upper and lower drive rails together. Simply applying
a voltage from +4.5V up to 13.2V on PVCC sets both gate
drive rail voltages simultaneously, while VCC’s operating
range is from +6.8V up to 13.2V. For 5V operation,
ISL6596/ISL6609 is recommended.
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces voltage
stress on the boot to phase pins.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F ), the output drive impedance, the
SW
external gate resistance, and the selected MOSFET’s
internal gate resistance and total gate charge. Calculating
the power dissipation in the driver for a desired application is
critical to ensure safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond the
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
Q
GATE
-------------------------------------
C
≥
BOOT_CAP
ΔV
BOOT_CAP
(EQ. 1)
temperature, while the power dissipation capacity in the DFN
package, with an exposed heat escape pad, is more than
1.5W. The DFN package is more suitable for high frequency
applications. See Layout Considerations paragraph for
thermal transfer improvement suggestions. When designing
the driver into an application, it is recommended that the
following calculation is used to ensure safe operation at the
desired frequency for the selected MOSFETs. The total gate
drive power losses due to the gate charge of MOSFETs and
Q
• PVCC
G1
-----------------------------------
Q
=
• N
Q1
GATE
V
GS1
where Q is the amount of gate charge per upper MOSFET
G1
at V
gate-source voltage and N is the number of
GS1
control MOSFETs. The DV
Q1
term is defined as the
BOOT_CAP
allowable droop in the rail of the upper gate drive.
FN6463.0
February 26, 2007
7
