return data from a command or action is always one SPI
cycle behind.
host to QT, and QT to host, at the same time. However the
return data from the QT is always the standard response byte
regardless of the command.
An acquisition burst always happens about 920µs after /SS
goes high after coming out of Sleep mode. SPI clocking
lasting more than 15ms can cause the chip to self-reset.
The setup and hold times should be observed per Figure 3-1.
3.2.4 Sleep Mode
3.2.1 /SS Line
Please refer to Figure 3-1, page 6.
/SS acts as a framing signal for SPI data clocking under host
control. See Figure 3-1.
The device always enters low-power sleep mode after an SPI
transmission (Figure 3-1), at or before about 35µs after the
last rising edge of CLK. Coincident with the sleep mode, the
device will lower DRDY. If another immediate acquisition
burst is desired, /SS should be raised again at least 35 µs
after the last rising edge of CLK. To prolong the sleep state, it
is only necessary to raise /SS after an even longer duration.
After a shift operation /SS must go high again, a minimum of
35µs after the last clock edge on CLK. The device
automatically goes into sleep state during this interval, and
wakes again after /SS rises. If /SS is simply held low after a
shift operation, the device will remain in sleep state up to the
maximum time shown in Figure 3-1. When /SS is raised,
another acquisition burst is triggered.
Changes on CLK will also cause the device to wake, however
the device will not cause an acquire burst to occur if /SS has
also gone low and high again.
In sleep mode, the device consumes only a few microamps of
current. The average current can be controlled by the host, by
adjusting the percentage of time that the device spends in
sleep.
If /SS is held high all the time, the device will burst in a
free-running mode at a ~17Hz rate. In this mode a valid
position result can be obtained quickly on demand, and/or
one of the two OUT pins can be used to wake the host. This
rate depends on the burst length which in turn depends on
the value of each Cs and load capacitance Cx. Smaller
values of Cs or higher values of Cx will make this rate faster.
The delay between the wake signal and the following burst is
1ms max to allow power to stabilize. If the maximum spec on
/SS low (1s) is exceeded, the device will eventually come out
of sleep and calibrate again on its own.
The Detect and DRDY lines will float for ~400µs (typical at
Vdd = 3.3V) after wake from Sleep mode; see Section 1.3 for
details.
Dummy /SS Burst Triggers: In order to force a single burst,
a dummy ‘command’ can be sent to the device by pulsing /SS
low for 10µs to 10ms; this will trigger a burst on the rising
edge of /SS without requiring an actual SPI transmission.
DRDY will fall within 56µs of /SS rising again, and then a
burst will occur 1mS later (while DRDY stays low).
After each acquisition burst, DRDY will rise again to indicate
that the host can do another SPI transmission.
After the burst completes, DRDY will rise again to indicate
that the host can get the results.
Note: Pin /SS clamps to Vss for 250ns after coming out of
sleep state as a diagnostic pulse. To prevent a possible pin
drive conflict, /SS should either be driven by the host as an
open-drain pull-high drive (e.g. with a 100K pullup resistor), or
there should be a ~1K resistor placed in series with the /SS
pin.
3.3 Commands
Commands are summarized in Table 3-1. Commands can be
overlapped, i.e. a new command can be used to shift out the
results from a prior command.
All commands cause a new acquisition burst to occur when
/SS is raised again after the command byte is fully clocked.
3.2.2 DRDY Line
Standard Response: All SPI shifts return a ‘standard
The DRDY line acts primarily as a way to inhibit the host from
clocking to the QT510 when the QT510 is busy. It also acts to
signal to the host when fresh data is available after a burst.
The host should not attempt to clock data to the QT510 when
DRDY is low, or the data will be ignored or cause a framing
error.
response’ byte which depends on the touch detection state:
No touch detection: Bit 7 = 0 (0= not touched)
Bit 6 = 1 to indicate QWheel type
= 0 to indicate Linear slider type
Bits 5, 4, 3, 2: unused (0)
Bit 1 = 1 if signal polarity error
On power-up, DRDY will first float for about 20ms, then pull
low for ~525ms until the initial calibration cycle has
completed, then drive high to indicate completion of
calibration. The device will be ready to communicate in
typically under 600ms (with Cs1 = Cs2 = 100nF).
While DRDY is a push-pull output; however, this pin floats
after power-up and after wake from Sleep mode, for ~400µs
(typical at Vdd = 3.3V). It is desirable to use a pulldown
resistor on DRDY to prevent false signalling back to the host
controller; see Figure 1-1 and Section 1.3.
Bit 0 = 1 if prox detection only
Is touch detection:
Bit 7 = 1 (1= is touched)
Bits 0..6: Contain calculated position
Note that touch detection calculated position is based on the
results of the prior burst, which is triggered by the prior /SS
rising edge (usually, from the prior command, or, from a
dummy /SS trigger - see Section ).
Bit 6 indicates the type of device: ‘1’ means that the device is
a wheel (e.g. QT510), and ‘0’ means the device is a linear
type (e.g. QT401).
3.2.3 MISO / MOSI Data Lines
MISO and MOSI shift on the falling edge of each CLK pulse.
The data should be clocked in on the rising edge of CLK. This
applies to both the host and the QT510. The data path follows
a circular buffer, with data being mutually transferred from
There are 5 commands as follows.
lQ
7
QT510 R6.04/0505
