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Advanced Information

Preliminary

OV6620/OV6120

OV6620 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA

OV6120 SINGLE-CHIP CMOS CIF B&W DIGITAL CAMERA

Features

n

101,376 pixels, 1/4” lens, CIF/QCIF format

n

Frame exposure/line exposure option

5-Volt operation, low power dissipation

Progressive scan read out

Data format - YCrCb 4:2:2, GRB 4:2:2, RGB Raw Data

8/16 bit video data: CCIR601, CCIR656, ZV port

Wide dynamic range, anti-blooming, zero smearing

Electronic exposure / Gain / white balance control

–

< 80 mW active power

< 10 mA in power-save mode

n

Gamma correction (0.45/0.55/1.00)

2

I C programmable (400 kb/s):

Image enhancement - brightness, contrast, gamma,

saturation, sharpness, window, etc.

Internal/external synchronization

– color saturation, brightness, contrast, white balance,

exposure time, gain

n

General Description

The OV6620 (color) and OV6120 (black and white) CMOS Im-

age sensors are single-chip video/imaging camera devices

designed to provide a high level of functionality in a single,

small-footprint package. Both devices incorporate a 352 x 288

image array capable of operating up to 60 frames per second

image capture. Proprietary sensor technology utilizes ad-

vanced algorithms to cancel Fixed Pattern Noise (FPN), elim-

inate smearing, and drastically reduce blooming. All needed

camera functions including exposure control, gamma, gain,

white balance, color matrix, windowing, and more, are pro-

grammable through an I C interface. Both devices can be pro-

grammed to provide image output in either 8-bit or 16-bit

digital formats.

2

Applications include: Video Conferencing, Video Phone, Vid-

eo Mail, Still Image, and PC Multimedia.

Array Elements (CIF)

(QCIF)

356 x 292

(176 x 144)

Pixel Size

9.0 x 8.2 mm

3.1 x 2.5 mm

Up to 60 FPS

Image Area

Max Frames/Sec

Electronic

Exposure

Up to 500 : 1

(for selected FPS)

7

8

9

42

41

40

39

38

37

36

35

34

33

32

31

AGND

AVDD

PWDN

VRCAP1

VRCAP3

IICB

VTO

ADVDD

ADGND

BW/CHSYNC

CBAR/Y0

Y1

G2X/Y2

RGB/Y3

CS1/Y4

SHARP/Y5

CS2/Y6

CS0/Y7

PWDB/PCLK

DOVDD

DGND

Scan Mode

progressive

0.45/.55/1.0

10

11

12

13

14

15

16

17

18

Gamma Correction

OV6620/OV6120

Min. Illumination

(3000K)

OV6620 - < 3 lux @ f1.2

OV6120 - < 0.5 lux @ f1.2

S/N Ratio

(Digital Camera Out)

> 48 dB

(AGC = Off, Gamma = 1)

VSYNC/CSYS

FODD/CLK

HREF/VSFRAM

FPN

< 0.03% V_P-P

< 0.2 nA/cm²

> 72 dB

Dark Current

Dynamic Range

5VDC, ±5% (Anal.)

5VDC or 3.3VDC (DIO)

Power Supply

Power

< 80mW Active

Requirements

< 30mW Standby

OV6620/OV6120 PIN ASSIGNMENTS

Package

48 pin LCC

OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94086 U.S.A.

Tel: (408) 733-3030 Fax: (408) 733-3061

e-mail: info@ovt.com

Version 1.11, 14 May 1999

Website: http://www.ovt.com

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Table 1. Pin Description

Pin No.

01

Name

Pin Type

Function/Description

Array power (+5VDC)

SVDD

V

in

02

RESET

AGCEN

Function

(Default = 0)

Chip Reset, active high

03

04

Function

(Default = 0)

Automatic Gain Control (AGC) selection

“0” - Disable AGC

“1” - Enable AGC

NOTE: This function is disabled when OV6620/OV6120 sensor is config-

2

ured in I C mode.

FREX

Function

Frame Exposure Control

(Default = 0)

“0” - Disable Frame Exposure Control

“1” - Enable Frame Exposure Control

05

06

07

08

09

VRCAP2

ASUB

V

(2.5V)

Array reference. Connect to ground through 0.1 uF capacitor.

Analog substrate voltage

ref

in

AGND

AVDD

Analog ground

in

Analog power supply (+5VDC)

in

PWDN

Function

(Default = 0)

Power down mode selection

“0” - normal mode

“1” - power down mode

10

VrCAP1

N/C

Internal voltage reference. Connect to ground through 0.1 µF capacitor.

Internal voltage reference. Connect to ground through 1 µF capacitor.

11

12

VrCAP3

IICB

2

Function

(Default = 0)

I C enable selection

2

“0” - Enable I C

“1” - Enable autocontrol mode

13

14

15

VTO

O

Luminance Composite Signal Output

ADVDD

ADGND

V

Analog power supply (+5VDC)

Analog signal ground

in

16

17

18

19

20

21

22

23

VSYNC/CSYS

FODD/CLK

HREF/VSFRAM

UV7/B8

I/O

Vertical sync output. At power up, read as CSYS.

Field ID FODD output or main clock output

HREF output. At power up, read as VSFRAM

Bit 7 of U video component output. At power up, sampled as B8.

Bit 6 of U video component output. At power up, sampled as ABKEN.

Bit 5 of U video component output. At power up, sampled as MIR.

Bit 4of U video component output.

UV6/ABKEN

UV5/MIR

UV4

UV3

Bit 3 of U video component output.

Advanced Information

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OMNIVISION TECHNOLOGIES, Inc.

OV6620/OV6120

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

Table 1. Pin Description

Pin No.

Name

UV2/QCIF

Pin Type

I/O

Function/Description

24

25

26

27

28

29

Bit 2 of U video component output. At power up, sampled as QCIF.

Bit 1 of U video component output. At power up, sampled as CC656.

Bit 0 of U video component output. At power up, sampled as GAMMA.

Crystal clock input

UV1/CC656

UV0/GAMMA

XCLK1

I/O

I

XCLK2

O

Crystal clock output

DVDD

V

Digital power supply (+5VDC)

in

30

31

32

DGND

Digital ground

DOGND

DOVDD

Digital interface output buffer ground

Digital interface output buffer power supply (+5VDC)

33

34

35

36

37

38

39

40

41

42

43

PCLK/PWDB

Y7/CS0

I/O

PCLK output. At power up sampled as PWDB.

Bit 7 of Y video component output. At power up, sampled as CS0.

Bit 6 of Y video component output. At power up, sampled as CS2.

Bit 5 of Y video component. At power up, sampled as SHARP.

Bit 4 of Y video component. At power up, sampled as CS1

Bit 3 of Y video component output. At power up, sampled as RGB.

Bit 2 of Y video component output. At power up, sampled as G2X.

Bit 1 of Y video component output.

Y6/CS2

Y5/SHARP

Y4/CS1

Y3/RGB

Y2/G2X

Y1

Y0/CBAR

CHSYNC/BW

DEGND

Bit 0 of Y video component output. At power up, sampled as CBAR.

CHSYNC output. At power up, sampled as BW.

V

I

Decoder ground.

in

44

45

46

47

DEVDD

SCL

Decoder power supply (+5VDC)

2

I C serial interface clock input

2

SDA

I/O

I C serial interface data input and output.

2

MULT

Function

(Default = 0)

I C slave selection

“0” - Select single slave ID

“1” - Enable multiple (8) slaves

48

SGND

V

Array ground

in

14 May 1999

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Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

1. Functional Description

(Note: References to color features do not apply to the OV6120 B&W Digital Image Sensor.)

1.1 Overview

The OV6620/OV6120 sensor is a 1/4-inch CMOS imag-

Referring to Figure 1, OV6620/OV6120 CMOS Image

Sensor Block Diagram below, the OV6620 sensor in-

cludes a 356 x 292 resolution image array, an analog

signal processor, dual 8-bit Analog-to-Digital convert-

ers, analog video multiplexer, digital data formatter and

video port, I C interface and registers, digital controls in-

cluding timing block, exposure, and black and white

balance.

ing device. The sensor contains approximately 101,376

pixels. Its design is based on a field integration read-out

system with line-by-line transfer and an electronic shut-

ter with a synchronous pixel read out scheme. The color

filter of the sensor consists of a primary color RG/GB ar-

ray arranged in line-alternating fashion.

2

VTO

DENB

GAMMA

Y(7:0)

r

g

mx

ADC

b

Y

Cb

Cr

analog processing

UV(7:0)

white

balance

detect

exposure

detect

column sense amp

(356x292)

image

array

registers

2

I C

WB

control

exposure control

video timing generator

interface

sys-clk

AWB

AWBTH/

AWBTM

1/2

AGCEN

SCL SDA IICB

PCLK

HREF VSYNC

MIR

FSIN

FODD CHSYNC

PROG

FZEX

FREZ

XVCLK1

Figure 1. OV6620/OV6120 CMOS Image Sensor Block Diagram

4

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Advanced Information

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OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

1.2 Analog Processor Circuits

1.2.1 Overview

1.2.2 Image Processing

The algorithm used for the electronic exposure control

is based on the brightness of the full image. The expo-

The image is captured by the 356 x 592 pixel image ar-

ray and routed to the analog processing section where

the majority of signal processing occurs. This block con-

tains the circuitry which performs color separation, ma-

trixing, Automatic Gain Control (AGC), gamma

correction, color correction, color balance, black level

calibration, “knee” smoothing, aperture correction, and

controls for picture luminance, chrominance, and anti-

alias filtering. The analog video signals are based on

the following formula:

sure is optimized for a “normal” scene which assumes

the subject is well lit relative to the background. In situ-

ations where the image is not well lit, the Automatic Ex-

posure Control (AEC) White/Black ratio may be

adjusted to suit the needs of the application.

Additional on-chip functions include Automatic Gain

Control (AGC) which provides a gain boost of up to

24dB. White balance control enables setting of proper

color temperature and can be programmed for automat-

ic or manual operation. Separate saturation, brightness,

contrast, and sharpness adjustments allow for further

fine tuning of the picture quality and characteristics. The

OV6620 image sensor also provides control over the

White Balance ratio for increasing/decreasing the im-

age field Red/Blue component ratio. The sensor pro-

vides a default setting which may be sufficient for many

applications.

Y = 0.59G + 0.31R + 0.11B

U = R-Y

V = B-Y

where R,G,B are the equivalent color components in

each pixel.

A YCrCb format is also supported, based on the formula

below:

1.2.3 Windowing

Y = 0.59G + 0.31R + 0.11B

Cr = 0.713 x (R - Y)

The windowing feature of the OV6620/OV6120 image

sensors allows user-definable window sizing as re-

quired by the application. Window size setting (in pixels)

ranges from 2 x 2 to 356 x 292, and can be positioned

anywhere inside the 356 x 292 boundary. Note that

modifying window size and/or position does not change

frame or data rate. The OV6620/OV6120 imager alters

the assertion of the HREF signal to be consistent with

the programmed horizontal and vertical region. The de-

fault output window is 352 x 288.

Cb = 0.564 x (B - Y)

The YCrCb/RGB Raw Data signal from the analog pro-

cessing section is fed to two on-chip 8-bit Analog-to-

Digital (A-to-D) converters: one for the Y/RG channel

and one shared by the CrCb/BG channels. The A-to-D

converted data stream is further conditioned in the digi-

tal formatter. The processed signal is delivered to the

digital video port through the video multiplexer which

routes the user-selected 16-, 8-, or 4-bit video data the

correct output pins.

1.2.4 Zoom Video Port (ZV)

The OV6620/OV6120 image sensor includes a Zoom

Video (ZV) function that supports standard ZV Port in-

terface timing. Signals available include VSYNC,

CHSYNC, PCLK and 16-bit data bus: Y[7:0] and

UV[7:0]. The rising edge of PCLK clocks data into the

ZV port. See Figure 2, Zoom Video Port Timing below.

The on-chip 8-bit A-to-D converters operate at up to 9

MHz, fully synchronous to the pixel rate. Actual conver-

sion rate is set as a function of the frame rate. A-to-D

black-level calibration circuitry ensures the following:

– the black level of Y/RGB is normalized to a value of 16

– the peak white level is limited to 240

– CrCb black level is 128

– Peak/Bottom is 240/16

– RGB raw data output range is 16/240

(Note: Values 0 and 255 are reserved for sync flag)

14 May 1999

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Even Field 1(FODD=0)

Odd Field(FODD=1)

VSYNC

t8 t8

HREF

PCLK

t6

t5

t7

t2

t3

t4

t1

Y[7:0] /

UV[7:0]

1

2

351 352

Valid Data

Horizontal Timing

VSYNC

T

ve

vs

1 Line

Y[7:0]/

UV[7:0]

T

line

Figure 2. Zoom Video Port Timing

Notes:

1. Zoom Video Port format output signal includes:

VSYNC: Vertical sync pulse.

HREF: Horizontal valid data output window.

PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom V Port. Default frequency is 8.86MHz when use

17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data.

Y[7:0]: 8 Bit luminance data bus.

UV[7:0]: 8 Bit chrominance data bus.

2. All timing parameters are provided in Table 13. Zoom Video Port AC Parameters

6

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OV6620/OV6120

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

1.2.5 QCIF Format

A QCIF mode is available for applications where high

resolution image capture is not required. When pro-

grammed in this mode, the pixel rate is reduced by one-

half. Default resolution is 176 x 144 pixels and can be

user-programmed for other resolutions. Refer to Table

7. QCIF Digital Output Format (YUV, beginning of line)

and Table 8. QCIF Digital Output Format (RGB Raw Da-

ta, Beginning of Line) for further information.

The OV6620/OV6120 image sensor can also be pro-

grammed to provide video output in RGB Raw Data 16-

bit/8-bit/4-bit format. The output sequence is matched to

the OV6620 Color Filter Pattern (See Section Figure 4.

Pixel Data Bus (RGB Output), below):

– Y channel output sequence is G R G R

– UV channel output sequence is B G B G

For 8-bit RGB Raw Data video output appears on the Y

channel (with an output sequence of B G R G) and the

UV channel is disabled.

1.2.6 Video Output

The video output port of the OV6620/OV6120 image

sensors provides a number of output format/standard

options to suit many different application requirements.

Table 2. Digital Output Formats, below, indicates the

output formats available. These formats are user pro-

In RGB Raw Data CCIR656 modes, the OV6620/

OV6120 imager asserts SAV (Start of Active Video) and

EAV (End of Active Video) to indicate the beginning and

the ending of HREF window. As a result, SAV and EAV

change with the active pixel window. The 8-bit RGB raw

data is also accessible without SAV and EAV informa-

tion.

2

grammable through the I C interface (See Section 3.1

2

I C Bus Protocol Format).

The OV6620/OV6120 imager supports both CCIR601

and CCIR656 output formats in the following configura-

tions (See Table 3. 4:2:2 16-bit Format for further de-

tails):

The OV6620/OV6120 imagers offer flexibility in YUV

output format. The devices may be programmed as

standard YUV 4:2:2. These devices may be configured

to “swap” the U V sequence. When swapped, the UV

channel output format for 16-bit configurations be-

comes:

– 16-bit, 4:2:2 format

(This mode complies with the 60/50 Hz CCIR601 tim-

ing standard. See Table 3. 4:2:2 16-bit Format be-

low)

– V U V U...etc.

and for 8-bit configurations becomes:

– V Y U Y ...etc.

– 8-bit data mode

(In this mode, video information is output in Cb Y Cr

Y order using the Y port only and running at twice the

pixel rate during which the UV port is inactive. See

Table 4. 4:2:2 8-bit Format below)

A third format is available for the 8-bit configurations

and OV6620/OV6120 enables the Y/UV sequence

swap:

– 4-bit nibble mode

– Y U Y V ...etc.

(In the nibble mode, video output data appears at bits

Y4-Y7. The clock rate for the output runs at twice the

normal output speed when in B/W mode, and 4 times

the normal output speed in when in color mode.)

The OV6620 color single-IC camera can be configured

for use as a black and white imaging device. In this

mode, vertical resolution is greater than in color. Video

data output is provided at the Y port (pins 34:41) and the

UV port is tri-stated. The data (Y/RGB) output rate is

equivalent to operating in 16-bit mode.

– 704 x 288 format

(When programmed for this mode, the OV6620/

OV6120 pixel clock is doubled and the video output

sequence is Y0Y0Y1Y1 ... and U0U0V0V0 ... See

Figure 3, Pixel Data Bus (YUV Output), below.)

The Y/UV or RGB output byte MSB and LSB can be re-

verse-ordered on the OV6620/OV6120 device. The Y7

- Y0 default sequence sets Y7 as MSB and Y0 as LSB.

Programming a reverse order configuration sets Y7 as

LSB and Y0 is MSB, with bits Y2-Y6 reversed-ordered

appropriately.

The OV6620/OV6120 imaging devices provide VSYNC,

HREF, PCLK, FODD, CHSYNC as standard output vid-

eo timing signals.

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Table 2. Digital Output Formats

Resolution

YUV

Pixel Clock

16-bit

352 x 288

704 x 288

176 x 144

Y

8-bit

4:2:2

CCIR656

Nibble

RGB

16-bit

8-bit

CCIR656¹

Nibble

16-bit

Y

Y/UV

8-bit

Y

swap²

U/V

YUV³

Y

RGB⁴

16-bit

8-bit

swap

YG

One

16-bit

8-bit

Y

Line

MSB/LSB swap⁵

Y

Notes:

(“Y” indicates mode/combination is supported by OV6620/OV6120.)

1. When in RGB CCIR656 format, output is 8 bits. SAV and EAV are inserted at the beginning and ending of

HREF, which synchronize the acquisition of Vsync and Hsync. In this format, an 8-bit data bus configuration

(without VSYNC and CHSYNC) may be used.

2. Y/UV swap is valid only in 8-bit mode. Y channel output sequence is Y U Y V...

3. In YUV format, U/V swap means UV channel output sequence swap. V U V U... for 16 bit; V Y U Y ... for 8-bit.

4. In RGB format, U/V swap means neighbor row B R output sequence swap. Refer to

RGB raw data output format for further details

8

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OV6620/OV6120

Table 3. 4:2:2 16-bit Format

Data Bus Pixel Byte Sequence

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

UV7

U7

U6

U5

U4

U3

U2

U1

U0

V7

V6

V5

V4

V3

V2

V1

V0

U7

U6

U5

U4

U3

U2

U1

U0

V7

V6

V5

V4

V3

V2

V1

V0

U7

U6

U5

U4

U3

U2

U1

U0

V7

V6

V5

V4

V3

V2

V1

V0

UV6

UV5

UV4

UV3

UV2

UV1

UV0

Y FRAME

UV FRAME

0

1

2

3

4

5

0

2

4

Table 4. 4:2:2 8-bit Format

Data Bus

Pixel Byte Sequence

Y7

U7

U6

U5

U4

U3

U2

U1

U0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

V7

V6

V5

V4

V3

V2

V1

V0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

U7

U6

U5

U4

U3

U2

U1

U0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

V7

V6

V5

V4

V3

V2

V1

V0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y FRAME

UV FRAME

0

1

2

3

0 1

2 3

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

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T

clk

PCLK

HREF

T

hd

T

su

10

Y

V

10

80

Y[7:0]

80

U

UV[7:0]

repeat for all data bytes

Pixel Data 16-bit Timing

(PCLK rising edge latches data bus)

T

clk

PCLK

HREF

T

su

T

hd

10

80

10

U

Y

V

Y

80

10

Y[7:0]

repeat for all data bytes

Pixel Data 8-bit Timing

(PCLK rising edge latches data bus)

Note: T_clkis pixel clock period. When the OV6620 system clock is 17.73 MHz, T_clk= 112 ns for 16-bit

output; T_clk= 56 ns for 8-bit output. T_suis HREF set-up time, maximum is 15 ns; T_hdis HREF hold time,

maximum is 15 ns.

Figure 3. Pixel Data Bus (YUV Output)

10

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T

clk

PCLK

HREF

T

su

hd

10

G

B

R

G

10

Y[7:0]

10

UV[7:0]

repeat for all data bytes

Pixel Data 16-bit Timing

PCLK rising edge latches data bus

T

clk

PCLK

HREF

Y[7:0]

T

hd

T

su

10

B

G

B

G

10

repeat for all data bytes

Pixel Data 8-bit Timing

PCLK rising edge latches data bus

Note: T_clkis pixel clock period. When the OV6620 system clock is 17.73MHz, T_clk= 112ns for 16-bit

output; T_clk= 56ns for 8-bit output. T_suis HREF set-up time, maximum is 15 ns; T_hdis HREF hold time,

maximum is 15 ns.

Figure 4. Pixel Data Bus (RGB Output)

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OV6620/OV6120

MSB/LSB swap means: Default Y/UV channel output port relationship is:

Table 5. Default Output Sequence

MSB

LSB

Output Port

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Internal Output data Y7

If the device is programmed for data swap, the sequence is changed to:

Table 6. Swapped MSB/LSB Output Sequence

MSB

LSB

Output Port

Y7

Y6

Y1

Y5

Y2

Y4

Y3

Y4

Y2

Y5

Y1

Y6

Y0

Y7

Internal Output data Y0

Table 7. QCIF Digital Output Format (YUV, beginning of line)

Pixel #

1

2

3

4

5

6

7

8

Y

Y0

U0,V0

Y1

U1,V1

Y2

U2,V2

Y3

U3,V3

Y4

U4,V4

Y5

U5,V5

Y6

Y7

UV

U6,V6

U7,V7

Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ...

– UV channel output U2 V3 U6 V7 U10 V11 ...

– Every line output data number is half(176 pixels) and only

one half line data (every other line, total 144 line) in one

frame will be output.

Table 8. QCIF Digital Output Format (RGB Raw Data, Beginning of Line)

Pixel #

1

2

3

4

5

6

7

8

Line 1

Line 2

B0

G0

G1

R1

B2

G2

G3

R3

B4

G4

G5

R5

B6

G6

G7

R7

1. Default RGB two line output mode:

– Y channel output G0 R1 G4 R5 G8 R9 ...

– UV channel output B0 G1 B4 G5 B8 G9 ...

– Every line output half data(176 pixels) and all

line(144 line) data in one frame will be output.

3. QCIF Resolution Digital Output Format

– Y channel output Y2 Y3 Y6 Y7 Y10 Y11 ...

– UV channel output U2 V3 U6 V7 U10 V11 ...

– Every line output data number is half (176 pixels)

and only one half line data (every other line, total

144 line) in one frame will be output.

2. YG two line output mode:

– Y channel output G0 R1 G4 R5 G8 R9 ...

– UV channel output B0 G1 B4 G5 B8 G9 ...

– Every line outputs half data (176 pixels) and all line

(144 line) data in one frame will be output.

12

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OV6620/OV6120

Table 9. RGB Raw Data Format

R\C

1

2

3

4

.

353

354

355

356

1

2

3

4

5

.

B

G

B

G

14

B

G

B

G

11

12

13

G

R

G

R

24

G

B

G

B

R

G

R

G

B

G

B

R

G

R

G

21

22

23

B

G

B

G

31

32

33

34

44

G

R

G

R

41

51

42

43

53

B

G

B

G

52

54

289

290

291

292

B

G

R

G

R

B

G

R

G

R

B

G

B

G

R

G

R

B

G

B

G

R

G

R

G

B

G

B

G

Notes:

A. Y port output data sequence: G R G R G R ... or G G G G ... ; UV port output data sequence: B G B G B G ... or B R B R ... ;

Array Color Filter Patter is Bayer-Pattern

B. Output Modes

16-bit Format (HREF total 292)

Default mode:

– 1st HREF Y channel output unstable data, UV output B₁₁G₁₂B₁₃G₁₄....

– 2nd HREF Y channel output G₂₁R₂₂G₂₃R₂₄..., UV output B₁₁G₁₂B₁₃G₁₄...

– 3rd HREF Y channel output G₂₁R₂₂G₂₃R₂₄..., UV output B₃₁G₂₃B₃₃G₃₄....

– Every line of data is output twice.

YG mode:

– 1st HREF Y and UV output unstable data.

– 2nd HREF Y channel output G₂₁G₁₂G₂₃G₁₄..., UV output B₁₁R₂₂B₁₃R₂₄...

– 3rd HREF Y is G₂₁G₃₂G₂₃G₃₄..., UV channel is B₃₁R₂₂B₃₃R₂₄...

– Every line data output twice.

One line mode:

– 1st HREF Y channel output B₁₁G₁₂B₁₃G₁₄...,

– 2nd HREF Y channel output G₂₁R₂₂G₂₃R₂₄...,

– UV channel tri-state.

8-bit Format (HREF total 292)

– 1st HREF Y channel output unstable data.

– 2nd HREF Y channel output B11 G21 R22 G12 ...

– 3rd HREF Y channel output B31 G21 R22 G32 ..., etc.

– PCLK timing is double and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice.

4-bit Nibble Mode Output Format

– Uses higher 4 bits of Y port (Y[7:4]) as output port.

– Supports YCrCb/RGB data, CCIR601/CCIR656 timing, Color/B&W.

– Output sequence: High order 4 bits followed by lower order 4 bits

Y0h Y0l Y1h Y1l ...

U0h U0l V0h V0l ...

For B/W or one-line RGB raw data, the output data clock speed is doubled. For color YUV, output clock is four times that of the 16-bit output

data. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2.

– Output sequence: U0h U0l Y0h Y0l V0h V0l Y1h Y1l ...

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

1.2.7 Slave Mode Operation

pulled high (Vcc). When a hardware reset occurs, the

OV6620/OV6120 sensor clears all registers or sets

them to their default values. Reset may also be initiated

The OV6620/OV6120 sensors can be programmable to

operate in slave mode configuration (COMI[6] = 1, de-

fault is master mode). HSYNC and VSYNC output sig-

nals are provided.

2

through the I C interface.

When used as a slave device, the external master must

provide the OV6620/OV6120 imager with the following:

1.2.10 Power Down Mode

Two methods are available for placing the OV6620/

OV6120 devices into power-down mode: hardware pow-

er down and I C/software power down.

1. System clock CLK to XCLK1 pin;

2. Horizontal sync, Hsync, to CHSYNC pin, positive

assertion;

3. Vertical frame sync, Vsync, to VSYNC pin,

positive assertion

2

To initiate hardware power down the PWDN pin (pin 9)

must be tied to high (+5VDC). When this occurs, the

OV6620/OV6120 internal device clock is halted and all

2

When in slave mode, the OV6620/OV6120 tri-states

CHSYNC (pin 42) and VSYNC (pin 16) output pins,

which may then be used as input pins. To synchronize

multiple devices, the OV6620/OV6120 image sensors

use external system clock, CLK, to synchronize external

horizontal sync, HSYNC, which is then used to synchro-

nize external vertical frame sync, Vsync. See Figure 5,

Slave Mode External Sync Timing for timing consider-

ations.

internal registers (except I C registers) are reset. In this

mode, current draw is less than 10uA.

2

Executing a software power down through the I C inter-

face suspends internal circuit activity, but does halt the

device clock. In this mode, current requirements drop to

less than 1mA.

1.2.11 Configuring the OV6620/OV6120 Image

Sensors

1.2.8 Frame Exposure Mode

Two methods are provided for configuring the OV6620/

OV6120 IC for specific application requirements.

The OV6620/OV6120 sensors support frame exposure

mode when programmed for Progressive Scan. FREX

(pin 4) is asserted by an external master device to set

exposure time. When FREX = 1, the OV6620/OV6120

pixel array will be quickly precharged. Based on the ex-

ternal master’s assertion of FREX, the OV6620/OV6120

devices capture the image. When the master de-asserts

FREX (FREX = 0), the video output data stream is deliv-

ered to the OV6620/OV6120 output port in a line-by-line

manner.

At power up, the OV6620/OV6120 sensor reads the sta-

tus of certain pins to determine what, if any, power up

default settings are requested. Once the reading of the

external pins is completed, the device configures its in-

ternal registers according to the specified pins. Not all

device functions are available for configuration through

external pin.

A more flexible and comprehensive method for configur-

2

It should be noted that FREX must active long enough

to ensure the complete image array has been pre-

charged.

ing the OV6620/OV6120 IC is to use its on-chip I C reg-

2

ister programming capability. The I C interface provides

access to all of the device’s programmable internal reg-

2

isters. See Section 3.1 I C Bus Protocol Format for fur-

When data is being output from the OV6620/OV6120

image sensor, care must be taken so as not to expose

the image array to light. This may affect the integrity of

the image data captured. A mechanical shutter synchro-

nized with the frame exposure rate can be used to min-

imize this situation. Frame exposure mode timing is

shown in Section Figure 6. Frame Exposure Timing be-

low.

2

ther details about using the I C interface on the

OV6620/OV6120 camera device.

1.2.9 Reset

The OV6620/OV6120 image sensor includes a RESET

pin (pin 2) which forces a complete hardware reset when

14

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

T

clk

hs

CLK

Hsync

1 line=472 * T

clk

Vsync

T

vs

1 frame = 625 * 472 * T

clk

Notes:

1. T_hs> 6 * T_clk(2) T_hs< T_vs< 472 * T_clk

2. Hsync period is 472 * CLK

3. Vsync period is 625 * 472 * CLK

4. OV6620 will be stable after 1 frame. (2nd Vsync).

Figure 5. Slave Mode External Sync Timing

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

T

set

Mechanical shutter off

FREX

T

in

T

hs

HSYNC

Precharge begin at rising edge of HSYNC

ARRAY

PRECHARGE

Array Exposure Period T

ex

Array Precharge

period T

1 Frame (292 line)

Valid Data

pr

DATA

OUTPUT

Invalid Data

Black Data

Head of Valid data

(8 line)

Next Frame

T

hd

VSYNC

HREF

Note: T_pr= 292* 4 * T_clk, T_clkis internal pixel period. For default 17.73 MHz, T_clk=112 us. If CLK[5:0] set to divided number, T_clkwill

increase accordingly.

T_exis array exposure time which is decided by external master device.

T_inis uncertain time due to using HSYNC rising edge synchronize FREX, T_in< T_hs

After FREX=0, there are 8 line data output before valid data output. T_hd= 4 * T_hs. Valid data is output when HRE

T_set= T_in+ T_pr+ T_ex. T_set> T_pr+ T_in. Because T_inis uncertain, so exposure time setting resolution is T_hs(one line).

Figure 6. Frame Exposure Timing

16

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OV6620/OV6120

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OV6620/OV6120

2. Electrical Characteristics

o

Table 10. DC Characteristics (0 C < TA < 85 C, Voltages referenced to GND)

Symbol

Supply

Descriptions

Max

Typ

Min

Units

V

Supply voltage- internal analog

(DEVDD,ADVDD,AVDD,SVDD,AOVDD,DVDD)

5.25

5.0

4.75

V

DD1

DD2

DD1

DD2

V

Supply voltage - internal digital &output digital

(DOVDD)

5.5

3.6

5.0

3.3

4.5

3.0

V

I

Supply Current (@ 50Hz frame rate & 5 volt digi-

tal I/O,25pf + 1TTL load on 16 bit data bus)

40

-

mA

Standby supply current

10

5

-

uA

Digital Inputs

V

input voltage LOW

input voltage HIGH

input capacitor

0.8

-

2.0

-

V

IL

IH

Cin

10

pF

Digital Outputs - standard load 25pf, 1.2kW to 3.0volts

V

output voltage HIGH

output voltage LOW

-

2.4

-

V

OH

OL

0.6

2

I C Inputs - 5k pull up + 100pf

V

SDA and SCL (V

=5V)

DD2

1.5

0

5

0

3

-0.5

3.0

V

IL

IH

IL

IH

SDA and SCL(V

=5V)

V

+ .5

dd

DD2

SDA and SCL (V

=3V)

1

-0.5

2.5

DD2

SDA and SCL(V

=3V)

3.5

DD2

18

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OV6620/OV6120

o

Table 11. AC Characteristics (T =25 C; Vdd=5V)

A

Symbol

Descriptions

Max

Typ

Min

Units

RGB/YCrCb output

Iso

maximum sourcing current

15

mA

DC level at zero signal

Y peak-peak 100% amplitude (without sync)

sync amplitude

1.2

1

0.4

V

Vy

ADC parameters

B

analog bandwidth

MHz

F diff

DLE

ILE

DC differential linearity error

DC integral linearity error

0.5

1

LSB

Table 12. Timing Characteristics

Symbol

Descriptions

Max

Typ

Min

Units

Oscillator & Clock in

f

frequency (XCLK1,XCLK2)

clock input rise/fall time

clock input duty cycle

30

5

17.734

50

10

45

MHz

ns

osc

t t

r , f

55

%

2

I C timing(400kbit/s)

t

Bus free time between STOP & START

SCL change after START status

SCL low period

-

1.3

0.6

1.3

0.6

0

ms

BUF

HD:SAT

LOW

SCL high period

HIGH

Data hold time

HD:DAT

SU:DAT

SU:STP

Data set-up time

0.1

0.6

Set-up time for STOP status

Digital timing

t

PCLK cycle time

16 bit operation

8 bit operation

pclk

-

112

56

ns

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Table 12. Timing Characteristics

Symbol

t t

Descriptions

Max

15

Typ

Min

Units

ns

PCLK rise/fall time

PCLK to data valid

PCLK to HREF delay

-

r, f

t

15

ns

pdd

phd

20

10

5

ns

Table 13. Zoom Video Port AC Parameters

Symbol

Parameter

PCLK fall timing

Min.

Max.

t1

t2

t3

t4

t5

t6

t7

t8

4 ns

8 ns

PCLK low time

50 ns

4 ns

PCLK rise time

8 ns

PCLK high time

50 ns

106 ns

10 ns

20 ns

1 us

PCLK period

Y/UV/HREF setup time

Y/UV/HREF hold time

VSYNC setup/hold time to HREF

Notes:

1. In Interlaced Mode, there are Even/Odd field different (t8). When In Progressive Scan Mode, only frame timing same as

Even field(t8).

2. After VSYNC falling edge, OV6620 will output black reference level, the line number is T_vs, which is the line number be-

tween the 1st HREF rising edge after VSYNC falling edge and 1st valid data CHSYNC rising edge. Then valid data, then

black reference, line number is T_ve, which is the line number between last valid data CHSYNC rising edge and 1st

CHSYNC rising edge after VSYNC rising edge. The black reference output line number is dependent on vertical window

setting.

3. When in default setting, T_vs= 14 * T_line, which is changed with register VS[7:0]. VS[7:0] step equal to 1 line.

4. When in default setting, T_ve= 4 * T_linefor Odd Field, T_ve= 3 * T_linefor Even Field, which is changed with register VE[7:0].

VE[7:0] step equal to 1 line.

20

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+0.010

0.440 ±0.005

0.040 ±0.003

0.060 -0.005

TYP.

0.040 ±0.007

31

42

TYP.

30

43

48

Bottom View

0.020 ±0.003

TYP.

19

6

R 0.0075

4 CORNERS

18

7

R 0.0075

48 PLCS

0.085 ±0.010

0.003

0.065 ±0.007

0.002

+0.012

0.030

±0.003

0.560 SQ. -0.005

0.430 SQ. ±0.005

0.350 SQ. ±0.005

0.015 ±0.002

0.020 ±0.002

42

43

31

42

43

30

Side View

48

1

19

6

7

6

19

7

18

0.006 MAX.

0.002 TYP.

Top View

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SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Array Center

(10.9 mil, 13.2 mil)

(276.9 µm, 335.3 µm)

1

DIE

Sensor

Array

Package Center

(0, 0)

Figure 7. OV6620/OV6120 Package Outline

Table 14. Ordering Information

Part Number

Description

Package

48 pin LCC

2

OV6620

OV6120

COLOR Image Sensor, CIF, Digital, I C Bus Control

2

B/W Image Sensor, CIF, Digital, I C Bus Control

OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or

design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein;

neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or reproduced, in any

form, without the prior written consent of OmniVision Technologies, Inc.

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OV6620/OV6120

2

3. I C Bus

2

V

. When the I C capability is enabled (I2CB = 1), the

Many of the functions and configuration registers in the

OV6620/OV6120 image sensors are available through

DD

OV6620/OV6120 imager operates as a slave device

that supports up to 400 kbps serial transfer rate using a

7-bit address/data transfer protocol .

2

the I C interface. The I C port is enabled by asserting

the I2CB line (pin 12) through a 10K ohm resistor to

1ST BYTE

2ND BYTE

3RD BYTE

S

SLAVE ID (7 BITS) RW

A

SUBADDRESS (8 BITS) A

DATA (8 BITS)

A

P

MSB

START

LSB=0

ACK

STOP

MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)

1ST BYTE

2ND BYTE

S

RW

A

P

SLAVE ID (7 BITS)

MSB

SUBADDRESS (8 BITS)

LSB=0

ACK

STOP

START

MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)

3RD BYTE

2ND BYTE

1ST BYTE

S

SLAVE ID (7 BITS) RW A

DATA (8 BITS)

A

DATA (8 BITS)

1

P

MSB

LSB=1

ACK

STOP

START

NO ACK IN

LAST BYTE

MASTER RECEIVE, SLAVE TRANSMIT (READ CYCLE)

SLAVE ID - 110CCC0X

S – START CONDITION

A – ACKNOWLEDGE BIT

– SLAVE TRANSMIT

CS2 (PIN 35)

CS1 (PIN 37)

CS0 (PIN 34)

– MASTER TRANSMIT

– MASTER INITIATE

P – STOP CONDITION

X – RW BIT, 1: READ, 0:WRITE

2

Figure 8. I C Bus Protocol Format

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2

3.1 I C Bus Protocol Format

2

In I C operation, the master must perform the following

operations:

Standard I C communications require only two pins:

SCL and SDA. SDA is configured as open drain for bi-

directional purpose. A HIGH to LOW transition on the

SDA while SCL is HIGH indicates a START condition. A

LOW to HIGH transition on the SDA while SCL is HIGH

indicates a STOP condition. Only a master can gener-

ate START/STOP conditions.

n Generate the start/stop condition

n Provide the serial clock on SCL

n Place the 7-bit slave address, the RW bit,

and the 8-bit subaddress on SDA

Except for these two special conditions, the protocol

that SDA remain stable during the HIGH period of the

clock, SCL. Each bit is allowed to change state only

when SCL is LOW (See Figure 9. Bit Transfer on the

The receiver must pull down SDA during the acknowl-

edge bit time. During the write cycle, the OV6620/

OV6120 device returns the acknowledgment and, dur-

ing read cycle, the master returns the acknowledgment

except when the read data is the last byte. If the read

data is the last byte, the master does not perform an

acknowledge, indicating to the slave that the read cycle

can be terminated. Note that the restart feature is not

supported here.

2

I C Bus and Figure 10. Data Transfer on the I C Bus

below).

2

The OV6620/OV6120 I C supports multi-byte write and

multi-byte read. The master must supply the subad-

dress. in the write cycle, but not in the read cycle.

Within each byte, MSB is always transferred first.

Read/write control bit is the LSB of the first byte.

SDA

DATA

CHANGE

ALLOWED

STABLE

SCL

2

Figure 9. Bit Transfer on the I C Bus

I

RW

SDA

SLAVE ID

SUB ADD

DATA

A

SCL

S

P

2

Figure 10. Data Transfer on the I C Bus

24

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Therefore, the OV6620/OV6120 sensor takes the read

subaddress from the previous write cycle. In multi-byte

write or multi-byte read cycles, the subaddress is auto-

matically increment after the first data byte so that con-

tinuous locations can be accessed in one bus cycle. A

multi-byte cycle overwrites its original subaddress;

therefore, if a read cycle immediately follows a multi-

byte cycle, you must insert a single byte write cycle that

provides a new subaddress.

The OV6620/OV6120 imager can be programmed to

one-of-eight slave ID addresses. Function pins CS[2:0]

pins 35, 37, 34, respectively).

Table 15. Slave ID Addresses

CS[2:0]

000

001

010

011

100

101

110

111

WRITE ID (hex)

READ ID (hex)

C0

C1

C4

C5

C8

C9

CC

CD

D0

D1

D4

D5

D8

D9

DC

DD

The OV6620/OV6120 sensors support both single chip

and multiple chip configurations. By asserting MULT

(pin 47) high, the sensor can be programmed for up to

8 slave ID addresses. Asserting MULT low configures

the OV6620/OV6120 imagers for single ID slave ad-

dress with address C0 for writes and address C1 for

reads. MULT is internally defaulted to a low condition.

and the third byte is the data associated with this regis-

ter. Writing to unimplemented subaddress is ignored.

In the read cycle, the second byte is the data associ-

ated with the previous stored subaddress. Reading of

unimplemented subaddress returns unknown.

3.2 Register Set

The table below provides a list and description of avail-

2

In the write cycle, the second byte in I C bus is the sub-

able I C registers contained in the OV6620/OV6120

address for selecting the individual on-chip registers,

image sensor.

2

Table 16. I C Registers

Subad-

dress

(hex)

Default

(hex)

Read/

Write

Register

Descriptions

AGC Gain Control

GC[7:6] - unimplemented bit, returns ‘X’ when read.

GC[5:0] – Storage for the current AGC Gain setting.

00

Gain[6:0]

00

RW

This register is updated automatically. If AGC is enabled, the internal control stores the optimal

gain value in this register. IF AGC is not enabled, a “00” is stored in this register.

Blue Gain Control

01

02

Blue[7:0]

Red[7:0]

80

RW

BLU[7] – “0” decrease gain, “1” increase gain.

BLU[6:0] – blue channel gain balance value.

Red Gain Control

RED[7] – “0” decrease gain, “1” increase gain.

RED[6:0] – red channel balance value.

Saturation Control

SAT[7:0] – saturation adjustment. “FFh”- highest, “00h”-lowest

03

04

05

Sat

Rsvd04

Cnt

80

XX

48

RW

-

reserved

Contrast Control

CTR[7:0] – contrast adjustment. “FFh”-highest, “00h”-lowest

RW

Brightness Control

BRT[7:0] – brightness adjustment. “FFh”-highest,“00h”-lowest

06

07

Brt

80

RW

Sharpness Control

SHP[7:4] – Threshold of sharpness. Range: 0~80mV, Step: 5 mV

SHP[3:0] – Sharpness control. Range: 0 ~ 8x, Step: 0.5x

Sharpness

C6

08

09

0A

0B

Rsvd08

Rsvd09

Rsvd0A

Rsvd0B

XX

-

reserved

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Version 1.11

25

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

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Default

Read/

Write

dress

(hex)

Register

Descriptions

(hex)

White Balance Background: Blue Channel

ABLU[7:6] - rsvd

ABLU[5] - Sign bit.

0C

AWB - Blue

20

R/W

“0” - decrease background blue component

“1” - increase background blue component

ABLU[4:0] - White balance blue ratio adjustment

White Balance Background: Red Channel

ARED[7:6] - rsvd

ARED[5] - Sign bit.

0D

0E

AWB - Red

COMR

20

R/W

RW

“0” - decrease background red component

“1” - increase background red component

ABLU[4:0] - White balance red ratio adjustment

Common Control R

0D

COMR[7] - Analog signal 2x gain control bit. “1” - Additional 2x gain, “0” - normal

COMR[6:0] - Reserved

Common Control S

COMS[7:6] - Reserved

COMS[5:4] - Black expanding level

“00” - 1.2V, “01” - 1.26V, “10” - 1.3V, “11” - 1.4V

COMS[3:2] - Set high threshold level

“00” - 1.9V, “01” - 2.0V, “10” - 2.1V, “11” - 2.2V

COMS[1:0] - Set low threshold level

“00” - 1.3V, “01” - 1.45V, “10” - 1.5V, “11” - 1.6V

0F

10

11

COMS

AEC

05

9A

00

RW

Automatic Exposure Control

AEC[7:0] - Set exposure time

Interlaced: T_ex= T_linex AEC[7:0]

Progressive: T_ex= T_linex AEC[7:0] x 2

R

Clock Rate Control

CLKRC[7:5] – Sync output polarity selection

“00” - HSYNC=Neg, CHSYNC=Neg, VSYNC=Pos

“01” - HSYNC=Neg, CHSYNC=Neg, VSYNC=Neg

“10” - HSYNC=Pos, CHSYNC=Neg, VSYNC=Pos

“11” - HSYNC=Pos, CHSYNC=Pos, VSYNC=Pos

CLKRC[5:0] – Clock prescaler

CLKRC

R

CLK = (CLK_main / ((CLKRC[5:0] + 1) x 2)) / 2

Common Control A

COMA[7] - SRST, “1” initiates soft reset. Initiate soft reset. All registers are set to default val-

ues and chip is reset to known state and resumes normal operation. This bit is automatically

cleared after reset.

COMA[6] - MIRR, “1” selects mirror image

12

COMA

24

RW

COMA[5] - VSFR, “1” enables AGC,

COMA[4] - Digital output format, “1” selects 8-bit: Y U Y V Y U Y V

COMA[3] - Select video data output: “1” - select RGB, “0” - select YCrCb

COMA[2] - Auto White Balance “1” - Enable AWB, “0” - Disable AWB

COMA[1] - Color Bar Test Pattern: “1” - Enable color bar test pattern

COMA[0] - reserved

Common Control B

COMB[7] - reserved

COMB[6] - reserved

COMB[5] - Select data format. “1” - Select 8-bit format, Y/CrCb and RGB is multiplexed to 8-bit

Y bus, UV bus is tri-stated, “0” - Select 16-bit format

COMB[4] - “1” - enable digital output in CCIR656 format

COMB[3] - CHSYNC output: “1” - Horizontal sync, “0” - composite sync

COMB[2] - “1” - Tristate Y and UV busses. “0” - enable both busses

COMB[1] - “1” - Initiate single frame transfer

COMB[0] - “1” - Enable auto adjust mode

13

COMB

01

RW

Common Control C

COMC[7] - reserved

COMC[6] - reserved

COMC[5] - QCIF digital output format selection. 1 - 176x144; 0 - 352x288.

COMC[4] - Field/Frame vertical sync output in VSYNC port selection: 1 - frame sync, only

ODD field vertical sync; 0 - field vertical sync, effect in Interlaced mode

COMC[3] - HREF polarity selection: 0 - HREF positive effective, 1 - HREF negative.

COMC[2] - gamma selection: 1 - RGB Gamma on ; 0 - gamma is 1.

COMC[1] - reserved

14

COMC

00

RW

COMC[0] - reserved

26

Version 1.11

14 May 1999

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Subad-

Default

Read/

Write

dress

(hex)

Register

Descriptions

(hex)

Common Control D

COMD[7] - reserved bit.

COMD[6] - PCLK polarity selection. “0” OV6620 output data at PCLK falling edge and data bus

will be stable at PCLK rising edge; “1” rising edge output data and stable at PCLK falling

edge. When OV6620 work as CCIR656 format, COMB4=1, this bit is disable and should

use PCLK rising edge latch data bus.

15

COMD

01

RW

COMD[5:1] - reserved bit.

COMD[0] - U V digital output sequence exchange control. 1 - UV UV ... for 16-bit, U Y V Y ...

for 8-bit; 0 - V U V U ... for 16Bit and V Y U Y ... for 8 Bit.

Field Slot Division

FSD[7:2] - Field interval selection. Odd Even mode defined by FD[1:0]

000000 - disable digital data output, only output black reference level.

000001 - divide to 2 slots, HREF is active one in every 2 field/frame

000010 - divide to 4 slots, HREF is active one in every 4 field/frame

000100 - divide to 8 slots, HREF is active one in every 8 field/frame

001000 - divide to 16 slots, HREF is active one in every16 field/frame

010000 - divide to 32 slots, HREF is active one in every 32 field/frame

100000 - divide to 64 slots, HREF is active one in every 64field/frame

FSD[1:0]- field mode selection. Each frame consists of two fields: Odd & Even, these bits

defines the assertion of HREF in relation to the two fields.

16

FSD

03

RW

00 - OFF mode; HREF is not asserted in both fields, one exception is the single frame

transfer operation (see the description for the register 13)

01 - ODD mode; HREF is asserted in odd field only.

10 - EVEN mode; HREF is asserted in even field only.

11 - FRAME mode; HREF is asserted in both odd field and even field. FD[7:2] useless.

Horizontal HREF Start

HS[7:0] - selects the starting point of HREF window, each LSB represents two pixels for CIF

resolution mode, one pixels for QCIF resolution mode, this value is set based on an internal

column counter, the default value corresponds to 352 horizontal window. Maximum window

size is 356. see window description below. HS[7:0] programmable range is [38]- [EB], and

should less than HE[7:0]. HS[7:0] should be programmable to value larger than or equal to

[38]. Value larger than [EC] is invalid. See window description below.

17

18

HREFST

38

RW

Horizontal HREF End

HE[7:0] - selects the ending point of HREF window, each LSB represents two pixels for full

resolution and one pixels for QCIF resolution, this value is set based on an internal column

counter, the default value corresponds to the last available pixel. The HE[7:0]

programmable range is [39] - [EC]. HE[7:0] should be larger than HS[7:0] and less than or

equal to [EC]. Value larger than [EC] is invalid. See window description below.

HREFEND

EA

Vertical Line Start

VS[7:0] - selects the starting row of vertical window, in full resolution mode, each LSB

represents 1 scan line in one frame. see window description below. Min. is [03], max. is [93]

and should less than VE[7:0].

19

1A

VSTRT

VEND

03

92

RW

Vertical Line End

VE[7:0]- selects the ending row of vertical window, in full resolution mode, each LSB

represents 1 scan line in one frame, see window description below. Min. is [04], max. is [94]

and should larger than VS[7:0].

Pixel Shift

PS[7:0] - to provide a way to fine tune the output timing of the pixel data relative to that of

HREF, it physically shifts the video data output time late in unit of pixel clock as shown in the

figure below. This function is different from changing the size of the window as is defined by

HS[7:0] & HE[7:0] in register 17&18.

1B

PSHFT

00

RW

Higher than default number shifts the pixel in delay(right) direction, the highest number is

“FF”. so maximum shift number is: Late: 256 pixels.

Manufacture ID Byte: High

MIDH[7:0] - read only, always returns “7F” as manufacturer’s ID no.

1C

1D

MIDH

MIDL

7F

A2

R

Manufacture ID Byte: Low

MIDL[7:0] - read only, always returns “A2” as manufacturer’s ID no.

1E

1F

Rsvrd1E

Rsvrd1F

C4

04

R

reserved

14 May 1999

Version 1.11

27

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Subad-

Default

Read/

Write

dress

(hex)

Register

Descriptions

(hex)

Common Control E

COME[7] - HREF pixel number selection. “1” - HREF include 704 PCLK, every data output

twice.

COME[6] - reserved.

COME[5] - “1” First stage aperture correction enable. Correction strength will be decided by

register [07]. “0” disable first stage aperture correction.

COME[4] - “1” Second stage aperture correction enable. Correction strength and threshold

value will be decided by COMF[7] ~ COMF[4].

COME[3] - AWB smart mode enable. 1 - Drop out pixel when compare pixel red, blue and

green component level to change register [01] and [02], which luminance level is higher than

presetting level and lower than presetting level, this two level is set by register [0F].

0 - calculate all pixels to get AWB result. Valid only when COMB[0]=1 and COMA[2]=1

COME[2] - AWB stop when field/frame image average luminance level is lower than a

presetting level enable. 1 - enable stop AWB when image luminance level is low. 0 - AWB is

independent with field/frame luminance level. Valid only when COMB0=1 and COMA[2]=1.

Average compare level is set by GAM[7:5].

20

COME

00

RW

COME[1] - AWB fast/slow mode selection. “1” - AWB is always fast mode, that is register [01]

and [02] is changed every field/frame. “0” AWB is slow mode, [01] and [02] change every 16/

64 field/frame decided by COMK[1]. When AWB enable, COMA[2]=1, AWB is working as

fast mode at first 1024 field/frame, than as slow mode later.

COME[0] - Digital output driver capability increase selection: “1” Double digital output driver

current; “0” low output driver current status.

Y Channel Offset Adjustment

YOFF[7] - Offset adjustment direction 0 - Add Y[6:0]; 1 -Substrate Y[6:0].

YOFF[6:0] -Y channel digital output offset adjustment. Range: +127mV ~ -127mV. If

COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value

to this register with I²C has no effect. If COMG[2]=1, Y channel offset adjustment will use

21

YOFF

80

RW

the register stored value which can be changed by I²C. If COMF[1]=0, this register has no

adjustment effect to A/D output data. If output RGB raw data, this register will adjust R/G/B

data.

U Channel Offset Adjustment

UOFF[7]: - Offset adjustment direction: 0 - Add U[6:0]; 1 -Substrate U[6:0].

UOFF[6:0] - U channel digital output offset adjustment. Range: +128mV ~ -128mV. If

COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value

22

23

UOFF

REFC

80

04

RW

to this register with I²C has no effect. If COMG[2]=1, U channel offset adjustment will use

the register stored value which can be changed by I²C. If COMF[1]=1, this register has no

effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data.

Reference Control

REFC[7:6] - Select different crystal circuit power level (11 = minimum).

REFC[5:4] - reserved

REFC[3:0]: Reference Voltage range selection. 2.5V - 3.5V and step is 0.0625V.

Automatic Exposure Control: Bright Pixel Ratio Adjustment

AEW[7:0] - Used as calculate bright pixel ratio. OV6620 AEC algorithm is count whole field/

frame bright pixel (its luminance level is higher than a fixed level) and black pixel (its

luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as

the ratio defined by register [25] and [26], image stable. This register is used to define bright

pixel ratio, default is 25%, each LSB represent step: 1.3% Change range is: [01] ~ [CA];

Increase AEW[7:0] will increase bright pixel ratio. For same light condition, the image

brightness will increase if AEW[7:0] increase.

24

AEW

33

RW

Note: AEW[7:0] must combine with register [26] AEB[7:0]. The relation must be as

follows:

AEW[7:0] + AEB[7:0] > [CA].

Automatic Exposure Control: Black Pixel Ration Adjustment

AEB[7:0] - used as calculate black pixel ratio. OV6620 AEC algorithm is count whole field/

frame bright pixel (its luminance level is higher than a fixed level) and black pixel (its

luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as

the ratio defined by register [25] and [26], image stable. This register is used to define black

pixel ratio, default is 75%, each LSB represent step: 1.3%; Change range is: [01] ~ [CA];

Increase AEB[7:0] will increase black pixel ratio. For same light condition, the image

brightness will decrease if AEB[7:0] increase.

25

AEB

97

RW

Note: AEB[7:0] must e combined with register [25] AEW[7:0]. The relation must be as

follows: EW[7:0] + AEB[7:0] > [CA].

28

Version 1.11

14 May 1999

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Subad-

Default

Read/

Write

dress

(hex)

Register

Descriptions

(hex)

Common Control F

COMF[7:6] - Second aperture correction threshold selection.

[00] - Difference of neighbor pixel luminance is larger than 8 mV, correction on.

[01] - 16 mV.

[10] - 32 mV.

[11] - 64 mV.

COMF[5:4] - Second aperture correction strength selection.

[00] and [01] - Strength is 50% of difference of neighbor pixel luminance.

[10] - 100%.

26

COMF

B0

RW

[11] - 200%.

COMF[3] - UV BLC swap. “1” swap; “0” no swap.

COMF[2] - Digital data MSB/LSB swap. “1” LSB->Bit7, MSB->Bit0; “0” normal.

COMF[1] - “1” A/D Black level calibration enable. “0” Disable A/D BLC.

COMF[0] - “1” Output first 4 line black level before valid data output. HREF number will

increase 4 relatively. “0” no black level output.

Common Control G

COMG[7] - reserved

COMG[6] - reserved.

COMG[5] - Select CKOUT pin output V flag. 1 - CKOUT output V flag signal. CKOUT=1,

means related UV channel output V component (or Red component), CKOUT=0 pointed to

U component (or Blue component). 0 - CKOUT output buffered XCLK2

COMG[4] - reserved.

COMG[3] - reserved

27

COMG

A0

RW

COMG[2] - “1” A/D offset adjustment manually mode enable: 1 - A/D data will be add/substrate

a value defined by register [21] and [22], which content is written by I²C. 0 - A/D data will be

added/substrate a value defined by register [21] and [22], which is updated by internal

circuit.

COMG[1] - Digital output full range selection. OV6620 output data value range is [10] - [F0], if

COMG[1] -1, range change to [01] - [FE] with signal overshoot and undershoot level.

COMG[0] - reserved.

Common Control H

COMH[7]: - “1” selects One-Line RGB raw data output format, “0” selects normal two-line RGB

raw data output, effective only in Progressive Scan mode.

COMH[6]: - “1” enable Black/White mode. When OV6620 working as BW camera, its vertical

resolution will be higher than color mode. At this mode, can’t set OV6620 working at 8 bit

output mode. OV6620 output data YUV/RGB from Y port. UV port will be tri-state. COMB[5]

and COMB[4] will be set to “0”. “0” normal color mode.

COMH[5]: - reserved.

COMH[4]: - Freeze AEC/AGC value, effective only when COMB0=1. “1” - register [00] and [10]

will not be updated and hold latest value. “0” - AEC/AGC normal working status.

COMH[3]: - AGC disable. 1 - when COMB[0]=1 and COMA[5]=1, internal circuit will not update

register [00], register [00] will kept latest updated value before COMH[3]=1. 0 - when

COMB0=1 and COMA[5]=1, register [00] will be updated by internal algorithm.

COMH[2]: - RGB raw data output YG format: 1 - Y channel G, UV channel B R; 0 - Y channel:

G R G R..., UV channel B G B G....

28

COMH

01

RW

COMH[1]: - Gain control bit. “1” Double PreAmp gain to 12dB. “0” PreAmp gain is 6dB.

COMH[0]: - High gain mode. “1” - AGC maximum gain is 24dB. AGC step is 1/8. “0” AGE

maximum gain is 18dB, AGC step is 1/16. Only effective when COMB[0]=1, COMA[5]=1 and

COMH[3]=0.

Common Control I

COMI[7]: - AEC disable. “1” If COMB[0]=1, AEC stop and register [10] value will be held at last

AEC value and not be updated by internal circuit. “0” - if COMB[0]=1, register [10] value will

be updated by internal circuit

COMI[6]: - Slave mode selection. “1” slave mode, use external Sync and Vsync; “0” master

mode

COMI[5]: - reserved

29

COMI

00

RW

COMI[4]: - reserved

COMI[3]: - Central 1/4 image area rather whole image used to calculate AEC/AGC. “0” use

whole image area to calculate AEC/AGC.

COMI[2]: - reserved

COMI[1:0] - Version flag. For Version A, value is [00], these two bits can only be read.

Frame Rate Adjust High

FRARH[7] - Frame Rate adjustment enable bit. “1” Enable.

FRARH[6] - reserved

FRARH[5] - Highest 1bit of frame rate adjust control byte. see explanation below.

2A

FRARH

84

RW

FRARH[4] - reserved

FRARH[3] - Y channel brightness adjustment enable. When COMF[2]=1 active.

FRARH[2] - reserved

FRARH[1] - “1” When in Frame exposure mode, only One frame data output.

FRARH[0] - reserved

14 May 1999

Version 1.11

29

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Subad-

Default

Read/

Write

dress

(hex)

Register

Descriptions

(hex)

Frame Rate Adjust Low

FRARL[7:0] - Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment resolution

is 0.21%. Control byte is 10 bit. Every LSB equal decrease frame rate 0.21%. Range is

0.21% - 109%. IF frame rate adjustment enable, COME7 must set to “0”.

2B

2C

FRARL

5E

88

RW

Rsvd2C

reserved

Common Control J

COMJ[7:5] - reserved

COMJ[4] - Enable auto black expanding mode.

COMJ[3] - “1” = White Balance update when AGC/AEC stable. “0” = White Balance register

update independent with AEC/AGC.

COMJ[2] - Band filter enable. After adjust frame rate to match indoor light frequency, this bit

enable a different exposure algorithm to cut light band induced by fluorescent light.

COMJ[1] - reserved

2D

COMJ

03

RW

COMJ[0] - A/D U and V BLC separate mode. “1” = U and V offset cancelled by different

register. “0” = U V offset cancelled by one common register [2E].

V Channel Offset Adjustment

VCOFF[7]: Offset adjustment direction: “0” = Add V[6:0]; “1” = Substrate V[6:0].

VCOFF[6:0] - V channel digital output offset adjustment. Range: +128mV ~ -128mV. If

COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value

to this register with I²C has no effect. If COMG[2] =1, V channel offset adjustment will use

2E

VCOFF

80

RW

the register stored value which can be changed by I²C. If COMF[1] =1, this register has no

effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data.

2F-32

33

Rsvd2F-Rsvd32

CPP

xx

-

Reserved

Color Processing Parameter Control

CPP[7:6] - reserved

CPP[5] - Luminance gamma on/off. “1” - luminance gamma on; “0” - luminance gamma is 1.

00

RW

CPP[4:0] - reserved

Bias Adjustment

BIAS[7:6] - A/D reference level adjustment. [00] - 110% internal full signal range; [01] - 120%,

[10] - 130%, [11] - 140%.

34

BIAS

A2

RW

BIAS[5:0] - reserved

35

36

37

Rsvd35

Rsvd36

Rsvd37

80

48

41

RW

reserved

Common Control K

COMK[7] - HREF edge latched by PCLK falling edge (When COMD[6] = 0). “0” HREF edge is

10 ns after PCLK rising edge.

COMK[6] - Output port drive current additional 2x control bit.

COMK[5] - reserved.

COMK[4] - ZV port Vertical timing selection. “1” VSYNC output ZV port vertical sync signal.

“0” = normal TV vertical sync signal.

COMK[3] - Quick stable mode when camera mode change. After relative control bit set, the

first VS will be the stable image with suitable AEC/AWB setting. “0” - slow mode, after mode

change need more field/frame to get stable AEC/AWB setting image.

COMK[2] - reserved

38

COMK

81

RW

COMK[1] - AWB stable time selection when in slow mode. “1” - 4 times less time needed to get

stable AWB setting when in slow AWB mode.

COMK[0] -reserved.

Common Control L

COML[7] - reserved

COML[6] - PCLK output timing selection. 1 -- PCLK valid only when HREF is high; 0 -- PCLK is

free running.

COML[5] - Vertical sync selection, 1 -- Same period between 1st HREF and VS falling edge in

two field; 0 - Different timing period between 1st HREF and VS falling edge

COML[4] - “1” select CHSYNC output from HREF port. “0” normal

COML[3] - “1” select HREF output from CHSYNC port. “0” normal

COML[2] - Tristate all control signal output (FODD, CHSYNC, HREF, PCLK)

COML[1] - Highest 1 bit of horizontal sync starting position, combined with register [3A]

COML[0] - Highest 1 bit of horizontal sync ending position, combined with register [3B]

39

COML

00

RW

Horizontal Sync Start Position

3A

3B

HSST

0F

3C

RW

HSST[7:0] - lower 8 bit of horizontal sync starting position, combined with register bit of

COML[1], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must less than HSST[8:0]

Horizontal Sync End Position

HEND[7:0] - lower 8 bit of horizontal sync ending position, combined with register bit of

HSEND

COML[0], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must be larger than HSST[8:0]

30

Version 1.11

14 May 1999

Advanced Information

Preliminary

OMNIVISION TECHNOLOGIES, Inc.

SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS

OV6620/OV6120

Subad-

dress

(hex)

Default

(hex)

Read/

Write

Register

Descriptions

Common Control M

COMM[7:5] - Select minimum AEC number if Banding filter enable. [000] -- 1 field, [001] -- 1/2;

[010] -- 1/4; [011] -- 1/8; [100] -- 1/16; [101]~[111] -- 1/32;

COMM[4] - AEC/AGC change mode selection

COMM[3] - AEC/AGC change mode selection

COMM[2] - AEC/AGC change fastest mode

3C

3D

3E

COMM

21

08

80

RW

COMM[1] - AEC/AGC change fast mode

COMM[0] - AEC/AGC change slowest mode

Common Control N

COMN[7] - Enable one frame drop when AEC change to keep data valid when Banding filter

mode enable.

COMN[6:4] - reserved

COMN[3] - Enable 50 Hz PAL video timing, so VTO analog signal can be displayed on TV

COMN[2:0] - reserved

COMN

COMO

Common Control O

COMO[7] - Input main clock divided by 2 or 4 selection. 1 -- 2; 0 -- 4

COMO[6:5] - reserved

COMO[4] - Select 4 bit nibble mode output

COMO[3] - reserved

COMO[2] - Enable Minimum exposure time is 4 line. Default is 1 line

COMO[1] - reserved

COMO[0] - reserved

Common Control P

COMP[7] - reserved

COMP[6] - Output main clock output from FODD port

COMP[5] - reserved

COMP[4] - Software whole chip power down enable, can be waked up by disable this bit

COMP[3:2] - reserved

COMP[1] - CCIR656 output control

3F

40

4D

COMP

Rsvd40 - Rsvd4C

YMXA

02

XX

02

RW

-

COMP[0] - Reset internal timing circuit without reset AEC/AGC/AWB value

reserved

YUV Matrix Control (Main)

YMXA[7:5] - reserved

YMXA[4:3] - YUV/YCrCB selection:

[00] U = u, V = v

[01] U = 0.938u, V = 0.838v

[10] U = 0.563u, V = 0.714v

[11] U = 0.5u, V = 0.877v

YMXA[2:0] - Reserved

RW

4E

4F

50

Rsvd4E

YMXB

XX

00

-

RW

-

reserved

YUV Matrix Control (Secondary)

YMXB[7:6] - Y channel delay selection: 0 ~ 3 tp

YMXB[5:4] - UV delay selection: 0 ~ 6 tp

YMXB[3:2] - Select UV average mode. [00] & [10]: U0/V0 (no delay); [01] -- 3 point average;

[11] -- 5 point average mode

YMXB[1:0] - Color killer control: [00]:2.4v;[01]:2.6v;[10]:2.8v;[11]:3.0v

Rsvd50 - Rsvd53

XX

reserved

14 May 1999

Version 1.11

31

厂商	型号	描述	页数
ETC	OV6120	单片CMOS CIF彩色数码摄像机[ SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA ]	31 页
ETC	OV6130	单片CMOS CIF彩色数码摄像机[ SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA ]	29 页
ETC	OV6630	单片CMOS CIF彩色数码摄像机[ SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA ]	29 页
OMNIVISION	OV6680	在3G手机视频会议摄像机最佳的低光灵敏度和像素表现[ optimal low-light sensitivity and pixel performance for video conferencing cameras in 3G mobile phones ]	2 页