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OZ968G

型号：

OZ968G

描述：

SMBus智能逆变控制器[ SMBus Smart Inverter Controller ]

品牌：

ETC[ ETC ]

页数：

6 页

PDF大小：

50 K

下载PDF手册
OZ968  
SMBus Smart Inverter Controller  
GENERAL DESCRIPTION  
FEATURES  
The OZ968 is a unique single-stage, high-  
efficiency, CCFL backlight controller. It drives a  
•
•
Single-stage power conversion  
Constant frequency design eliminates inter-  
ference with LCDs  
Built-in open-lamp protection and short-  
circuit protection  
Reliable 2-winding transformer design elimi-  
nates arcing failures and the need for fold-  
back wiring  
zero-voltage-switching circuit and provides a  
near sinusoidal output voltage and current wave-  
forms for a CCFL backlight. Typical operating  
frequency ranges from 30KHz to 100KHz. These  
advances drive the OZ968 beyond comparable  
conventional inverter designs with two power  
conversion stages (one operates at a variable  
frequency, the other at a constant frequency).  
•
•
•
32-level dimming and 256-level contrast  
control via SMBus  
•
•
High efficiency, 90% typical  
Supports both floating secondary and  
grounded secondary designs  
Operating in a PWM push-pull drive, the trans-  
former in an OZ968 backlight inverter requires  
only one primary winding and one secondary  
winding. The secondary winding requires no fold-  
back treatment.  
ORDERING INFORMATION  
The OZ968 supports a bi-directional, two-wire  
bus, data transmission protocol to control dim-  
ming (32 levels) and contrast (256 levels). Sup-  
ply current is 1mA in active mode, 150µA in  
standby mode.  
OZ968G - 16-pin plastic SOP  
The OZ968 is available in a 16-pin SOP pack-  
age. It is specified over the commercial tempera-  
o
o
ture range 0 C to +70 C.  
TYPICAL APPLICATION CIRCUIT  
20V  
SMBCLCK  
SMBDATA  
ENABLE  
5V  
C1  
47u/  
25v  
CONTRAST  
OZ968  
C5  
C6  
1:40  
0.1u  
1
2
3
4
5
6
7
8
FB  
VDD 16  
SCP 15  
22p/3KV  
R3  
C2  
Q4  
3.3k  
3904  
CMP  
SST  
ADJ  
CNT  
RT  
CCFL  
0.1u  
Q2  
VSEQ 14  
SMBD 13  
SMBC 12  
OVP 11  
C3  
Si4559EY/P  
D1  
0.47u  
C7  
Q3  
1N4148  
3906  
R6  
2.2k  
R4  
D2  
4.7u  
200k  
1N4148  
Q1  
Si4559EY/  
N
R8  
Q5  
3904  
R5  
R7  
CT  
PDR 10  
R10  
R9  
1k  
10k  
0.1ohm  
R2  
100k  
10k  
120k  
C4  
220p  
GND  
NDR  
9
Figure 1. Typical Application Circuit  
06/15/00  
Copyright 1999 by O2Micro  
OZ968-SF-1.5  
All Rights Reserved  
Page 1  
U.S. Patent #5,619,402  
OZ968  
FUNCTIONAL BLOCK DIAGRAM  
IBIAS  
REF  
Qp  
clki  
RT  
OSC  
ramp  
clk  
CT  
set  
Break  
PDR  
NDR  
Before  
Make  
F/F  
Reset  
Comparator  
+
-
Qn  
reset  
FB  
160K  
-
+
EA  
40K  
ADJ  
CMP  
+
OVP  
OVP  
-
See P.8,  
vd  
iss  
poff  
Section 9  
Slow  
Start  
SST  
CNT  
pofbr  
lcd_susp  
pofcnt  
Protections  
+
SCP  
-
SCP  
csusp  
bsusp  
Brightness  
DAC  
Contrast  
DAC  
0.5V  
SMBC  
SMBD  
VSEQ  
8bit  
data  
5bit  
data  
xolp_ok  
xscp_ok  
SMB INTERFACE  
CLAMP  
OVP  
OVP  
Figure 2. Functional Block Diagram  
OZ968-SF-1.5  
Page 2  
OZ968  
PIN CONFIGURATION  
Pin No.  
Name  
FB  
CMP  
SST  
Description  
Current sense feedback.  
Compensation for the current sense feedback.  
1
2
3
Soft start in two steps. Two-interval current sources of 50µA and 0.6µA  
provide 1:26.6 ratio between the two time intervals of soft start. Connect a  
capacitor between this pin and the ground to adjust the soft-start timing.  
The output of the brightness D/A converter. The brightness has 32 adjust-  
able levels. The default range is between 0.9V to 2.5V.  
The output of the contrast D/A converter. The contrast has 256 levels from  
0.8V to 2.8 V (8mV per step). This output has a current capability of up to  
2mA.  
4
5
ADJ  
CNT  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
RT  
CT  
Timing resistor.  
Timing capacitor. CT and RT set the clock frequency. Fs = 1.60 / (RT * CT).  
Ground.  
Gate drive output for the N-MOSFET.  
Gate drive output for the P-MOSFET.  
Over-voltage protection sense input.  
SMBus Clock Input/Output  
SMBus Data Input/Output.  
Vee power sequence input.  
Short-circuit protection sense input.  
GND  
NDR  
PDR  
OVP  
SMBC  
SMBD  
VSEQ  
SCP  
VDD  
Supply voltage input.  
ABSOLUTE MAXIMUM RATINGS  
VDD  
7.0 V Logic inputs  
-0.3 V to VDD+0.3 V  
GND  
+/- 0.3 V  
o
Storage temp.  
Operating temp.  
Operating junction temp.  
-55 to 150 C  
o
0 to 70 C  
o
150 C  
RECOMMENDED OPERATING RANGE  
VDD  
Fosc  
Rt  
4.75 V to 5.25 V  
30 KHz to 100 KHz  
50 K to 150 K  
OZ968-SF-1.5  
Page 3  
OZ968  
FUNCTIONAL SPECIFICATIONS  
Parameter  
Test Conditions  
Limits  
Unit  
VDD = 5V, Tj =25, Test Circuit  
Min  
Typ  
Max  
Oscillator  
Initial accuracy  
Temp. stability  
Line regulation  
Error Amplifier  
Bias current  
Ct = 270pF, Rt = 100k  
TA = 0oC to 70oC  
54  
-
59  
200  
2
64  
500  
3
KHz  
ppm/ oC  
%
4.5 V < VDD <5.5V  
-
-
2.5  
5
µA  
mV  
dB  
Input offset voltage  
Open loop voltage gain  
Unity gain bandwidth  
Dimming D/A Output (ADJ – floating)  
Maximum level  
-
60  
-
2.0  
80  
5.0  
-
-
2.0  
MHz  
2.40  
0.8  
2.40  
-
2.50  
0.9  
2.5  
10  
2.65  
1.0  
2.65  
-
V
V
V
Minimum level  
Power-on reset default  
Settling time  
µs  
D/A output levels  
Contrast D/A Output  
Maximum level  
-
32  
-
2.70  
0.75  
0.75  
-
2.80  
0.80  
0.80  
10  
2.95  
0.90  
0.90  
-
V
V
V
Minimum level  
Power-on reset default  
Settling time  
µs  
mA  
Maximum output current  
Load regulation  
-
-
-
2.0  
50  
2.2  
100  
-
mV/mA  
D/A output levels  
256  
Under-voltage Lockout  
Power-on Voltage  
3.8  
-
4.0  
0.3  
4.2  
-
V
V
Hysteresis  
Break-before-Make  
Delay (between NDR and PDR)  
Supply  
100KHz, 800pF loading  
100KHz, 800pF loading  
-
400  
-
ns  
Supply current – Standby Mode  
-
-
150  
1
-
µA  
Supply current – Active Mode  
Output (NDR and PDR)  
Output high voltage  
2
mA  
VDD = 5.0V  
VDD = 5.0V  
VDD = 5.0V  
4.75  
-
-
-
0.25  
-
V
V
Ω
Output low voltage  
-
-
Output resistance  
50  
OZ968-SF-1.5  
Page 4  
OZ968  
TWO-WIRE BUS REGISTER DESCRIPTION  
The following register map describes the SMBus interface between SMBus Host and the OZ968  
Register Map  
For Write commands.  
Function  
Slave Address  
(7-bit)  
Register Index  
Data  
(Hex)  
A9  
AA  
Contrast  
Brightness  
0101 000  
0101 000  
byte  
byte  
Contrast (A9)  
SMBus Protocol: Read or Write Byte  
Input/Output: Byte -- bit flags mapped as follows:  
Bit #  
7:0  
Name  
D7-D0  
R/W  
r/w  
Default  
0000  
0000  
Description  
Bits D7-D0 contain the contrast level setting. When D7-D0  
= FF, the CNT pin of the OZ968 outputs 2.8V. When D7-  
D0 = 00, the CNT pin outputs 0.8V.  
Brightness (AA)  
SMBus Protocol: Read or Write Byte  
Input/Output: Byte -- bit flags mapped as follows:  
Bit #  
7:0  
Name  
D7-D0  
R/W  
r/w  
Default  
0000  
0000  
Description  
Bits D7-D0 contain the brightness level setting. When D7-  
D0 = FF, the OZ968 inverter outputs miniimum brightness.  
When D7-D0 = 00, the OZ968 inverter outputs maximum  
brightness.  
OZ968-SF-1.5  
Page 5  
OZ968  
PACKAGE INFORMATION  
DIM  
INCHES  
MILLIMETERS  
MIN  
MAX  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
A
A1  
B
C
D
E
e
0.0532  
0.0040  
0.013  
0.0075  
0.3859  
0.1497  
0.0688  
0.0098  
0.020  
0.0098  
0.3937  
0.1574  
SOP-16  
PACKAGE  
E H  
0.050 BCS.  
1.27 BCS.  
H
L
α
0.2284  
0.016  
0°  
0.2440  
0.050  
8°  
5.80  
0.40  
0°  
6.20  
1.27  
8°  
D
C
D
A
L
B
e
A1  
OZ968-SF-1.5  
Page 6  
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