TXS0102
2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR
FOR OPEN-DRAIN APPLICATIONS
www.ti.com
SCES640–JANUARY 2007
FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
B1
1
2
3
4
8
7
6
5
B2
GND
VCCA
A2
1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on
B port (VCCA ≤ VCCB
)
VCCB
OE
A1
VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance
State
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
YZP PACKAGE
(BOTTOM VIEW)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D1
C1
B1
A1
D2
C2
B2
A2
4 5
3 6
2 7
1 8
A2
A1
ESD Protection Exceeds JESD 22
VCCA
OE
–
A Port
VCCB
GND
B2
–
–
–
2500-V Human-Body Model (A114-B)
B1
250-V Machine Model (A115-A)
1500-V Charged-Device Model (C101)
abc
abc
abc
abc
–
B Port
–
–
–
8-kV Human-Body Model (A114-B)
250-V Machine Model (A115-A)
1500-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This two-bit noninverting translator uses two separate configurable power-supply rails. The A port is designed to
track VCCA. VCCA accepts any supply voltage from 1.65 V to 3.6 V. The B port is designed to track VCCB. VCCA
must be less than or equal to VCCB. VCCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for
low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
Reel of 3000
TXS0102YZPR
Reel of 3000
Tube of 250
Reel of 3000
TXS0102DCTR
TXS0102DCTT
TXS0102DCUR
NFEZ_ _ _
–40°C to 85°C
SSOP – DCT
NFEZ _ _ _
_ _ NFE
VSSOP – DCU
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.