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8XL196NP

型号：

8XL196NP

描述：

商业CHMOS 16位微控制器[ COMMERCIAL CHMOS 16-BIT MICROCONTROLLER ]

品牌：

INTEL[ INTEL ]

页数：

34 页

PDF大小：

532 K

下载PDF手册
8XL196NP COMMERCIAL  
CHMOS 16-BIT MICROCONTROLLER  
n 14 MHz Operation at 2.7–3.3 Volts  
n Chip-select Unit  
— 6 Chip Select Pins  
n 1 Mbyte of Linear Address Space  
n Optional 4 Kbytes of ROM  
n 1000 Bytes of Register RAM  
n Register-register Architecture  
n 32 I/O Port Pins  
— Dynamic Demultiplexed/Multi-  
plexed Address/Data Bus for Each  
Chip Select  
— Programmable Wait States (0, 1, 2,  
or 3) for Each Chip Select  
— Programmable Bus Width (8- or 16-  
bit) for Each Chip Select  
n 16 Prioritized Interrupt Sources  
n 4 External Interrupt Pins and NMI Pin  
— Programmable Address Range for  
Each Chip Select  
n 2.0µs 16 × 16 Unsigned Multiplication  
n 3.4µs 32/16 Unsigned Division  
n 2 Flexible 16-bit Timer/Counters with  
Quadrature Counting Capability  
n 3 Pulse-width Modulator (PWM) Outputs  
n 100-pin SQFP or 100-pin QFP Package  
with High Drive Capability  
n Complete System Development  
n Full-duplex Serial Port with Dedicated  
Support  
Baud-rate Generator  
n High-speed CHMOS Technology  
n Peripheral Transaction Server  
n Event Processor Array (EPA) with 4 High-  
speed Capture/Compare Channels  
®
The 8XL196NP is a member of Intel’s 16-bit MCS 96 microcontroller family. The device features 1 Mbyte of  
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch  
between multiplexed and demultiplexed operation. When operating at 14 MHz in demultiplexed mode, the  
8XL196NP can access a 200 ns memory device with zero wait states. The 8XL196NP is available without  
ROM (80L196NP) or with 4 Kbytes of ROM (83L196NP).  
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-  
ment of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such  
products. Information contained herein supersedes previously published specifications on these devices from Intel.  
© INTEL CORPORATION, 1996  
March 1996  
Order Number: 272824-001  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
16  
CPU  
4K Bytes  
ROM (optional)  
1000  
RALU  
Interrupt  
Controller  
Byte  
Register  
File  
Chip Select  
CS5:0#  
Memory Controller  
with  
Peripheral  
Transaction  
Server  
Microcode  
Engine  
24 Bytes  
CPU SFRs  
Chip Select  
Control  
Signals  
Queue  
8
A19:16/  
EPORT3:0  
16  
A15:0  
Pulse  
Width  
Modulator  
Baud  
Rate  
Gen  
Serial  
Port  
Timer 1  
Timer 2  
Event  
Processor  
Array  
AD15:0  
Port  
3
Port  
4
Port 1  
Port 2  
Port 3/  
EXTINT3:2 PWM2:0  
Port 4/  
Port 1/  
Port 2/  
Hold Control,  
SIO,  
EPA3:0,  
Timer 1,  
Timer 2  
EXTINT1:0  
A2351-01  
Figure 1. 8XL196NP Block Diagram  
2
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
1.0 NOMENCLATURE OVERVIEW  
X
XX  
8
X
X
XXXXX XX  
A2815-01  
Figure 2. 8XL196NP Family Nomenclature  
Table 1. Description of Product Nomenclature  
Parameter  
Options  
Description  
Temperature and Burn-in Options  
no mark  
Commercial operating temperature range (0°C to 70°C)  
with Intel standard burn-in.  
Packaging Options  
S
QFP  
SB  
SQFP  
Program–memory Options  
0
3
No ROM  
ROM  
Process Information  
Product Family  
Device Speed  
L
Low Voltage CHMOS  
196NP  
no mark  
14 MHz  
3
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
2.0 PINOUT  
V
AD0  
NC  
RESET#  
NMI  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
SS  
A18 / EPORT.2  
A19 / EPORT.3  
WR# / WRL#  
RD#  
BHE# / WRH#  
ALE  
INST  
READY  
RPD  
ONCE  
V
V
V
A8  
A9  
EA#  
A0  
A1  
V
CC  
V
9
SS  
A2  
A3  
A4  
A5  
A6  
A7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SS  
S8XL196NP  
CC  
SS  
V
CC  
V
A10  
A11  
A12  
A13  
A14  
A15  
SS  
NC  
P3.0 / CS0#  
P3.1 / CS1#  
P3.2 / CS2#  
P3.3 / CS3#  
View of component as  
mounted on PC board  
V
V
SS  
SS  
P3.4 / CS4#  
P3.5 / CS5#  
P3.6 / EXTINT2  
NC  
XTAL1  
XTAL2  
V
P2.7 / CLKOUT  
NC  
P2.6 / HLDA#  
P2.5 / HOLD#  
SS  
P3.7 / EXTINT3  
P1.0 / EPA0  
V
CC  
A4318-01  
Figure 3. 8XL196NP 100-pin SQFP Package  
4
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 2. 8XL196NP 100-pin SQFP Pin Assignment  
Pin  
1
Name  
RESET#  
Pin  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
Name  
EXTINT3/P3.7  
EPA0/P1.0  
VCC  
Pin  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
Name  
Pin  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
Name  
WR#/WRL#  
EPORT.3/A19  
EPORT.2/A18  
VSS  
CLKOUT/P2.7  
†
2
NMI  
EA#  
A0  
NC  
3
VSS  
4
EPA1/P1.1  
EPA2/P1.2  
EPA3/P1.3  
T1CLK/P1.4  
T1DIR/P1.5  
VCC  
XTAL2  
XTAL1  
VSS  
5
A1  
VCC  
6
VCC  
VSS  
A2  
EPORT.1/A17  
EPORT.0/A16  
AD15  
†
7
NC  
8
A15  
9
A3  
A14  
AD14  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
A4  
T2CLK/P1.6  
VSS  
A13  
AD13  
A5  
A12  
AD12  
A6  
T2DIR/P1.7  
PWM0/P4.0  
PWM1/P4.1  
PWM2/P4.2  
P4.3  
A11  
AD11  
A7  
A10  
AD10  
VCC  
VSS  
A9  
AD9  
A8  
VSS  
†
NC  
VSS  
AD8  
†
NC  
VCC  
VCC  
VCC  
CS0#/P3.0  
CS1#/P3.1  
CS2#/P3.2  
CS3#/P3.3  
VSS  
VSS  
VSS  
AD7  
TXD/P2.0  
RXD/P2.1  
EXTINT0/P2.2  
BREQ#/P2.3  
EXTINT1/P2.4  
HOLD#/P2.5  
HLDA#/P2.6  
ONCE  
RPD  
READY  
INST  
ALE  
AD6  
AD5  
AD4  
AD3  
CS4#/P3.4  
CS5#/P3.5  
EXTINT2/P3.6  
AD2  
BHE#/WRH#  
RD#  
AD1  
100 AD0  
†
To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows:  
Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future  
devices), and Pin 52 = VCC  
.
5
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 3. 100-pin SQFP Pin Assignment Arranged by Functional Categories  
Address & Data  
Name Pin  
Address & Data (cont)  
Input/Output  
Name  
Power & Ground  
Name  
Pin  
85  
Pin  
18  
19  
20  
21  
23  
24  
27  
29  
30  
31  
82  
81  
78  
77  
46  
47  
48  
49  
50  
51  
25  
26  
41  
38  
39  
40  
45  
32  
33  
35  
37  
44  
Name  
Pin  
A0  
4
5
AD13  
AD14  
AD15  
CS0#/P3.0  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
6
A1  
84  
CS1#/P3.1  
CS2#/P3.2  
CS3#/P3.3  
CS4#/P3.4  
CS5#/P3.5  
EPA0/P1.0  
EPA1/P1.1  
EPA2/P1.2  
EPA3/P1.3  
EPORT.0  
EPORT.1  
EPORT.2  
EPORT.3  
P2.2  
14  
28  
34  
42  
67  
80  
92  
7
A2  
8
83  
A3  
9
A4  
10  
11  
12  
13  
65  
64  
63  
62  
61  
60  
59  
58  
82  
81  
78  
77  
100  
99  
98  
97  
96  
95  
94  
93  
91  
89  
88  
87  
86  
Bus Control & Status  
A5  
Name  
Pin  
73  
74  
47  
49  
50  
72  
75  
71  
76  
A6  
ALE  
A7  
BHE#/WRH#  
BREQ#  
HOLD#  
HLDA#  
A8  
A9  
15  
22  
36  
43  
53  
56  
66  
68  
79  
90  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
AD9  
INST  
RD#  
READY  
WR#/WRL#  
P2.3  
Processor Control  
Name Pin  
CLKOUT  
P2.4  
P2.5  
51  
3
P2.6  
EA#  
P2.7  
EXTINT0  
EXTINT1  
EXTINT2  
EXTINT3  
NMI  
46  
48  
25  
26  
2
P3.6  
No Connection  
Name  
P3.7  
Pin  
16  
17  
52  
57  
P4.3  
NC  
NC  
NC  
NC  
PWM0/P4.0  
PWM1/P4.1  
PWM2/P4.2  
RXD/P2.1  
T1CLK/P1.4  
T1DIR/P1.5  
T2CLK/P1.6  
T2DIR/P1.7  
TXD/P2.0  
ONCE  
69  
1
RESET#  
RPD  
70  
55  
54  
XTAL1  
XTAL2  
AD10  
AD11  
AD12  
6
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
RESET#  
NMI  
EA#  
A0  
1
2
3
4
5
6
7
8
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
RD#  
BHE# / WRH#  
ALE  
INST  
READY  
RPD  
A1  
V
CC  
V
ONCE  
SS  
V
V
V
A2  
A3  
A4  
A5  
A6  
A7  
SS  
9
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
SB8XL196NP  
SS  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
NC  
V
CC  
V
SS  
NC  
NC  
View of component as  
mounted on PC board  
P3.0 / CS0#  
P3.1 / CS1#  
P3.2 / CS2#  
P3.3 / CS3#  
V
SS  
XTAL1  
XTAL2  
V
SS  
V
P3.4 / CS4#  
P3.5 / CS5#  
P3.6 / EXTINT2  
SS  
NC  
P2.7 / CLKOUT  
A4317-01  
Figure 4. 8XL196NP 100-pin QFP Package  
7
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 4. 8XL196NP 100-pin QFP Pin Assignment  
Pin  
1
Name  
Pin  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
Name  
EXTINT2/P3.6  
No Connection  
EXTINT3/P3.7  
EPA0/P1.0  
VCC  
Pin  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
Name  
HOLD#/P2.5  
HLDA#/P2.6  
No Connection  
CLKOUT/P2.7  
VSS  
Pin  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
Name  
AD0  
RD#  
2
No Connection  
WR#/WRL#  
EPORT.3/A19  
EPORT.2/A18  
VSS  
3
RESET#  
4
NMI  
5
EA#  
6
A0  
EPA1/P1.1  
EPA2/P1.2  
EPA3/P1.3  
T1CLK/P1.4  
T1DIR/P1.5  
VCC  
XTAL2  
XTAL1  
VSS  
VCC  
7
A1  
EPORT.1/A17  
EPORT.0/A16  
AD15  
8
VCC  
9
VSS  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
A2  
A14  
AD14  
A3  
A13  
AD13  
A4  
T2CLK/P1.6  
VSS  
A12  
AD12  
A5  
A11  
AD11  
A6  
T2DIR/P1.7  
PWM0/P4.0  
PWM1/P4.1  
PWM2/P4.2  
P4.3  
A10  
AD10  
A7  
A9  
AD9  
VCC  
A8  
VSS  
VSS  
VSS  
AD8  
No Connection  
CS0#/P3.0  
CS1#/P3.1  
CS2#/P3.2  
CS3#/P3.3  
VSS  
VCC  
VCC  
VCC  
VSS  
AD7  
VSS  
ONCE  
RPD  
AD6  
TXD/P2.0  
RXD/P2.1  
EXTINT0/P2.2  
BREQ#/P2.3  
EXTINT1/P2.4  
AD5  
READY  
INST  
AD4  
AD3  
CS4#/P3.4  
CS5#/P3.5  
ALE  
AD2  
BHE#/WRH#  
100 AD1  
8
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 5. 100-pin QFP Pin Assignment Arranged by Functional Categories  
Address & Data  
Name Pin  
Address & Data (cont)  
Input/Output  
Name  
Power & Ground  
Name  
Pin  
86  
Pin  
19  
20  
21  
22  
24  
25  
29  
31  
32  
33  
83  
82  
79  
78  
48  
49  
50  
51  
52  
54  
26  
28  
43  
40  
41  
42  
47  
34  
35  
37  
39  
46  
Name  
Pin  
A0  
6
7
AD13  
AD14  
AD15  
CS0#/P3.0  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
8
A1  
85  
CS1#/P3.1  
CS2#/P3.2  
CS3#/P3.3  
CS4#/P3.4  
CS5#/P3.5  
EPA0/P1.0  
EPA1/P1.1  
EPA2/P1.2  
EPA3/P1.3  
EPORT.0  
EPORT.1  
EPORT.2  
EPORT.3  
P2.2  
16  
30  
36  
44  
68  
81  
93  
9
A2  
10  
11  
12  
13  
14  
15  
66  
65  
64  
63  
62  
61  
60  
59  
83  
82  
79  
78  
1
84  
A3  
A4  
Bus Control & Status  
A5  
Name  
Pin  
74  
75  
49  
51  
52  
73  
76  
72  
77  
A6  
ALE  
A7  
BHE#/WRH#  
BREQ#  
HOLD#  
HLDA#  
A8  
A9  
17  
23  
38  
45  
55  
58  
67  
69  
80  
91  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
AD9  
INST  
RD#  
READY  
WR#/WRL#  
P2.3  
Processor Control  
Name Pin  
CLKOUT  
P2.4  
P2.5  
54  
5
P2.6  
EA#  
P2.7  
EXTINT0  
EXTINT1  
EXTINT2  
EXTINT3  
NMI  
48  
50  
26  
28  
4
P3.6  
No Connection  
Name  
100  
99  
98  
97  
96  
95  
94  
92  
90  
89  
88  
87  
P3.7  
Pin  
2
P4.3  
NC  
NC  
NC  
NC  
PWM0/P4.0  
PWM1/P4.1  
PWM2/P4.2  
RXD/P2.1  
T1CLK/P1.4  
T1DIR/P1.5  
T2CLK/P1.6  
T2DIR/P1.7  
TXD/P2.0  
18  
27  
53  
ONCE  
70  
3
RESET#  
RPD  
71  
57  
56  
XTAL1  
XTAL2  
AD10  
AD11  
AD12  
9
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
3.0 SIGNALS  
Table 6. Signal Descriptions  
Name  
A15:0  
Type  
Description  
I/O  
System Address Bus  
These address pins provide address bits 0–15 during the entire external memory  
cycle during both multiplexed and demultiplexed bus modes.  
A19:16  
I/O  
Address Pins 16–19  
These address pins provide address bits 16–19 during the entire external memory  
cycle during both multiplexed and demultiplexed bus modes, supporting extended  
addressing of the 1-Mbyte address space.  
NOTE: Internally, there are 24 address bits; however, only 20 external address  
pins (A19:0) are implemented. The internal address space is 16 Mbytes  
(000000–FFFFFFH) and the external address space is 1 Mbyte (00000–  
FFFFFH). The microcontroller resets to FF2080H in internal memory or  
F2080H in external memory.  
A19:16 share package pins with EPORT.3:0.  
AD15:0  
I/O  
Address/Data Lines  
The function of these pins depends on the bus width and mode.  
16-bit Multiplexed Bus Mode:  
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or  
receive data during the second half of the bus cycle.  
8-bit Multiplexed Bus Mode:  
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive address  
bits 0–7 during the first half of the bus cycle and drive or receive data during the  
second half of the bus cycle.  
16-bit Demultiplexed Mode:  
AD15:0 drive or receive data during the entire bus cycle.  
8-bit Demultiplexed Mode:  
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that  
is currently on the high byte of the internal bus.  
ALE  
O
Address Latch Enable  
This active-high output signal is asserted only during external memory cycles. ALE  
signals the start of an external bus cycle and indicates that valid address  
information is available on the system address/data bus (A19:16 and AD15:0 for a  
multiplexed bus; A19:0 for a demultiplexed bus).  
An external latch can use this signal to demultiplex address bits 0–15 from the  
address/data bus in multiplexed mode.  
10  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Name  
BHE#  
Type  
Description  
†
O
Byte High Enable  
During 16-bit bus cycles, this active-low output signal is asserted for word and high-  
byte reads and writes to external memory. BHE# indicates that valid data is being  
transferred over the upper half of the system data bus. Use BHE#, in conjunction  
with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed  
address/data bus), to determine which memory byte is being transferred over the  
system bus:  
BHE#  
AD0 or A0 Byte(s) Accessed  
0
0
1
0
1
0
both bytes  
high byte only  
low byte only  
BHE# shares a package pin with WRH#.  
†
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the  
chip configuration register 0 (CCR0) determines whether it functions as BHE# or  
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.  
BREQ#  
O
Bus Request  
This active-low output signal is asserted during a hold cycle when the bus controller  
has a pending external memory cycle. When the bus-hold protocol is enabled  
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the  
configuration selected through the port configuration registers (P2_MODE,  
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until  
the bus-hold protocol is disabled (WSR.7 is cleared).  
The microcontroller can assert BREQ# at the same time as or after it asserts  
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.  
BREQ# shares a package pin with P2.4.  
Clock Output  
CLKOUT  
O
Output of the internal clock generator. The CLKOUT frequency is ½ the internal  
operating frequency (f). CLKOUT has a 50% duty cycle.  
CLKOUT shares a package pin with P2.7.  
Chip-select Lines 0–5  
CS5#:0  
O
The active-low output CSx# is asserted during an external memory cycle when the  
address to be accessed is in the range programmed for chip select x. If the external  
memory address is outside the range assigned to the six chip selects, no chip-  
select output is asserted and the bus configuration defaults to the CS5# values.  
Immediately following reset, CS0# is automatically assigned to the range FF2000–  
FF20FFH (F2000–F20FFH if external).  
CS5:0# share package pins with P3.5:0.  
11  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Name  
EA#  
Type  
Description  
I
External Access  
This input determines whether memory accesses to special-purpose and program  
memory partitions (FF2000–FF2FFFH) are directed to internal or external memory.  
These accesses are directed to internal memory if EA# is held high and to external  
memory if EA# is held low. For an access to any other memory location, the value  
of EA# is irrelevant.  
EA# is not latched and can be switched dynamically during normal operating mode.  
Be sure to thoroughly consider the issues, such as different access times for  
internal and external memory, before using this dynamic switching capability.  
Always connect EA# to VSS when using a microcontroller that has no internal  
nonvolatile memory.  
EPA3:0  
I/O  
I/O  
I
Event Processor Array (EPA) Capture/Compare Channels  
High-speed input/output signals for the EPA capture/compare channels.  
EPA3:0 share package pins with P1.3:0.  
EPORT.3:0  
Extended Addressing Port  
This is a 4-bit, bidirectional, memory-mapped port.  
EPORT.3:0 share package pins with A.19:16.  
EXTINT0  
EXTINT1  
EXTINT2  
EXTINT3  
External Interrupts  
In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt  
pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum  
high time is one state time.  
In standby and powerdown modes, asserting the EXTINTx signal for at least 50 ns  
causes the device to resume normal operation. The interrupt does not need to be  
enabled, but the pin must be configured as a special-function input. If the EXTINTx  
interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the  
CPU executes the instruction that immediately follows the command that invoked  
the power-saving mode.  
In idle mode, asserting any enabled interrupt causes the device to resume normal  
operation.  
EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with  
P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package  
pin with P3.7.  
HLDA#  
O
Bus Hold Acknowledge  
This active-low output indicates that the CPU has released the bus as the result of  
an external device asserting HOLD#. When the bus-hold protocol is enabled  
(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the  
configuration selected through the port configuration registers (P2_MODE,  
P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until  
the bus-hold protocol is disabled (WSR.7 is cleared).  
12  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Description  
Name  
HOLD#  
Type  
I
Bus Hold Request  
An external device uses this active-low input signal to request control of the bus.  
When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can  
function only as HOLD#, regardless of the configuration selected through the port  
configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change  
the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is  
cleared).  
HOLD# shares a package pin with P2.5.  
Instruction Fetch  
INST  
O
When high, INST indicates that an instruction is being fetched from external  
memory. The signal remains high during the entire bus cycle of an external  
instruction fetch. INST is low for data accesses, including interrupt vector fetches  
and chip configuration byte reads. INST is low during internal memory fetches.  
NMI  
I
I
Nonmaskable Interrupt  
In normal operating mode, a rising edge on NMI generates a nonmaskable  
interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for  
greater than one state time to guarantee that it is recognized.  
ONCE  
On-circuit Emulation  
Holding ONCE high during the rising edge of RESET# places the device into on-  
circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance  
state, thereby isolating the device from other components in the system. The value  
of ONCE is latched when the RESET# pin goes inactive. While the device is in  
ONCE mode, you can debug the system using a clip-on emulator.  
To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent  
inadvertent entry into ONCE mode, connect the ONCE pin to VSS  
.
P1.7:0  
P2.7:0  
I/O  
I/O  
Port 1  
This is a standard, 8-bit, bidirectional port that shares package pins with individually  
selectable special-function signals.  
Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1,  
P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.  
Port 2  
This is a standard, 8-bit, bidirectional port that shares package pins with individually  
selectable special-function signals.  
Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,  
P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and  
P2.7/CLKOUT.  
P3.7:0  
I/O  
Port 3  
This is a standard, 8-bit, bidirectional port that shares package pins with individually  
selectable special-function signals.  
Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#,  
P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and  
P3.7/EXTINT3.  
13  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Name  
P4.3:0  
Type  
Description  
I/O  
Port 4  
This ia a 4-bit bidirectional, standard I/O port with high-current drive capability.  
Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1,  
and P4.2/PWM2. P4.3 has a dedicated package pin.  
PWM2:0  
RD#  
O
O
Pulse Width Modulator Outputs  
These are PWM output pins with high-current drive capability.  
PWM2:0 share package pins with P4.2:0.  
Read  
Read-signal output to external memory. RD# is asserted only during external  
memory reads.  
RD# shares a package pin with OE#. (While most signals that share package pins  
are connected to the pin by programming their associated control registers, both of  
these signals are always connected to the pin.)  
READY  
I
Ready Input  
This active-high input can be used to insert wait states in addition to those  
programmed in the chip configuration byte 0 (CCB0) and the bus control x register  
(BUSCONx). CCB0 is programmed with the minimum number of wait states (0–3)  
for an external fetch of CCB1, and BUSCONx is programmed with the minimum  
number of wait states (0–3) for all external accesses to the address range assigned  
to the chip-select x channel. If READY is low when the programmed number of wait  
states is reached, additional wait states are added until READY is pulled high.  
READY shares a package pin with P5.6.  
Reset  
RESET#  
I/O  
A level-sensitive reset input to and open-drain system reset output from the  
microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-  
down transistor connected to the RESET# pin for 16 state times. In the powerdown,  
standby, and idle modes, asserting RESET# causes the chip to reset and return to  
normal operating mode. After a device reset, the first instruction fetch is from  
FF2080H (or F2080H in external memory). For the 80L196NP, the program and  
special-purpose memory locations (FF2000–FF2FFFH) reside in external memory.  
For the 83L196NP, these locations can reside either in external memory or in  
internal ROM.  
RPD  
I
Return from Powerdown  
Timing pin for the return-from-powerdown circuit.  
If your application uses powerdown mode, connect a capacitor between RPD and  
V
SS if the internal oscillator is the clock source.  
The capacitor causes a delay that enables the oscillator and PLL circuitry to  
stabilize before the internal CPU and peripheral clocks are enabled.  
The capacitor is not required if your application uses powerdown mode and if an  
external clock input is the clock source.  
If your application does not use powerdown mode, leave this pin unconnected.  
14  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Description  
Name  
RXD  
Type  
I/O  
Receive Serial Data  
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as  
either an input or an open-drain output for data.  
RXD shares a package pin with P2.1.  
Timer 1 External Clock  
T1CLK  
I
External clock for timer 1. Timer 1 increments (or decrements) on both rising and  
falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature  
counting mode.  
and  
External clock for the serial I/O baud-rate generator input (program selectable).  
T1CLK shares a package pin with P1.4.  
T2CLK  
T1DIR  
T2DIR  
TXD  
I
I
Timer 2 External Clock  
External clock for timer 2. Timer 2 increments (or decrements) on both rising and  
falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature  
counting mode.  
T2CLK shares a package pin with P1.6.  
Timer 1 External Direction  
External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high  
and decrements when it is low. Also used in conjunction with T1CLK for quadrature  
counting mode.  
T1DIR shares a package pin with P1.5.  
Timer 2 External Direction  
I
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high  
and decrements when it is low. It is also used in conjunction with T2CLK for  
quadrature counting mode.  
T2DIR shares a package pin with P1.7.  
Transmit Serial Data  
O
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it  
is the serial clock output.  
TXD shares a package pin with P2.0.  
VCC  
VSS  
PWR Digital Supply Voltage  
Connect each VCC pin to the digital supply voltage.  
GND Digital Circuit Ground  
These pins supply ground for the digital circuitry. Connect each VSS pin to ground  
through the lowest possible impedance path.  
†
WR#  
O
Write  
This active-low output indicates that an external write is occurring. This signal is  
asserted only during external memory writes.  
WR# shares a package pin with WRL#.  
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the  
chip configuration register 0 (CCR0) determines whether it functions as WR# or  
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.  
15  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 6. Signal Descriptions (Continued)  
Name  
WRH#  
Type  
Description  
†
O
Write High  
During 16-bit bus cycles, this active-low output signal is asserted for high-byte  
writes and word writes to external memory. During 8-bit bus cycles, WRH# is  
asserted for all write operations.  
WRH# shares a package pin with BHE#.  
†
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the  
chip configuration register 0 (CCR0) determines whether it functions as BHE# or  
WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.  
†
WRL#  
O
Write Low  
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes  
and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for  
all write operations.  
WRL# shares a package pin with WR#.  
†
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the  
chip configuration register 0 (CCR0) determines whether it functions as WR# or  
WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.  
XTAL1  
XTAL2  
I
Input Crystal/Resonator or External Clock Input  
Input to the on-chip oscillator and the internal clock generators. The internal clock  
generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When  
using an external clock source instead of the on-chip oscillator, connect the clock  
input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.  
O
Inverted Output for the Crystal/Resonator  
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design  
uses an external clock source instead of the on-chip oscillator.  
16  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
4.0 ADDRESS MAP  
Table 7. 8XL196NP Address Map  
Description  
External device (memory or I/O) connected to address/data bus  
Address  
(Note 1)  
Notes  
FF FFFFH  
FF 3000H  
2
FF 2FFFH Internal ROM or external device (memory or I/O) connected to address/data bus  
FF 2000H (determined by EA# pin)  
2, 3  
FF 1FFFH  
External device (memory or I/O) connected to address/data bus  
FF 0100H  
2
FF 00FFH  
Reserved for ICE  
FF 0000H  
4
2
FE FFFFH Overlaid memory (reserved for future devices);  
0F 0000H locations xF0000–xF00FFH are reserved for ICE  
0E FFFFH  
896 Kbytes of external device (memory or I/O) connected to address/data bus  
01 0000H  
2
00 FFFFH  
External device (memory or I/O) connected to address/data bus  
00 3000H  
2
00 2FFFH External device (memory or I/O) connected to address/data bus or  
00 2000H remapped internal ROM  
2, 5, 6  
2, 4, 7  
4, 7, 9  
6
00 1FFFH  
Memory-mapped peripheral special-function registers (SFRs)  
00 1FE0H  
00 1FDFH  
Internal peripheral special-function registers (SFRs)  
00 1F00H  
00 1EFFH  
External device (memory or I/O) (reserved for future devices)  
00 0400H  
00 03FFH  
Upper register file (general-purpose register RAM)  
00 0100H  
8, 9  
00 00FFH  
Lower register file (general-purpose register RAM and stack pointer)  
00 0018H  
8, 10  
4, 7, 8, 10  
00 0017H  
Lower register file (CPU SFRs)  
00 0000H  
NOTES:  
1. Internally, there are 24 address bits (A23:0); however, only 20 address lines (A19:0) are bonded out.  
The external address space is 1 Mbyte (00000–FFFFFH).  
2. Address with indirect, indexed, or extended modes.  
3. The 8XL196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external  
memory).  
4. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.  
5. These areas are mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1.  
Otherwise, they are mapped to external memory.  
6. WARNING: The contents or functions of these memory locations may change with future device revi-  
sions, in which case a program that relies on one or more of these locations may not function properly.  
7. Refer to the 8XC196NP, 80C196NU Microcontroller User’s Manual.  
8. Code executed in locations 000000H to 0003FFH will be forced external.  
9. Address with indirect, indexed, or extended modes or through register windows.  
10. Address with direct, indirect, indexed, or extended modes.  
17  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.0 ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This document contains information on  
products in the design phase of development. The  
specifications are subject to change without notice.  
Do not finalize a design with this information.  
Revised information will be published when the  
product is available. Verify with your local Intel  
sales office that you have the latest datasheet  
before finalizing a design.  
Storage Temperature ................................. –60°C to +150°C  
Supply Voltage with Respect to VSS............. –0.5 V to +7.0 V  
Power Dissipation ........................................................ 1.5 W  
OPERATING CONDITIONS*  
TA (Ambient Temperature Under Bias) ..............0°C to +70°C  
V
F
CC (Digital Supply Voltage) ............................ 2.7 V to 3.3 V  
XTAL1 (Input Frequency for VCC = 2.7–3.3 V)  
(Note 1).............. 8 MHz to 14 MHz  
*WARNING: Stressing the device beyond the “Absolute  
Maximum Ratings” may cause permanent damage. These  
are stress ratings only. Operation beyond the “Operating  
Conditions” is not recommended and extended exposure  
beyond the “Operating Conditions” may affect device reli-  
ability.  
NOTES:  
1.  
This device is static and should operate below 1 Hz, but  
has been tested only down to 8 MHz.  
5.1 DC Characteristics  
Table 8. DC Characteristics at VCC = 2.7 – 3.3 V  
(1)  
Symbol  
ICC  
Parameter  
Min  
Typ  
Max  
Units Test Conditions  
VCC Supply Current  
Idle Mode Current  
28  
40  
mA  
XTAL1 = 14MHz  
VCC = 3.3V  
Device in Reset  
IIDLE  
IPD  
ILI  
14  
50  
25  
75  
mA  
µA  
µA  
XTAL1 = 14MHz  
VCC = 3.3 V  
Powerdown Mode Current  
(Note 2)  
VCC = 3.3V  
Input Leakage Current  
(all input pins except RESET)  
±10  
VSS < VIN < VCC  
VIL  
Input Low Voltage (all pins)  
Input High Voltage  
–0.5  
0.2 VCC +1.3  
–0.5  
0.4  
V
V
V
V
VIH  
VCC + 0.5  
0.3 VCC  
VCC + 0.5  
VIL1  
Input Low Voltage XTAL1  
Input High Voltage XTAL1  
VIH1  
0.7 VCC  
NOTES:  
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed  
are at room temperature and with VCC = 3.0 V.  
2. For temperatures below 100°C, typical is 10 µA.  
3. For all pins except P4.3:0, which have higher drive capability.  
4. If VOL is held above 0.45 V or VOH is held below Vcc–0.7 V, current on pins must be externally limited to  
the following values: IOL and IOH maximum on all output pins is 12 mA.  
5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which  
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).  
6. Pin capacitance is not tested. CS is based on design simulations.  
18  
 
 
 
 
 
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 8. DC Characteristics at VCC = 2.7 – 3.3 V(Continued)  
(1)  
Symbol  
VOL  
Parameter  
Min  
Typ  
Max  
Units Test Conditions  
Output Low Voltage (output  
configured as complemen-  
tary) (Note 3,4)  
0.3  
V
V
IOL = 200 µA  
0.45  
IOL = 3.2 mA  
VOH  
Output High Voltage (output  
configured as complemen-  
tary) (Note 4)  
VCC – 0.3  
VCC – 0.7  
V
V
I
OH = –200 µA  
IOH = –3.2 mA  
VOH2  
Output High Voltage on  
XTAL2  
VCC – 0.3  
VCC – 0.7  
V
V
I
OH = –100 µA  
IOH = –500 µA  
OL = 8 mA  
IOL = 10 mA  
VOL  
Output Low Voltage on P4.x  
(output configured as comple-  
mentary)  
0.45  
0.6  
V
V
I
1
VOL  
Output Low Voltage in  
RESET on ALE, INST, and  
NMI  
0.45  
V
IOL = 2 µA  
2
VOH  
Output High Voltage in  
RESET (Note 5)  
VCC – 0.7  
V
V
IOH = –2 µA  
IOL = 30 µA  
1
VOL  
Output Low Voltage in  
RESET for ONCE pin  
0.8  
3
VOL  
Output Low Voltage on  
XTAL2  
0.3  
V
V
IOL = 100 µA  
IOL = 500 µA  
4
0.45  
VTH+–VTH– Hysteresis voltage width on  
0.3  
V
RESET# pin  
CS  
Pin Capacitance (any pin to  
VSS) (Note 6)  
10  
95  
pF  
kΩ  
RRST  
RESET Pull-up Resistor  
9
VCC = 3.3V,  
VIN = 2.0V  
NOTES:  
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed  
are at room temperature and with VCC = 3.0 V.  
2. For temperatures below 100°C, typical is 10 µA.  
3. For all pins except P4.3:0, which have higher drive capability.  
4. If VOL is held above 0.45 V or VOH is held below Vcc–0.7 V, current on pins must be externally limited to  
the following values: IOL and IOH maximum on all output pins is 12 mA.  
5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which  
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).  
6. Pin capacitance is not tested. CS is based on design simulations.  
19  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
35  
30  
25  
20  
15  
10  
5
IIDLE@VCC = 3.0 V  
CC@VCC = 3.0 V  
I
0
2
4
6
8
10 12 14 16 18 20  
Frequency (MHz)  
A4319-01  
Figure 5. ICC, IIDLE versus Frequency  
20  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.2 AC Characteristics — Multiplexed Bus Mode  
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.  
Table 9. AC Characteristics, Multiplexed Bus Mode  
VCC = 2.7 V – 3.3 V  
Symbol  
Parameter  
Units  
Min  
The 8XL196NP Will Meet These Specifications  
Max  
FXTAL  
Input frequency on XTAL1  
Period, 1/FXTAL  
8
14  
MHz  
ns  
1
TXTAL  
71  
20  
125  
110  
1
1
TXHCH  
TCLCL  
TCHCL  
TAVRL  
TAVWL  
XTAL1 High to CLKOUT High/Low  
CLKOUT Cycle Time  
ns  
2TXTAL  
ns  
1
CLKOUT High Period  
TXTAL1 – 10  
TXTAL1 + 15  
ns  
A15:0, CSx# Valid to RD# Low  
A15:0, CSx# Valid to WR# Low  
A19:16, CSx# Hold after WR# Rising Edge  
A19:16, CSx# Hold after RD# Rising Edge  
CLKOUT Low to ALE High  
2TXTAL1 – 30  
ns  
2TXTAL1 – 15  
ns  
TW  
0
HSH  
TRHSH  
TCLLH  
TLLCH  
TLHLH  
0
–12  
–10  
10  
15  
ns  
ns  
ALE Low to CLKOUT High  
ALE Cycle Time  
4TXTAL  
ns (1)  
1
TLHLL  
ALE High Period  
TXTAL1 – 15  
TXTAL1 – 18  
TXTAL1 – 25  
TXTAL1 – 30  
5
TXTAL1 + 5  
ns  
ns  
TAVLL  
AD15:0 Valid to ALE Low  
AD15:0 Hold after ALE Low  
ALE Low to RD# Low  
RD# Low to CLKOUT Low  
RD# Low Period  
TLLAX  
ns  
TLLRL  
ns  
TRLCL  
TRLRH  
TRHLH  
TRLAZ  
TLLWL  
TCLWL  
TQVWH  
TCHWH  
TWLWH  
NOTES:  
30  
ns  
TXTAL1 – 10  
TXTAL1 – 5  
ns (1)  
RD# High to ALE High  
RD# Low to Address Float  
ALE Low to WR# Low  
CLKOUT Low to WR# Low  
Data Valid before WR# High  
CLKOUT High to WR# High  
WR# Low Period  
TXTAL1 + 20 ns (2)  
5
ns  
ns  
TXTAL1 – 30  
–18  
10  
10  
ns  
TXTAL1 – 23  
–10  
ns (1)  
ns  
TXTAL1 – 10  
ns (1)  
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.  
2. Assuming back-to-back bus cycles.  
3. 8-bit bus only.  
21  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 9. AC Characteristics, Multiplexed Bus Mode (Continued)  
V
CC = 2.7 V – 3.3 V  
Min Max  
The 8XL196NP Will Meet These Specifications  
Symbol  
Parameter  
Units  
TWHQX  
TWHLH  
TWHBX  
TWHAX  
TRHBX  
Data Hold after WR# High  
TXTAL1 – 33  
TXTAL1 – 12  
TXTAL1 – 10  
TXTAL1 – 30  
TXTAL1 – 10  
TXTAL1 – 25  
ns  
WR# High to ALE High  
TXTAL1 + 20 ns (2)  
BHE#, INST Hold after WR# High  
A15:8 Hold after WR# High  
BHE#, INST Hold after RD# High  
A15:8 Hold after RD# High  
ns  
ns (3)  
ns  
TRHAX  
ns (3)  
NOTES:  
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.  
2. Assuming back-to-back bus cycles.  
3. 8-bit bus only.  
22  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 10. AC Characteristics, Multiplexed Bus Mode  
VCC = 2.7 V – 3.3 V  
Min Max  
The External Memory System Must Meet These Specifications  
Symbol  
Parameter  
Units  
TAVYV  
TYLYH  
TCLYX  
TAVDV  
TRLDV  
TSLDV  
TCLDV  
TRHDZ  
TRXDX  
NOTES:  
AD15:0 Valid to READY Setup  
Non READY Time  
2TXTAL1 – 60  
No Upper Limit  
ns  
ns  
READY Hold after CLKOUT Low  
AD15:0 Valid to Input Data Valid  
RD# Active to Input Data Valid  
Chip-select Low, A19:16 Valid to Data Valid  
CLKOUT Low to Input Data Valid  
End of RD# to Input Data Float  
Data Hold after RD# Inactive  
0
TXTAL1 – 20 ns (1)  
3TXTAL1 – 55 ns (2)  
TXTAL1 – 25 ns (2)  
4TXTAL1 – 75  
TXTAL1 – 50  
TXTAL1 – 10  
ns  
ns  
ns  
0
1. Exceeding the maximum specification causes additional wait states.  
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.  
Table 11. AC Timing Symbol Definitions  
Signals  
Conditions  
High  
†
A
B
C
D
Address  
BHE#  
H
HOLD#  
HLDA#  
ALE  
S
W
X
CSx#  
H
L
HA  
L
WR#, WRH#, WRL#  
XTAL1  
Low  
CLKOUT  
Data  
V
X
Z
Valid  
Q
R
Data Out  
RD#  
Y
READY  
No Longer Valid  
Floating  
G
Buswidth  
BR BREQ#  
†
Address bus (demultiplexed mode) or Address/data bus (multiplexed mode)  
23  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
T
XTAL1  
XTAL1  
T
T
T
T
CHCL  
CLCL  
XHCH  
CLKOUT  
RLCL  
T
T
CLLH  
LLCH  
T
LHLH  
ALE  
RD#  
T
T
T
T
RHLH  
T
LHLL  
RLRH  
LLRL  
LLAX  
T
T
RLDV  
T
RHDZ  
AVLL  
T
RLAZ  
Address Out  
Data  
AD15:0  
(read)  
T
AVDV  
T
T
T
WHLH  
LLWL  
WLWH  
WR#  
T
T
WHQX  
QVWH  
AD15:0  
(write)  
Address Out  
Data Out  
Address Out  
T
T
RHBX  
WHBX  
BHE#,  
INST  
Valid  
T
RHAX  
T
WHAX  
AD15:8  
Address Out  
T
SLDV  
Address Out  
A19:16  
CSx#  
T
WHSH  
T
RHSH  
A2844-01  
Figure 6. System Bus Timing Diagram (Multiplexed Bus Mode)  
24  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
T
(max)  
CLYX  
CLKOUT  
T
AVYV  
T
(min)  
CLYX  
READY  
ALE  
T
+ 2T  
XTAL1  
LHLH  
T
+ 2T  
XTAL1  
RLRH  
RD#  
T
+ 2T  
RLDV  
+ 2T  
XTAL1  
T
AVDV  
XTAL1  
AD15:0  
(read)  
Address Out  
Address Out  
Data In  
T
+ 2T  
WLWH  
XTAL1  
+ 2T  
WR#  
T
QVWH  
XTAL1  
AD15:0  
(write)  
Data Out  
BHE#, INST  
A19:16  
Extended Address Out  
CSx#  
A3250-01  
Figure 7. READY Timing Diagram (Multiplexed Bus Mode)  
25  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.3 AC Characteristics — Demultiplexed Bus Mode  
Test Coditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.  
Table 12. AC Characteristics, Demultiplexed Bus Mode  
VCC = 2.7 V – 3.3 V  
Symbol  
Parameter  
Units  
Min  
The 8XL196NP Will Meet These Specifications  
Input requency on XTAL1  
Period, 1/FXTAL  
Max  
FXTAL  
8
14  
MHz  
ns  
1
TXTAL  
71  
20  
125  
110  
1
1
TXHCH  
TCLCL  
TCHCL  
TAVRL  
TAVWL  
TCLLH  
TLLCH  
TLHLH  
XTAL1 High to CLKOUT High/Low  
CLKOUT Cycle Time  
ns  
2TXTAL  
ns  
1
CLKOUT High Period  
TXTAL1 – 10 TXTAL1 + 15  
2TXTAL1 – 48  
ns  
A19:0, CSx# Valid to RD# Low  
A19:0, CSx# Valid to WR# Low  
CLKOUT Low to ALE High  
ALE Low to CLKOUT High  
ALE Cycle Time  
ns  
2TXTAL1 – 37  
ns  
– 12  
– 15  
10  
15  
ns  
ns  
4TXTAL  
ns (1)  
1
TLHLL  
ALE High Period  
TXTAL1 – 12 TXTAL1 + 10  
ns  
ns  
TRLCH  
TRLRH  
TRHLH  
TWLCH  
TQVWH  
TCHWH  
TWLWH  
TWHQX  
TWHLH  
TWHBX  
TWHAX  
TRHBX  
TRHAX  
NOTES:  
RD# Low to CLKOUT High  
RD# Low Period  
– 5  
20  
2TXTAL1 – 10  
ns (1)  
RD# High to ALE High  
TXTAL1 – 5 TXTAL1 + 20 ns (2)  
WR# Low to CLKOUT High  
Data Valid before WR# High  
CLKOUT High to WR# High  
WR# Low Period  
– 10  
10  
ns  
ns (1)  
ns  
3TXTAL1 – 55  
– 15  
5
2TXTAL1 – 13  
TXTAL1 – 25  
ns (1)  
ns  
Data Hold after WR# High  
WR# High to ALE High  
TXTAL1 – 10 TXTAL1 + 20 ns (2)  
BHE#, INST Hold after WR# High  
A19:0, CSx# Hold after WR# High  
BHE#, INST Hold after RD# High  
A19:0, CSx# Hold after RD# High  
TXTAL1 – 10  
ns  
ns  
ns  
ns  
0
TXTAL1 – 10  
0
1. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.  
2. Assuming back-to-back bus cycles.  
26  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
Table 13. AC Characteristics, Demultiplexed Bus Mode  
VCC = 2.7 V – 3.3 V  
Min Max  
The External Memory System Must Meet These Specifications  
Symbol  
Parameter  
Units  
TAVYV  
TYLYH  
TCLYX  
TAVDV  
TRLDV  
TCLDV  
TRHDZ  
TRXDX  
NOTES:  
A19:0, CSx# Valid to READY Setup  
Non READY Time  
3TXTAL1 – 88  
No Upper Limit  
ns  
ns  
READY Hold after CLKOUT Low  
A19:0, CSx# Valid to Input Data Valid  
RD# Active to Input Data Valid  
CLKOUT Low to Input Data Valid  
End of RD# to Input Data Float  
Data Hold after RD# Inactive  
TXTAL1 – 30 ns (1)  
4TXTAL1 – 75 ns (2)  
2TXTAL1 – 33 ns (2)  
TXTAL1 – 50  
TXTAL1 – 5  
ns  
ns  
ns  
0
1. Exceeding the maximum specification causes additional wait states.  
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.  
27  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
T
XTAL1  
XTAL1  
T
T
T
CLCL  
CHCL  
XHCH  
CLKOUT  
T
CLDV  
T
T
LLCH  
CLLH  
T
LHLH  
ALE  
RD#  
T
T
T
RHLH  
LHLL  
RLRH  
T
RLCH  
T
T
RHDZ  
RLDV  
AD15:0  
(read)  
Valid  
T
AVDV  
T
CHWH  
T
WHLH  
T
WLWH  
T
WLCH  
WR#  
T
T
QVWH  
WHQX  
AD15:0  
(write)  
Valid  
T
RHBX  
T
WHBX  
BHE#,  
INST  
Valid  
T
T
RHAX  
WHAX  
A19:0  
CSx#  
Address Out  
Address  
A2845-01  
Figure 8. System Bus Timing Diagram (Demultiplexed Bus Mode)  
28  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
T
(max)  
CLYX  
CLKOUT  
READY  
T
(min)  
CLYX  
T
AVYV  
T
+ 2T  
LHLH  
XTAL1  
+ 2T  
ALE  
RD#  
T
RLRH  
XTAL1  
T
+ 2T  
RLDV  
+ 2T  
XTAL1  
XTAL1  
T
AVDV  
AD15:0  
(read)  
Data  
T
+ 2T  
XTAL1  
WLWH  
WR#  
T
+ 2T  
QVWH  
XTAL1  
AD15:0  
(write)  
Data Out  
BHE#, INST  
A19:0  
Extended Address Out  
CSx#  
A3256-01  
Figure 9. READY Timing Diagram (Demultiplexed Bus Mode)  
29  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.4 HOLD#/HLDA# Timing  
Table 14. HOLD#/HLDA# Timings  
V
CC = 2.7 V – 3.3V  
Symbol  
Parameter  
Units  
Min  
Max  
THVCH  
HOLD# Setup Time (to guarantee recognition at next clock)  
CLKOUT Low to HLDA# Low  
83  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCLHAL  
TCLBRL  
THALAZ  
THALBZ  
TCLHAH  
TCLBRH  
THAHAX  
THAHBV  
–15  
–15  
15  
15  
33  
25  
15  
25  
CLKOUT Low to BREQ# Low  
HLDA# Low to Address Float  
HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven  
CLKOUT Low to HLDA# High  
–25  
–25  
–20  
–20  
CLKOUT Low to BREQ# High  
HLDA# High to Address No Longer Floating  
HLDA# High to BHE#, INST, RD#, WR# Valid  
CLKOUT  
THVCH  
THVCH  
Hold Latency  
HOLD#  
HLDA#  
BREQ#  
TCLHAL  
TCLHAH  
TCLBRL  
TCLBRH  
THALAZ  
THAHAX  
A19:0, AD15:0  
THALBZ  
THAHBV  
Weakly held inactive  
TCLLH  
CSx#, BHE#,  
INST, RD#, WR#  
WRL#, WRH#  
ALE  
Start of strongly driven ALE  
A2460-03  
Figure 10. HOLD#/HLDA# Timing Diagram  
30  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.5 AC Characteristics — Serial Port, Shift Register Mode  
Table 15. Serial Port Timing — Shift Register Mode  
V
CC = 2.7 V – 3.3V  
Symbol  
Parameter  
Serial Port Clock period  
Units  
Min  
Max  
TXLXL  
(BRR ≥ x002H)  
6TXTAL  
4TXTAL  
ns  
ns  
1
1
(BRR = x001H) (Note 1)  
TQVXH  
TXHQX  
TXHQV  
TDVXH  
TXHDX  
TXHQZ  
NOTE:  
Output data setup to clock high  
Output data hold after clock high  
Next output data valid after clock high  
Input data setup to clock high  
Input data hold after clock high  
Last clock high to output float  
3TXTAL1 – 30  
ns  
ns  
ns  
ns  
ns  
ns  
2TXTAL1 – 90  
2TXTAL1 + 50  
2TXTAL1 + 50  
0
5TXTAL1+ 30  
1. The minimum baud-rate register value for receptions is x002H and the minimum baud-rate register  
value for transmissions is x001H.  
T
XLXL  
TXD  
T
T
XHQV  
XLXH  
T
T
XHQZ  
T
XHQX  
5
QVXH  
RXD  
0
T
1
2
7
4
6
3
(Out)  
T
DVXH  
XHDX  
Valid  
RXD  
(In)  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
Valid  
A2080-02  
Figure 11. Serial Port Waveform — Shift Register Mode  
31  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
5.6 External Clock Drive  
Table 16. External Clock Drive  
Symbol  
1/TXLXL  
Parameter  
Input frequency  
Min  
8
Max  
14  
Units  
MHz  
ns  
TXLXL  
TXHXX  
TXLXX  
TXLXH  
TXHXL  
Period (TXTAL  
High Time  
Low Time  
Rise Time  
Fall Time  
)
71  
125  
1
0.35TXTAL  
0.35TXTAL  
0.65TXTAL  
0.65TXTAL  
10  
ns  
1
1
1
ns  
1
ns  
10  
ns  
TXHXL  
TXHXX  
TXLXH  
0.7 VCC + 0.5 V  
0.7 VCC + 0.5 V  
0.3 VCC – 0.5 V  
TXLXL  
TXLXX  
0.3 VCC – 0.5 V  
A2119-02  
Figure 12. External Clock Drive Waveforms  
5.7 Test Output Waveforms  
2.5 V  
1.6 V  
0.5 V  
1.6 V  
0.5 V  
Test Points  
0.25 V  
AC testing inputs are driven at 2.5 V for a logic "1" and 0.25 V for  
a logic "0". Timing measurements are made at 1.6 V for a logic  
"1" and 0.5 V for a logic "0".  
A2740-01  
Figure 13. AC Testing Output Waveforms During 3.0 Volt Testing  
32  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
VLOAD + 0.15 V  
VLOAD  
VOH – 0.15 V  
Timing Reference  
Points  
VOL + 0.15 V  
VLOAD – 0.15 V  
For timing purposes, a port pin is no longer floating when a  
150 mV change from load voltage occurs and begins to float  
when a 150 mV change from the loading VOH/VOL level occurs  
with IOL/IOH ≤10 mA.  
A2739-01  
Figure 14. Float Waveforms During 3.0 Volt Testing  
33  
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER  
6.0 THERMAL CHARACTERISTICS  
All thermal impedance data is approximate for static  
air conditions at 1 watt of power dissipation. Values  
will change depending on operating conditions and  
the application. The Intel Packaging Handbook  
(order number 240800) describes Intel’s thermal  
impedance test methodology.  
Table 17. Thermal Characteristics  
Package Type  
100-pin SQFP  
100-pin QFP  
θ
θ
JC  
JA  
55°C/W  
56°C/W  
14°C/W  
16°C/W  
7.0 8XL196NP ERRATA  
Change identifiers have been used on embedded  
products since 1990. The change identifier is the  
last character in the FPO number. The FPO number  
is typically a nine character number located on the  
second line of the topside package mark. The  
following errata listing is applicable to the B–step  
(denoted by a “B” or “C” at the end of the topside  
tracking number):  
1. Any jump, conditional jump, or call instruction  
located within six bytes of the top of a page,  
i.e., 0FFFA–0FFFFH, may cause a jump to the  
wrong page. To ensure this problem does not  
occur, place at least six NOPs at the top of  
each page.  
8.0 DATASHEET REVISION HISTORY  
This datasheet is valid for devices with an “A” at the  
end of the topside tracking number. Datasheets are  
changed as new device information becomes  
available. Verify with your local Intel sales office that  
you have the latest version before finalizing a  
design or ordering devices.  
34  
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