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3SK324

型号：

3SK324

描述：

硅N沟道双栅MOS FET的UHF射频低噪声放大器[ Si Nch Dual Gate MOS FET UHF RF LOW NOISE Amplifier ]

品牌：

RENESAS[ RENESAS TECHNOLOGY CORP ]

页数：

8 页

PDF大小：

86 K

下载PDF手册
3SK324  
Si Nch Dual Gate MOS FET  
UHF RF LOW NOISE Amplifier  
REJ03G0532-0100  
Rev.1.00  
May 18, 2005  
Features  
•
•
•
•
Low noise characteristics; NF = 1.0 dB typ. (at f = 900 MHz)  
High gain characteristics; PG = 24 dB typ. (at f = 900 MHz)  
Capable low voltage operation; +B = 3.5 V  
High Endurance Voltage; VDS = 6 V  
Outline  
RENESAS Package code: PTSP0004ZA-A  
(Package name: CMPAK-4)  
2
1. Source  
2. Gate1  
3. Gate2  
4. Drain  
3
1
4
Notes:  
1. Marking is “UG-”.  
Absolute Maximum Ratings  
(Ta = 25°C)  
Item  
Symbol  
Ratings  
Unit  
Drain to source voltage  
VDS  
6
V
+6  
–6  
Gate1 to source voltage  
Gate2 to source voltage  
VG1S  
VG2S  
V
V
+6  
–6  
Drain current  
ID  
20  
250  
mA  
mW  
°C  
Channel power dissipation  
Channel temperature  
Storage temperature  
Pch*2  
Tch  
150  
Tstg  
–55 to +150  
°C  
Notes: 2. Value on the glass epoxy board (50 mm × 40 mm × 1 mm).  
Rev.1.00, May 18,2005, page 1 of 7  
3SK324  
Electrical Characteristics  
(Ta = 25°C)  
Item  
Symbol  
V(BR)DSS  
V(BR)G1SS  
V(BR)G2SS  
IG1SS  
Min  
6
Typ  
—
Max  
—
Unit  
V
Test Conditions  
Drain to source breakdown voltage  
Gate1 to source breakdown voltage  
Gate2 to source breakdown voltage  
Gate1 to source cutoff current  
Gate2 to source cutoff current  
Gate1 to source cutoff voltage  
Gate2 to source cutoff voltage  
Forward transfer admittance  
ID = 200 µA, VG1S = VG2S = 0  
IG1 = ±10 µA, VG2S = VDS = 0  
IG2 = ±10 µA, VG1S = VDS = 0  
±6  
±6  
—
—
0
—
—
V
—
—
V
—
±100  
±100  
1
nA VG1S = ±5 V, VG2S = VDS = 0  
nA VG2S = ±5 V, VG1S = VDS = 0  
IG2SS  
—
VG1S(off)  
VG2S(off)  
|yfs|  
0.5  
0.7  
42  
V
V
VDS = 5 V, VG2S = 3V, ID = 100 µA  
VDS = 5 V, VG1S = 3 V, ID = 100 µA  
0.3  
30  
1.1  
—
mS VDS = 3.5 V, ID = 10 mA,  
VG2S = 3 V, f = 1 kHz  
Power gain  
Noise figure  
PG  
NF  
20  
—
24  
—
dB VDS = 3.5 V, ID = 10 mA,  
VG2S = 3 V, f = 900 MHz  
1.0  
1.6  
dB  
900MHz PG, NF Test Circuit  
VD  
VG2  
VG1  
C6  
C4  
R1  
C5  
R2  
C3  
R3  
RFC  
Output (50 Ω)  
D
G2  
G1  
L4  
L3  
Input (50 Ω)  
S
L1  
L2  
C1  
C2  
:
:
:
:
:
:
Variable Capacitor (10 pF MAX)  
Disk Capacitor (1000 pF)  
Air Capacitor (1000 pF)  
47 kΩ  
47 kΩ  
4.7 kΩ  
C1, C2  
C3  
C4 to C6  
R1  
R2  
R3  
L1:  
L3:  
L2:  
10  
26  
(φ1 mm Copper wire)  
Unit : mm  
21  
29  
18  
L4:  
RFC : φ1mm Copper wire with enamel 4 turns inside dia 6 mm  
Rev.1.00, May 18,2005, page 2 of 7  
3SK324  
Main Characteristics  
Maximum Channel Power  
Dissipation Curve  
Typical Output Characteristics  
20  
1.3 V  
400  
300  
200  
100  
1.2 V  
VG2S = 3 V  
1.1 V  
15  
10  
5
1.0 V  
0.9 V  
0.8 V  
0.7 V  
VG1S = 0.6 V  
0
0
0
1
2
3
4
5
50  
100  
150  
200  
Drain to Source Voltage VDS (V)  
Ambient Temperature Ta (°C)  
Note 3 : When using the glass epoxy board  
(50 mm x 40 mm x 1 mm )  
Drain Current vs.  
Gate1 to Source Voltage  
Drain Current vs.  
Gate1 to Source Voltage  
20  
15  
20  
15  
VDS = 5 V 3.0 V  
2.5 V  
VDS =3.5 V  
3.0 V  
2.5 V  
2.0 V  
2.0 V  
1.5 V  
1.5 V  
10  
5
10  
5
0
1.0 V  
1.0 V  
VG2S = 0.5 V  
1.5 2.0  
VG2S = 0.5 V  
0
0.0  
0.0  
0.5  
1.0  
0.5  
1.0  
1.5  
2.0  
Gate1 to Source Voltage VG1S (V)  
Gate1 to Source Voltage VG1S (V)  
Forward Transfer Admittance  
vs. Gate1 to Source Voltage  
Forward Transfer Admittance  
vs. Gate1 to Source Voltage  
50  
40  
30  
20  
50  
40  
30  
20  
V
DS = 5 V  
V
DS = 3.5 V  
VG2S = 3 V  
VG2S = 3 V  
2.5 V  
2.5 V  
2 V  
10  
0
10  
0
2 V  
2.0  
1.5 V  
1.0 V  
1.5  
1.5 V  
1.5  
1.0 V  
1.0  
0.0  
0.5  
1.0  
2.0  
0.0  
0.5  
Gate1 to Source Voltage VG1S (V)  
Gate1 to Source Voltage VG1S (V)  
Rev.1.00, May 18,2005, page 3 of 7  
3SK324  
Gain Reduction vs.  
Drain Current vs.  
Gate2 to Source Voltage  
Power Gain, Noise Figure  
40  
30  
20  
3.0  
2.0  
ID = 10 mA (start)  
f = 900 MHz  
PG  
NF  
35  
30  
25  
20  
15  
10  
10  
0
1.0  
0.0  
VDS = 3.5 V  
G2S = 3.0 V  
f = 900 MHz  
5 V  
V
5
0
V
DS = 3.5 V  
1
0
2
3
4
0
5
10  
15  
20  
Gate2 to Source Voltage V  
(V)  
Drain Current ID (mA)  
G2S  
Gate2 to Source Voltage vs.  
Power Gain, Noise Figure  
Drain to Source Voltage vs.  
Power Gain, Noise Figure  
30  
20  
3.0  
2.0  
30  
20  
3.0  
2.0  
PG  
NF  
PG  
NF  
10  
0
1.0  
0.0  
10  
0
1.0  
0.0  
V
DS = 3.5 V  
VG2S = 3.0 V  
D ≅ 10 mA  
I
D = 10 mA (start)  
I
f = 900 MHz  
f = 900 MHz  
1.0  
1.5  
2.0  
2.5  
3.0  
1
2
3
4 5  
Gate2 to Source Voltage V  
(V)  
Drain to Source Voltage  
V
(V)  
G2S  
DS  
Maximum Stable Gain vs. Drain Current  
5 V  
Maximum Stable Gain vs. Drain Current  
30  
25  
20  
30  
25  
VG2S = 3.0 V  
f = 2 GHz  
VDS = 3.5 V  
20  
15  
15  
5 V  
10  
5
10  
5
VDS = 3.5 V  
VG2S = 3.0 V  
f = 900 MHz  
0
0
0
5
10  
15  
20  
0
5
10  
15  
20  
Drain Current ID (mA)  
Drain Current ID (mA)  
Rev.1.00, May 18,2005, page 4 of 7  
3SK324  
Maximum Stable Gain vs. Frequency  
40  
30  
20  
10  
VDS = 3.5 V  
G2S = 4 V  
D = 10 mA  
0
V
I
-10  
0.0 0.5 1.0 1.5  
2.0  
2.5 3.0  
Frequency f (GHz)  
Rev.1.00, May 18,2005, page 5 of 7  
3SK324  
S parameter  
(VDS = 3.5 V, VG2S = 4 V, ID = 10 mA, Zo =50 Ω)  
S11  
S21  
S12  
S22  
f (GHz)  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
Mag  
Phase  
-6.0  
Mag  
4.33  
4.23  
4.15  
4.06  
3.94  
3.84  
3.73  
3.62  
3.52  
3.42  
3.30  
3.19  
3.08  
2.97  
2.84  
2.63  
2.28  
1.77  
1.47  
Phase  
170.1  
160.5  
151.2  
142.1  
133.5  
125.0  
116.7  
108.6  
100.5  
92.5  
Mag  
Phase  
139.0  
84.8  
Mag  
Phase  
-6.1  
0.996  
0.989  
0.973  
0.956  
0.940  
0.920  
0.899  
0.879  
0.858  
0.840  
0.816  
0.794  
0.772  
0.752  
0.734  
0.727  
0.754  
0.825  
0.877  
0.002  
0.003  
0.003  
0.004  
0.004  
0.003  
0.004  
0.005  
0.010  
0.014  
0.020  
0.028  
0.036  
0.048  
0.058  
0.069  
0.079  
0.092  
0.111  
0.992  
0.988  
0.978  
0.963  
0.948  
0.931  
0.915  
0.899  
0.883  
0.869  
0.857  
0.846  
0.838  
0.835  
0.837  
0.849  
0.867  
0.869  
0.847  
-11.7  
-17.1  
-22.6  
-27.8  
-32.9  
-37.7  
-42.4  
-46.9  
-51.3  
-55.5  
-59.3  
-62.8  
-66.0  
-68.5  
-69.7  
-70.0  
-73.3  
-80.3  
-11.9  
-17.7  
-23.5  
-28.9  
-34.4  
-39.6  
-44.7  
-49.7  
-54.5  
-59.3  
-63.9  
-68.5  
-72.9  
-77.3  
-82.4  
-88.1  
-95.5  
-102.1  
96.9  
75.9  
82.6  
91.7  
132.5  
157.1  
169.9  
173.8  
174.8  
175.0  
169.6  
165.1  
160.8  
156.3  
152.6  
152.4  
150.7  
84.4  
76.2  
67.8  
59.2  
49.4  
38.2  
26.6  
20.3  
24.7  
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
3.0  
0.890  
0.882  
0.867  
0.851  
0.834  
0.816  
0.795  
0.771  
0.744  
0.713  
0.677  
-88.0  
-94.7  
1.45  
1.52  
1.56  
1.58  
1.56  
1.54  
1.50  
1.47  
1.43  
1.39  
1.36  
29.7  
28.9  
25.0  
19.9  
14.4  
8.8  
0.136  
0.162  
0.192  
0.223  
0.256  
0.294  
0.333  
0.374  
0.416  
0.458  
0.497  
147.2  
142.4  
136.6  
130.5  
123.9  
117.3  
109.8  
101.9  
93.6  
0.818  
0.796  
0.780  
0.766  
0.753  
0.739  
0.724  
0.706  
0.681  
0.654  
0.624  
-108.0  
-112.9  
-117.7  
-122.4  
-127.3  
-132.2  
-137.2  
-142.2  
-146.9  
-151.2  
-154.8  
-100.9  
-106.6  
-112.1  
-117.5  
-122.8  
-128.1  
-133.2  
-138.1  
-142.4  
3.2  
-2.2  
-7.7  
-12.9  
-18.3  
84.6  
74.7  
Rev.1.00, May 18,2005, page 6 of 7  
3SK324  
Package Dimensions  
JEITA Package Code  
SC-82A  
RENESAS Code  
Package Name  
MASS[Typ.]  
0.006g  
PTSP0004ZA-A  
CMPAK-4(T) / CMPAK-4(T)V  
D
A
e2  
B
e
Q
b1  
c
B
E
HE  
LP  
Reference  
Symbol  
Dimension in Millimeters  
Min  
0.8  
0
Nom  
Max  
1.1  
0.1  
1.0  
L
A
A
A
A
1
2
3
A
A
L1  
0.8  
0.9  
0.25  
0.32  
0.42  
0.3  
A3  
b
b
0.25  
0.35  
0.4  
0.5  
x
S
A
M
e2  
e
b
1
b
2
b
3
0.4  
c
0.1  
0.13  
0.11  
2.0  
0.15  
c
1
A2  
A1  
A
l1  
D
E
e
1.8  
2.2  
1.15  
1.25  
0.65  
1.35  
e
H
0.6  
2.1  
2
b5  
y
S
1.8  
0.3  
0.1  
0.2  
2.4  
0.7  
e1  
E
S
L
L
1
0.5  
b
b1  
b3  
L
P
0.6  
l1  
b2  
x
y
0.05  
0.05  
0.45  
0.55  
c1  
c
1
b
b
e
4
5
1
c
c
b4  
Pattern of terminal position areas  
1.5  
0.2  
l
0.9  
1
A-A Section  
B-B Section  
Q
Ordering Information  
Part Name  
Quantity  
Shipping Container  
3SK324UG-  
3000 pcs.  
Taping  
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of  
production before ordering the product.  
Rev.1.00, May 18,2005, page 7 of 7  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,  
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's  
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.  
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,  
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.  
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of  
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is  
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product  
information before purchasing a product listed herein.  
The information described here may contain technical inaccuracies or typographical errors.  
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.  
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor  
home page (http://www.renesas.com).  
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to  
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes  
no responsibility for any damage, liability or other loss resulting from the information contained herein.  
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life  
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a  
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater  
use.  
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.  
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and  
cannot be imported into a country other than the approved destination.  
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.  
RENESAS SALES OFFICES  
http://www.renesas.com  
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.  
Renesas Technology America, Inc.  
450 Holger Way, San Jose, CA 95134-1368, U.S.A  
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501  
Renesas Technology Europe Limited  
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.  
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900  
Renesas Technology Hong Kong Ltd.  
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong  
Tel: <852> 2265-6688, Fax: <852> 2730-6071  
Renesas Technology Taiwan Co., Ltd.  
10th Floor, No.99, Fushing North Road, Taipei, Taiwan  
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999  
Renesas Technology (Shanghai) Co., Ltd.  
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China  
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952  
Renesas Technology Singapore Pte. Ltd.  
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632  
Tel: <65> 6213-0200, Fax: <65> 6278-8001  
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .2.0  
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 		3SK108R 晶体管| MOSFET | N沟道| 20V V（ BR ） DSS |我30MA （D ） | DIP\n[ TRANSISTOR | MOSFET | N-CHANNEL | 20V V(BR)DSS | 30MA I(D) | DIP ] 1 页

ETC

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