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EZ80L925048MOD

型号：

EZ80L925048MOD

描述：

eZ80L92模块是一个紧凑的，高性能的以太网模块[ eZ80L92 Module is a compact, high-performance Ethernet module ]

品牌：

ZILOG[ ZILOG, INC. ]

页数：

38 页

PDF大小：

405 K

下载PDF手册
eZ80L925048MOD  
eZ80L92 Module  
Product Specification  
PS017005-0903  
PRELIMINARY  
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126  
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com  
This publication is subject to replacement by a later edition. To determine whether  
a later edition exists, or to request copies of publications, contact:  
ZiLOG Worldwide Headquarters  
532 Race Street  
San Jose, CA 95126  
Telephone: 408.558.8500  
Fax: 408.558.8300  
www.ZiLOG.com  
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other  
products and/or service names mentioned herein may be trademarks of the companies with which  
they are associated.  
Document Disclaimer  
©2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,  
applications, or technology described is intended to suggest possible uses and may be superseded.  
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF  
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS  
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY  
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR  
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval  
ZiLOG, use of information, devices, or technology as critical components of life support systems is  
not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document  
under any intellectual property rights.  
PS017005-0903  
P R E L I M I N A R Y  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
iii  
Table of Contents  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v  
The eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . 13  
EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
®
Mounting the Module onto the eZ80 Development Platform . . . . . . . . . . . . . . 19  
ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
The eZ80L92 Module Product Specification . . . . . . . . . . . . . . . . . . . . . . . . 32  
PS017005-0903  
P R E L I M I N A R Y  
Table of Contents  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
iv  
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
PS017005-0903  
P R E L I M I N A R Y  
Table of Contents  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
iv  
List of Figures  
Figure 1. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3  
Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . 4  
Figure 3. eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . 8  
Figure 4. Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Figure 5. Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 6. Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Figure 7. Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Figure 8. Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Figure 9. eZ80L92 Module Schematic Diagram, #1 of 9—Top Level . . . . . . . 23  
Figure 10. eZ80L92 Module Schematic Diagram, #2 of 9—100-Pin QFP  
eZ80L92 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Figure 11. eZ80L92 Module Schematic Diagram, #3 of 9—  
36-Pin SRAM Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Figure 12. eZ80L92 Module Schematic Diagram, #4 of 9—NOR Flash Device 26  
Figure 13. eZ80L92 Module Schematic Diagram, #5 of 9—E-NET Module . . . 27  
Figure 14. eZ80L92 Module Schematic Diagram, #6 of 9—IrDA Reset . . . . . . 28  
Figure 15. eZ80L92 Module Schematic Diagram, #7 of 9—Headers . . . . . . . . 29  
Figure 16. eZ80L92 Module Schematic Diagram, #8 of 9—Power Supply . . . 30  
Figure 17. eZ80L92 Module Schematic Diagram, #9 of 9—Control Logic . . . . 31  
PS017005-0903  
P R E L I M I N A R Y  
List of Figures  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
v
List of Tables  
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5  
Table 2. eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8  
Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14  
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
PS017005-0903  
P R E L I M I N A R Y  
List of Tables  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
1
The eZ80L92 Module  
The eZ80L92 Module is a compact, high-performance Ethernet module specially  
designed for the rapid development and deployment of embedded systems  
requiring control and Internet/Intranet connectivity.  
This low-cost, expandable module is powered by ZiLOG’s latest power-efficient,  
high-speed, optimized pipeline architecture eZ80L92 device (eZ80L925048MOD),  
®
a member of ZILOG’s new eZ80 microprocessor family.  
The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch micro-  
processor, which can operate with a clock speed of 48MHz. It can operate in Z80-  
compatible addressing mode (64KB) or full 24-bit addressing mode (16MB).  
The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of  
applications, including industrial control, IrDA connectivity, communication, secu-  
rity, automation, point-of-sale terminals, and embedded networking applications.  
Module Features  
•
eZ80L92 MPU default factory operating clock frequency at 48MHz  
•
•
•
•
•
•
•
•
•
10Base-T Ethernet Media Access Controller+ PHI with Onboard RJ45 connector  
512KB zero-wait-state onboard SRAM  
1MB onboard NOR Flash ROM (90–100ns)  
GoldCap backup for Real-Time Clock  
I/O connector provides 24 general-purpose 5V-tolerant I/O pinouts  
ZiLOG’s industry-leading IrDA transceiver—ZiLOG ZHX1810  
In-circuit Flash programming circuitry  
2
Onboard connector provides I C 2-wire SDA/SCL interface  
Onboard connector provides I/O bus for external peripheral connections (IRQ,  
CS, 24 address, 8 data)  
•
•
•
•
•
Low-cost adaptation to carrier board via two 2x25pin (2.54mm) headers  
®
Horizontal or vertical mounting onto the eZ80 Development Platform  
Small footprint 64x64mm; height is 24mm  
3.3V power supply  
Standard operating temperature range: 0ºC to +70ºC  
PS017005-0903  
P R E L I M I N A R Y  
The eZ80L92 Module  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
2
eZ80L92 Processor Features  
®
•
•
Single-cycle instruction fetch, high-performance, pipelined eZ80 CPU core  
Low power features including SLEEP mode, HALT mode, and selective  
peripheral power-down control  
•
•
•
•
•
•
Two UARTs with independent baud rate generators  
SPI with independent clock rate generator  
2
I C with independent clock rate generator  
Infrared Data Association (IrDA)-compliant infrared encoder/decoder  
®
New DMA-like eZ80 instructions for efficient block data transfer  
Glueless external memory interface with 4 chip selects, individual wait state  
generators, and an external WAIT input pin—supports Intel- and Motorola-style  
buses  
•
•
Fixed-priority vectored interrupts (both internal and external) and interrupt  
controller  
Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and  
separate VDD pin for battery backup  
•
•
•
•
•
•
•
Six 16-bit Counter/Timers with prescalers and direct input/output drive  
Watch-Dog Timer  
24 bits of general-purpose I/O  
JTAG and ZDI debug interfaces  
100-pin LQFP package  
3.0–3.6V supply voltage with 5V tolerant inputs  
Standard operating temperature range: 0ºC to +70ºC  
Note:  
All signals with an overline are active Low. For example, B/W, for which  
WORD is active Low, and B/W, for which BYTE is active Low.  
Block Diagram  
Figure 1 illustrates a block diagram of the eZ80L92 Module.  
PS017005-0903  
P R E L I M I N A R Y  
The eZ80L92 Module  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
3
Gold Cap  
32 KHz XTAL  
XTAL/Osc.  
eZ80 CPU  
IrDA  
Transceiver  
Real-Time Clock  
Power-On  
Reset  
Watch-Dog  
Timer  
UART  
UART  
PD  
PC  
PB  
ZDI/JTAG  
I2C/SPI  
SPI  
6 Timer  
RJ45  
Bus Controller  
10 BaseT  
Controller  
w/ Magnetics  
1 MB  
Flash/ROM  
128/512 KB  
SRAM  
50-Pin Connector  
Figure 1. eZ80L92 Module Functional Block Diagram  
PS017005-0903  
P R E L I M I N A R Y  
The eZ80L92 Module  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
4
Pin Description  
Peripheral Bus Connector  
Figure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position  
JP1 on the eZ80L92 Module. Table 1 describes the pins and their functions.  
JP1  
A0  
A3  
V3.3_EXT  
A7  
A9  
A14  
A16  
GND_EXT  
A1  
A12  
A20  
A17  
DIS_FLASH  
V3.3_EXT  
A23  
CS1  
D0  
D2  
D4  
A6  
A10  
GND_EXT  
A8  
1
3
5
7
2
4
6
8
A13  
A15  
A18  
A19  
A2  
A11  
A4  
A5  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
DIS_ETH  
A21  
A22  
CS0  
CS2  
D1  
D3  
D5  
D7  
GND_EXT  
D6  
IOREQ  
RD  
INSTRD  
BUSREQ  
MREQ  
GND_EXT  
WR  
BUSACK  
HEADER 25X2  
IDC50  
Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
5
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification*  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
1
A6  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
2
A0  
3
A10  
A3  
4
5
GND  
V
/Ground (0V).  
SS  
6
V
3.3V Supply Input Pin.  
DD  
7
A8  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
8
A7  
9
A13  
A9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A15  
A14  
A18  
A16  
A19  
GND  
A2  
V
/Ground (0V).  
SS  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
A1  
A11  
A12  
A4  
A20  
A5  
A17  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
®
timing requirements for the eZ80 CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
6
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
25  
DIS_Eth  
DIS_Flash  
A21  
PU 10KΩ  
Input  
A Low disables on-module EMAC from  
responding to CS3 on a per-cycle basis.  
CS3 can be used on the eZ80  
Development Platform; CMOS Input 3.3V  
(5V tolerant)  
®
26  
PU 10KΩ  
Input  
A Low disables on-module Flash memory  
from responding to CS0 on a per-cycle  
®
basis. CS0 can be used on the eZ80  
Development Platform for external memory  
purposes; CMOS Input 3.3V (5V tolerant).  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
Bidirectional  
V
3.3V supply input pin.  
DD  
A22  
A23  
CS0  
CS1  
CS2  
D0  
Bidirectional  
Bidirectional  
Output  
Output  
Output  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
PU 4k7Ω  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
D1  
D2  
D3  
D4  
D5  
GND  
D7  
V
/Ground (0V).  
SS  
PU 4k7Ω  
Bidirectional  
Bidirectional  
Bidirectional  
D6  
MREQ  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
®
timing requirements for the eZ80 CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
7
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)  
Pull  
Pin # Symbol  
Up/Down* Signal Direction Comments  
44  
45  
46  
47  
48  
49  
50  
IORQ  
GND  
Bidirectional  
V
/Ground (0V).  
SS  
RD  
Bidirectional  
Bidirectional  
Output  
WR  
INSTRD  
BUSACK  
BUSREQ  
PU 10KΩ  
PU 10KΩ  
Output  
Input  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
®
timing requirements for the eZ80 CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
8
I/O Connector  
Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position  
JP2 of the eZ80L92 Module. Table 2 describes the pins and their functions.  
JP2  
PB7  
PB5  
PB3  
PB6  
PB4  
PB2  
PB0  
PC7  
PC5  
PC3  
PC1  
PD7  
GND_EXT  
PD4  
PD2  
PD0  
1
3
5
7
2
4
6
PB1  
8
GND_EXT  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
PC6  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
PC4  
PC2  
PC0  
PD6  
PD5  
PD3  
PD1  
TDO  
TDI  
TRIGOUT  
TMS  
GND_EXT  
TCK  
RTC_VDD  
IICSCL  
IICSDA  
FLASHWE  
CS3  
EZ80CLK  
GND_EXT  
DIS_IRDA  
WAIT  
GND_EXT  
NMI  
RESET  
V3.3_EXT  
HALT_SLP  
V3.3_EXT  
HEADER 25X2  
IDC50  
Figure 3. eZ80L92 Module I/O Connector Pin Configuration  
Table 2. eZ80L92 Module I/O Connector Pin Identification*  
Pull  
Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
1
2
PB7  
PB6  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
9
Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
3
PB5  
PB4  
PB3  
PB2  
PB1  
PB0  
GND  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
PD7  
PD6  
GND  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
Bidirectional  
4
Bidirectional  
5
Bidirectional  
6
Bidirectional  
7
Bidirectional  
8
Bidirectional  
9
V
/Ground (0V).  
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
V
/Ground (0V).  
SS  
Bidirectional  
PD 4k7  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Bidirectional  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
10  
Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)  
Pull Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
27  
28  
29  
30  
31  
TDO  
Output  
JTAG data output pin.  
JTAG data input pin.  
TDI/ZDA  
GND  
PU 10KΩ Input  
V
/Ground (0V).  
SS  
TRIGOUT  
TCK/ZCL  
Output  
Active High trigger event indicator.  
PU 10KΩ Input  
JTAG clock. High on reset enables ZDI mode; Low  
on reset enables OCI debug.  
32  
33  
34  
35  
36  
37  
38  
39  
TMS  
PU 10KΩ Input  
JTAG Test Mode Select.  
RTC_V  
RTC supply from GoldCap (or external battery).  
48MHz synchronous CPU clock.  
DD  
EZ80CLK  
SCL  
Output  
2
PU 4k7  
PU 4k7  
Bidirectional  
Bidirectional  
I C Bus Clock.  
GND  
V
/Ground (0V).  
SS  
2
SDA  
I C Bus Data.  
V /Ground (0V).  
SS  
GND  
FlashWE  
PU 10KΩ Input  
Low enables Write to onboard Flash memory. If this  
pin is unconnected, the Flash memory is write-  
protected.  
40  
41  
42  
GND  
V
/Ground (0V).  
SS  
CS3  
Output  
PU 10KΩ Input  
Used on module for CS8900 EMAC.  
DIS_IRDA  
Low disables onboard IRDA transceiver to use PD0/  
PD1 UART pins externally.  
43  
44  
RESET  
WAIT  
PU 2k2  
PU 2k2  
Bidirectional  
Input  
Reset output from Module or push-button reset.  
®
Driving the WAIT pin Low forces the eZ80 CPU to  
provide additional clock cycles for an external  
peripheral or external memory to complete its Read  
or Write operation.  
45  
V
3.3V supply input pin.  
DD  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
11  
Table 2. eZ80L92 Module I/O Connector Pin Identification* (Continued)  
Pull  
Signal  
Pin # Symbol  
Up/Down Direction  
Comments  
V /Ground (0V).  
SS  
46  
47  
GND  
®
HALT_SLP  
Output, Active A Low on this pin indicates that the eZ80 CPU  
Low  
enters either HALT or SLEEP mode because of exe-  
cution of either a HALT or SLP instruction.  
48  
NMI  
PU 10KΩ Schmitt Trig- The NMI input is a higher priority input than the  
ger Input,  
Active Low  
maskable interrupts. It is always recognized at the  
end of an instruction, regardless of the state of the  
interrupt enable control bits. This input includes a  
Schmitt trigger to allow RC rise times. This external  
NMI signal is combined with an internal NMI signal  
generated from the WDT block before being con-  
®
nected to the NMI input of the eZ80 CPU.  
49  
50  
V
3.3V supply input pin.  
DD  
Reserved  
NC  
Reserved—No Connection.  
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10pF to satisfy  
timing requirements for the CPU.  
All unused inputs should be pulled to either V  
consumption and to reduce noise sensitivity.  
or GND, depending on their inactive levels, to reduce power  
DD  
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down  
Register.  
All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.  
PS017005-0903  
P R E L I M I N A R Y  
Pin Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
12  
Onboard Component Description  
Logic-Level I/Os  
The I/O connector features 24 general-purpose 3.3V CMOS I/O pins that can be  
used as outputs or inputs interfacing to external logic. All I/Os are 5V tolerant.  
Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/  
O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin).  
For more information on eZ80L92 dual modes, please refer to the eZ80L92 Prod-  
uct Specification (PS0130).  
Onboard Battery Backup  
An onboard 0.1F capacitor (GoldCap) is used to bridge power outages of 2–4  
hours if the power supply to the module is disconnected. The capacitor is charged  
to 3.1V during normal operation and is discharged through the on-chip Real Time  
Clock. The VRTC pin is available on the I/O connector of the module to connect  
external components to a power supply or to a larger GoldCap.  
Do not connect a Lithium Battery to the GoldCap capacitor, because  
onboard charging circuitry for the capacitor can destroy the lithium bat-  
tery.  
Caution:  
Ethernet Media Access Controller  
The eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is  
attached to the data/address bus of the processor. This chip is connected to the  
processor’s CS3 Chip Select, A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt  
purposes. Connection of pins PD6 and PD7 for LANACT (wake-up from sleep)  
and SLEEP is optional and resistor-selectable onboard (see below).  
Ethernet LEDs  
There are two green LEDs, a Link LED and a LAN LED, that are located adjacent  
to each other on the eZ80L92 Module. A flashing LAN LED (top) indicates  
received link pulses from the 10Base-T Ethernet. This LAN LED should be ON if  
RX+ is connected to TX+ and RX– is connected to TX–. A steady Link LED (bot-  
tom) indicates Traffic (RX or TX) on the LAN.  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
13  
An RJ45 loopback connector can be used to verify the correct operation of the  
Receiver and the Transmitter. The green LED should be on if RX+ is connected  
with TX+ and RX– is connected with TX–.  
Ethernet Connectors  
The eZ80L92 Module is equipped with an RJ45 connector that features integrated  
magnetics (transformer, common mode chokes). The remaining pins on the  
onboard RJ45 connector are not connected.  
Node assignments for the RJ45 Ethernet connector are shown in Table 3.  
Table 3. Ethernet Connector Pin Assignments  
Pin  
1
Function  
TX+  
2
TX–  
3
RX+  
6
RX–  
Node assignment, in contrast to hub assignment, means that a straight-through  
cable (equivalent pin numbers on both sides of the cable are connected to each  
other) is used to attach the board to an Ethernet hub or switch. To connect the  
eZ80L92 Module directly to another node (e.g., a personal computer), a crossover  
cable must be used.  
The EMAC can be additionally protected by placing a U9 ESD protection array on  
the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1  
(ST Microelectronics) devices.  
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt  
GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s  
INTRQ0 output.  
GPIO output bit PD7 can be used to enter the EMAC into SLEEP mode. When  
pulling SLEEP (PD7) Low after enabling HWStandbyE and HWSleepE modes,  
the chip draws lower current, because only the receiver is operating. A zero-Ohm  
resistor at position R14 on the eZ80L92 Module is required for this function. In this  
case, the PD6 pin is not available for GPIO on the I/O connector.  
If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is con-  
nected to GPIO input PD6 and can be used in interrupt edge-detection mode to  
wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
14  
the module is required for this function. In this case, the PD6 pin is not available  
for GPIO on the I/O connector.  
EMAC Ports  
Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base  
address is user-selectable. The EMAC is connected as an 8- or 16-bit device with  
8-word-wide I/O registers:  
EMAC Wait States  
The CS8900A EMAC should be operated in Intel bus mode so that the setup and  
hold times for the I/O access are met. For 48MHz operation, first set CS3_BMC (I/  
O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus  
cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a  
20.8ns CPU Clock cycle time, the Read and Write access time is:  
2 x 4 x 20.8ns–16ns (for capacitive and chip delays) = 150ns  
Memory  
The eZ80L92 Module offers SRAM and Flash memories and the wait states that  
support memory operations, as described in this section.  
Wait States  
To ensure that valid data is read from or written to slower memories, a number of  
wait states must be inserted into the memory or I/O access operations by the pro-  
cessor. The number of wait states that are required should be added by program-  
ming the chip select control registers. To calculate the minimum number of wait  
states required, refer to Table 4.  
Table 4. Chip Frequency to Wait State Cycle Time Calculation  
MHz  
12  
Cycle Time  
83.3ns  
20  
50.0ns  
24  
41.7ns  
36  
27.8ns  
40  
25.0ns  
48  
20.8ns  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
15  
Static RAM  
The eZ80L92 Module features 512KB of fast SRAM. Access speed is typically  
12ns or faster, allowing zero-wait-state operation at 48MHz. With the CPU at  
48MHz, onboard SRAM can be accessed with zero wait states in eZ80 mode.  
CS1_CTL (chip select CS1) can be set to 08h (no wait states).  
Flash Memory  
The Flash Boot Loader, application code, and user configuration data are held  
permanently in NOR Flash memory. A typical application requires eight times  
more ROM for code than RAM. As an example, for 128KB onboard SRAM, 1MB  
of ROM is required. The eZ80L92 Module allows NOR Flash memories between  
4megabits (512KB) and 32 megabits (4MB) to be used. The chips are housed in  
wide TSOP40 cases. Flash ROM access times are 55–150ns; typically 90ns.  
NOR Flash should be operated in Intel bus mode to satisfy setup and hold times  
and to prevent bus contention with a Write cycle that could possibly follow. For  
proper CPU operation at 48MHz, first set the bus mode control register  
CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register  
CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with  
two system clocks per bus cycle and zero wait states.  
IrDA Transceiver  
An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1  
(RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type  
870nm Class 1.  
The receiver supply current is 90–150µA and the transmitter supply current is  
260mA when the LED is active.The IrDA transceiver is accessible via the IrDA  
controller attached to UART0 on the eZ80L92 device. The UART0 console and  
the IrDA transceiver cannot be used simultaneously.  
To use the UART0 for console or to save power, the transceiver can be disabled  
by the software or by an off-board signal when using the proper jumper selection.  
The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the  
DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings.  
To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.  
Reset Generator  
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip  
generates a reset pulse with a duration of 200ms if the power supply drops below  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
16  
2.93V. This reset pulse ensures that the board always starts in a defined condi-  
tion. The RESET pin on the I/O connector reflects the status of the RESET line. It  
is a bidirectional pin for resetting external peripheral components or for resetting  
the eZ80L92 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).  
Serial Interface Ports  
The processor contains two 16550-style UARTs with programmable baud rate  
generators. UART0 is typically used for console I/O and initial boot code upload or  
to connect remote peripherals that can be controlled and monitored via Ethernet.  
UART0 is connected to GPIO PD[0:3] on the I/O connector. There are no RS232-  
level shifters on the eZ80L92 Module.  
Do not connect an RS-232 interface without level shifters.  
Note:  
UART1 can be used for modem attachment or as a communications port to a host  
computer, where the embedded Ethernet module emulates an AT-style modem for  
internet access. UART1 does not offer onboard RS232-level shifters.  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
17  
Physical Dimensions  
The size of the eZ80L92 Module PCB is 64x64mm. With an RJ45 Ethernet con-  
nector, the overall height is 25mm, as shown in Figure 4.  
63.5 mm  
16 mm  
8.5 mm  
Link  
LAN  
13.7 mm  
8.3 mm  
max.  
LEDs  
1
1
2.54 mm  
16.3 mm  
RJ45  
9 mm  
3.5 mm  
64 mm  
Top View  
9 mm  
IrDA  
2.7 mm  
6.2 mm  
7 mm  
55.88 mm  
Figure 4. Dimension Drawing  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
18  
Figure 5 illustrates a top view of the eZ80L92 Module.  
Figure 5. Top Layer  
Figure 6 illustrates a bottom view of the eZ80L92 Module.  
Figure 6. Bottom Layer  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
19  
Mounting the Module onto the eZ80® Development Platform  
The eZ80L92 Module can be mounted in several positions. Depending on volume  
and area restrictions, it can be mounted horizontally or vertically with or without  
®
components between the connectors on the eZ80 Development Platform. See  
Figure 8 for examples.  
Low Profile Mounting  
s
D
RJ45  
(rear)  
63.5 mm  
E
L
1
1
15.3 mm  
8.3 mm  
64 mm  
E-NET Module  
Bus  
H = 4.5 mm  
1.7 mm  
I/O  
Carrier Board  
4.2 mm  
Stacked Mounting  
RJ45  
(rear)  
1
1
64 mm  
E-NET Module  
Bus  
I/O  
H = 4.5 mm  
8.5 mm  
Modem or Power Supply  
50.5 mm max  
Carrier Board  
Figure 7. Mounting Examples  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
20  
ESD/EMI Protection  
Caution:  
The eZ80L92 Module is a component that is intended to be part of a  
system design for end-user devices. Therefore, the user must exercise  
caution to use ESD protection on the I/O pins.  
The EMAC can be additionally protected by placing an ESD protection array on  
the eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelec-  
tronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used  
for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD cur-  
rents from flowing through the digital circuitry.  
The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and  
common mode chokes for EMI suppression.  
CMOS I/Os are ESD-sensitive and must be handled with care. Han-  
dling of the module should be performed in ESD-safe environments (for  
example with a wrist-wrap attached). When developing applications,  
the user must provide for proper ESD protection on external, user-  
accessible I/Os (e.g. suppressor arrays for the I/Os).  
Caution:  
The components are mounted on a multilayer PCB to provide a stable ground  
plane for onboard components. The module features several GND pins next to  
pins with higher switching frequency for short ground returns. If unused, the clock  
output can be separated from the module header by removing a series resistor on  
the module. Removing the series resistor further reduces electromagnetic emis-  
sions.  
Absolute Maximum Ratings  
Stresses greater than those listed in Table 5 can cause permanent damage to the  
device. These ratings are stress ratings only. Operation of the device at any con-  
dition outside those indicated in the operational sections of these specifications is  
not implied. Exposure to absolute maximum rating conditions for extended peri-  
ods may affect device reliability. For improved reliability, unused inputs should be  
tied to one of the supply voltages (VDD or VSS).  
Table 5. Absolute Maximum Ratings  
Parameter  
Min  
0
Max  
+70  
+85  
90%  
3.3  
Units  
ºC  
Standard operating temperature  
Storage temperature  
–45  
25%  
—
ºC  
Operating Humidity (RH @ 50ºC)  
Operating Voltage ( 5%)  
V
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
21  
Power Supply  
The eZ80L92 Module requires a regulated external 3.3VDC/0.5A power supply.  
You may use a Low Dropout Regulator (LDO) to get 3.3V from 5V or use the fol-  
lowing switcher circuit to generate 3.3V from unregulated 10-28V power supply.  
Power connections follow these conventional descriptions:  
Connection  
Power  
Circuit  
VCC  
Device  
V
V
DD  
SS  
Ground  
GND  
Figure 8 offers two typical power supply examples.  
Switcher 10–28V → 3.3V  
To Module  
U1  
LM2575S-ADJ  
4
2
L1  
10–28V  
VDD  
3.3V  
FB  
VOUT  
N
1
V
VIN  
O
IN  
330uH/1A  
R1  
5k6  
1%  
C3  
/
G
N
D
O
F
F
C2  
C1  
100n  
D1  
1A/30V  
1000uF  
470uF/6.3V  
Low ESR  
R2  
3
5
3k3  
1%  
GND  
GND  
LDO 5V → 3.3V  
U1  
LM3940  
4-6V  
VDD  
V
VI  
VO  
3.3V  
CC  
G
N
D
C3  
470uF/6.3V  
Low ESR  
C1  
100n  
GND  
GND  
Figure 8. Power Supply Examples  
PS017005-0903  
P R E L I M I N A R Y  
Onboard Component Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
22  
Document Number Description  
The Document Control Number that appears in the footer of each page of this  
document contains unique identifying attributes, as indicated in the following  
table:  
PS  
Product Specification  
Unique Document Number  
Revision Number  
0170  
05  
0903  
Month and Year Published  
Change Log  
Rev Date  
Purpose  
Original issue  
By  
01 June 2002  
02 July 2002  
03 October 2002  
04 January 2003  
M. Staubermann, R. Pujar  
M. Staubermann, R. Beebe  
R. Beebe  
Minor modifications  
Minor modifications  
Minor modifications  
R. Beebe  
05 September 2003 Minor modifications  
R. Beebe  
PS017005-0903  
P R E L I M I N A R Y  
Document Number Description  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
Schematic Diagrams  
23  
Figures 9 through 17 diagram the layout of the eZ80L92 Module.  
RAM  
CPU  
Peripherals  
Reset  
Connector  
Headers  
03  
02  
07  
08  
SRAM  
eZ80  
IRDA_TXD  
IRDA_RXD  
IRDA_SD  
IRDA_TXD  
D[0..7]  
-RESET  
-RESET  
D[0..7]  
D[0..7]  
-RESET  
-RESET IRDA_RXD  
IRDA_SD  
-RESET  
A[0..23]  
-FLASHWE  
A[0..23]  
A[0..23]  
-FLASHWE  
-RD  
-WR  
-IOREQ  
-MREQ  
-INSTRD  
-IOREQ  
-MREQ  
-INSTRD  
-RD  
-WR  
-RD  
-WR  
-IOREQ  
-MREQ  
-INSTRD  
-IOREQ  
-MREQ  
-INSTRD  
-CS1  
-CS1  
-WAIT  
-HALT_SLP  
-WAIT  
-HALT_SLP  
-WAIT  
-HALT_SLP  
-WAIT  
-HALT_SLP  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSACK  
-NMI  
-NMI  
ROM  
-NMI  
CLK_OUT  
RTC_VDD  
-NMI  
04  
CLK_OUT  
RTC_VDD  
CLK_OUT  
RTC_VDD  
NOR-Flash  
CLK_OUT  
RTC_VDD  
D[0..7]  
D[0..7]  
A[0..23]  
A[0..23]  
Logic  
06  
IICSDA  
IICSCL  
IICSDA  
IICSCL  
IICSDA  
IICSCL  
IICSDA  
IICSCL  
-RD  
-WR  
CTRL-Logic  
-RD  
-WR  
D[0..7]  
D[0..7]  
-CSFLASH  
-RESFLASH  
-FLASHWE  
-RESET  
-WAIT  
-CSFLASH  
-RESFLASH  
-FLASHWE  
-RESET  
-WAIT  
A[0..23]  
A[0..23]  
PB[0..7]  
PC[0..7]  
PD[0..7]  
IRDA_TXD  
IRDA_RXD  
IRDA_SD  
PB[0..7]  
PC[0..7]  
PD[0..7]  
IRDA_TXD  
-WR  
-RD  
IRDA_RXD  
IRDA_SD  
-DIS_FL  
-WR  
-RD  
-DIS_FL  
-DIS_FL  
-DIS_IRDA  
PB[0..7]  
PD[0..7]  
-CS[0..3]  
-DIS_IRDA  
-DIS_IRDA  
-CS[0..3]  
-CS[0..3]  
PB[0..7]  
PC[0..7]  
PD[0..7]  
-CSFLASH  
PC[0..7]  
PD[0..7]  
-CSFLASH  
JTAG[1..4]  
TDO  
-RESFLASH  
JTAG[1..4]  
TDO  
-RESFLASH  
-CS[0..3]  
-CS[0..3]  
JTAG[1..4]  
TDO  
JTAG[1..4]  
TDO  
-DIS_ETH  
Ethernet  
05  
Power  
09  
V3.3  
GND  
CS8900A  
V3.3_EXT  
GND_EXT  
SD[0..7]  
SA[0..3]  
PowerSupply  
SD[0..7]  
SA[0..3]  
V3.3  
GND  
V3.3  
GND  
IOCHRDY  
-ETHRD  
-ETHWR  
IOCHRDY  
-ETHRD  
-ETHWR  
ETHIRQ  
-SLEEP  
-ACTIVE  
ETHIRQ  
-SLEEP  
-ACTIVE  
-DIS_ETH  
Figure 9. eZ80L92 Module Schematic Diagram, #1 of 9—Top Level  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
24  
XIN  
eZ80=IIC-bus-master  
PB[0..7]  
PC[0..7]  
48 MHz  
Y2  
IICSDA  
XOUT  
IICSDA  
IICSDA  
IICSCL  
HC49SM  
IICSCL  
IICSCL  
CLK_OUT  
1M  
C17  
R27  
CLK_OUT  
CLK_OUT  
L1  
C16  
15pF  
4.7pF  
3.3 H  
PB[0..7]  
PC[0..7]  
PD[0..7]  
PB[0..7]  
PC[0..7]  
PD[0..7]  
PD[0..7]  
A0  
A1  
A2  
A3  
A4  
A5  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A0  
PD7/RI0  
C25  
2
A1  
PD6/DCD0  
PD5/DSR0  
PD4/DTR0  
PD3/CTS0  
PD2/RTS0/IR_SD  
PD1/RxD0/IR_RXD  
PD0/TxD0/IR_TXD  
VDD  
220pF  
3
A2  
4
A3  
-RESET  
V3.3  
5
6
-RESET  
A4  
A5  
VDD  
VSS  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
VDD  
VSS  
A15  
A16  
A17  
A18  
A19  
A20  
JTAG[1..4]  
TDO  
JTAG[1..4]  
7
JTAG[1..4]  
TDO  
8
U8  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
R28  
100  
9
TDO  
TDI  
(= JTAG0)  
= JTAG1  
TRIGOUT = JTAG2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
TDO  
-RD  
-RD  
-WR  
TDI (ZDA)  
TRIGOUT  
TCK (ZCL)  
TMS  
-WR  
TCK  
TMS  
= JTAG3  
= JTAG4  
eZ80L92  
TQFP100  
D1  
-IOREQ  
-MREQ  
-INSTRD  
-WAIT  
TMM BAT 41  
-IOREQ  
-MREQ  
-INSTRD  
VSS  
RTC_VDD  
RTC_XOUT  
RTC_XIN  
MINIMELF_AK  
RTC_VDD  
RTC_XOUT  
RTC_XIN  
VSS  
RTC_VDD  
GoldCap  
A15  
A16  
A17  
A18  
A19  
A20  
C18  
100nF  
VDD  
-HALT_SLP  
-BUSACK  
-BUSREQ  
-NMI  
C19  
-WAIT  
HALT_SLP  
BUSACK  
BUSREQ  
NMI  
0,1F  
-HALT_SLP  
GOLDCAP_SD  
-HALT_SLP  
R29  
-RESET  
10k  
RESET  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSACK  
R32  
RTC_XOUT  
RTC_XIN  
-NMI  
-NMI  
V3.3  
220  
Y3  
32.768kHz  
XTAL3  
C20  
18pF  
VDD  
VSS  
A[0..23]  
-CS[0..3]  
D[0..7]  
A[0..23]  
V3.3  
A[0..23]  
-CS[0..3]  
D[0..7]  
C24  
18pF  
-CS[0..3]  
GND  
V3.3  
V3.3  
D[0..7]  
C21  
1nF  
C22  
1nF  
C23  
1nF  
PLACE CAPS CLOSE  
TO PINS  
97,7,33,43  
RTC_VDD  
RTC_VDD  
Figure 10. eZ80L92 Module Schematic Diagram, #2 of 9—100-Pin QFP eZ80L92 Device  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
25  
D[0..7]  
D[0..7]  
RN1  
A[0..23]  
A21/A22/A23  
not used  
here  
A[0..23]  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
2
3
4
5
6
7
8
9
1
-CS1  
-RD  
-WR  
-CS1  
-RD  
-WR  
U1  
A20  
A16  
A18  
A0  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
A0  
A1  
N.C.  
A18  
A17  
A16  
A15  
OE  
I/O7  
I/O6  
VSS  
VDD  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
N.C.  
4.7k  
A1  
A15  
A14  
A13  
-RD  
D7  
3
A2  
A2  
A3  
-CS1  
D0  
D1  
4
A3  
5
A4  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
CE  
I/O0  
I/O1  
VDD  
VSS  
I/O2  
I/O3  
WE  
A5  
D6  
D2  
D3  
-WR  
A12  
A9  
A6  
A4  
D5  
D4  
A11  
A8  
A10  
A7  
A6  
A7  
A8  
A5  
A19  
A17  
A9  
512kx8 SRAM  
SOJ36.400  
C7  
100nF  
V3.3  
GND  
U2D  
VDD  
VSS  
9
8
74LVC04/SO  
U2F  
U2E  
11  
10  
13  
12  
74LVC04/SO  
74LVC04/SO  
Figure 11. eZ80L92 Module Schematic Diagram, #3 of 9—36-Pin SRAM Device  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
26  
D[0..7]  
A[0..23]  
Intel-Type  
U3  
A0  
DFLASH0  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
21  
20  
19  
18  
17  
16  
15  
14  
8
7
36  
6
5
4
25  
DQ0  
26  
=
=
=
=
=
=
=
=
A0  
A1  
DFLASH1  
DFLASH2  
DFLASH3  
DFLASH4  
DFLASH5  
DFLASH6  
DFLASH7  
A1  
DQ1  
27  
A2  
A3  
A4  
A2  
A3  
DQ2  
28  
DQ3  
32  
A4  
DQ4  
33  
A5  
A5  
DQ5  
34  
A6  
A6  
DQ6  
35  
VDD  
R1  
A7  
A7  
A8  
A9  
DQ7  
A8  
A9  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
-CSFLASH  
-RD  
-WR  
-RESFLASH  
-WP  
22  
CE  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
10K  
U2A  
24  
OE  
9
WE  
10  
12  
RP  
-FLASHWE  
3
2
1
WP  
2
0R  
R2  
VPP  
1
11  
VPP  
40  
13  
37  
A21  
A20  
74LVC04/SO  
29  
N.C.  
A20/A21 used for  
16/32Mbit-Flash  
38  
N.C.  
Pin37=N.C.  
for 4Mbit-  
Flashes  
MT28F008B3VG  
TSOP40.20MM  
C8  
100nF  
D[0..7]  
D[0..7]  
V3.3  
GND  
A[0..23]  
A22/A23  
not used here  
A[0..23]  
VDD  
VSS  
-CSFLASH  
-RD  
-WR  
-CSFLASH  
-RD  
-WR  
-RESFLASH  
-RESFLASH  
-FLASHWE  
-FLASHWE  
Note: Must be pulled 'low'  
externally for programming.  
Figure 12. eZ80L92 Module Schematic Diagram, #4 of 9—NOR Flash Device  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
27  
V3.3  
GND  
VDD  
VSS  
R19  
10k  
90 degree,  
stacked  
dual-LED  
R20  
220  
R21  
220  
0603  
green  
-LANLED  
0603  
LD1B  
3
4
2
-LANLED  
-LINKLED  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
SD9  
SD8  
LANLED  
LINKLED/HC0  
XTAL2  
XTAL1  
AVSS  
LD1A  
-LINKLED  
1
R22  
4k7  
MEMW  
MEMR  
INTRQ2  
INTRQ1  
INTRQ0  
IOCS16  
MEMCS16  
INTRQ3  
SHBE  
SA0  
SA1  
SA2  
SA3  
SA4  
Y1  
20.000 MHz  
HC49SM  
yellow  
AVDD  
AVSS  
RES  
RXD-  
RXD+  
AVDD  
AVSS  
TXD-  
TXD+  
AVSS  
AVDD  
DO-  
DO+  
CI-  
CI+  
DI-  
ETHIRQ  
R23  
4k99/1%  
U7  
RXD-  
RXD+  
ESD protection array  
U9  
CS8900A-CQ3  
TQFP100  
SA0  
SA1  
SA2  
SA3  
TXD-  
TXD+  
RD+  
RD-  
TD+  
TD-  
1
2
3
4
8
7
6
5
SA5  
SA[0..3]  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
REFRESH  
SA12  
DI+  
LCDA15C-6  
SO8.150  
BSTATUS/HC1  
SLEEP  
TEST  
-SLEEP  
int. Pull-Up  
-DIS_ETH  
GND  
GND  
J1  
8R2  
C12  
TXD-  
TD-  
TD+  
R24  
560pF  
TXD+  
1
1
2
2
3
3
4
4
5
5
6
6
device addresses:  
00300h bis 0030Fh  
8R2  
R25  
RXD-  
RD-  
CTD  
C13  
100nF  
-ETHRD  
CRD  
-ETHRD  
-ETHRD  
-ETHWR  
R26  
100  
-ETHWR  
-ETHWR  
IOCHRDY  
8
8
SD[0..7]  
RXD+  
RD+  
HFJ11-1041  
TX+ H<A-LO>FA1STJACK  
C14  
100nF  
C15  
R34  
10k  
0603  
100nF  
JP4  
through hole  
solder pad  
HEADER 1  
SIP1  
TX- <-> 2  
RX+ <-> 3  
RX- <-> 6  
SD[0..7]  
SA[0..3]  
ETHIRQ  
-SLEEP  
V3.3  
SD[0..7]  
SA[0..3]  
ETHIRQ  
place  
near  
J1  
don't  
stuff  
VDD  
VSS  
L2  
CASE  
ferrite  
tbd  
don't stuff  
GND  
-SLEEP  
-ACTIVE -LANLED  
=
-ACTIVE  
Figure 13. eZ80L92 Module Schematic Diagram, #5 of 9—E-NET Module  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
28  
V3.3  
C9  
100nF  
0603  
R3  
2k2  
0603  
U4  
-RESET  
2
-RESET  
RESET  
open-drain  
C10  
10nF  
0603  
MAX6328UR29  
SOT-23-L3  
alternative:  
Maxim  
MAX6802UR29D3  
IR-transceiver  
V3.3  
R5  
68R  
C11  
330nF  
U5  
R6  
2R7, 0.25W  
1206  
(MMA 020 4)  
IRDA_TXD  
IRDA_RXD  
5
1
2
4
3
6
IRDA_TXD  
IRDA_RXD  
VCC  
LEDA  
TXD  
SD  
IRDA_TXD  
IRDA_SD  
IRDA_SD  
V3.3  
IRDA_SD  
IRDA_RXD  
RXD  
GND  
VDD  
VSS  
ZHX1810  
GND  
Figure 14. eZ80L92 Module Schematic Diagram, #6 of 9—IrDA Reset  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
29  
A[0..23]  
D[0..7]  
A[0..23]  
D[0..7]  
connector 1  
connector 2  
JP1  
JP2  
A6  
A0  
A3  
V3.3_EXT  
A7  
A9  
A14  
A16  
GND_EXT  
A1  
A12  
A20  
A17  
-DIS_FL  
V3.3_EXT  
A23  
-CS1  
D0  
PB7  
PB5  
PB6  
PB4  
PB2  
PB0  
PC7  
PC5  
PC3  
PC1  
PD7  
GND_EXT  
PD4  
PD2  
PD0  
1
3
5
7
2
4
6
1
3
2
4
A10  
GND_EXT  
PB3  
PB1  
GND_EXT  
5
7
9
6
8
A8  
A13  
A15  
A18  
A19  
A2  
A11  
A4  
-CS[0..3]  
R7  
4k7  
R8  
-CS[0..3]  
8
4k7  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
PC6  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
PC4  
PC2  
PC0  
PD6  
PD5  
PD3  
PD1  
TDO  
IICSDA  
IICSCL  
IICSDA  
IICSCL  
IICSDA  
IICSCL  
R9  
A5  
CLK_OUT  
-DIS_FL  
EZ80CLK  
CLK_OUT  
-DIS_FL  
DIS_ETH  
33place near eZ80  
output (PHI)  
A21  
A22  
-CS0  
-CS2  
D1  
D3  
D5  
D7  
-MREQ  
TDI  
TRIGOUT  
TMS  
GND_EXT  
TCK  
-DIS_IRDA  
-FLASHWE  
RTC_VDD  
RTC_VDD  
IICSCL  
IICSDA  
-FLASHWE  
-CS3  
-RESET  
V3.3_EXT  
-HALT_SLP  
V3.3_EXT  
EZ80CLK  
-DIS_IRDA  
-FLASHWE  
RTC_VDD  
-DIS_ETH  
PB[0..7]  
D2  
D4  
GND_EXT  
D6  
-IOREQ  
-RD  
GND_EXT  
-DIS_IRDA  
-WAIT  
GND_EXT  
-NMI  
GND_EXT  
-WR  
-INSTRD  
-BUSREQ  
PB[0..7]  
PC[0..7]  
PD[0..7]  
-BUSACK  
R36  
10K  
HEADER 25X2  
IDC50  
HEADER 25X2  
IDC50  
PC[0..7]  
PD[0..7]  
-RESET  
-RESET  
-RD  
-WR  
-RD  
-WR  
-IOREQ  
-MREQ  
-INSTRD  
R10  
R33  
-IOREQ  
-MREQ  
-INSTRD  
2k2  
0603  
2k2  
0603  
-WAIT  
-HALT_SLP  
-WAIT  
-WAIT  
-HALT_SLP  
R11  
10k  
R12  
10k  
-BUSREQ  
-BUSACK  
-BUSREQ  
-BUSREQ  
-BUSACK  
-NMI  
JTAG1  
(JTAG0 =) TDO  
=
TDI  
-NMI  
JTAG2  
JTAG3  
JTAG4  
=
=
=
TRIGOUT  
TCK  
TMS  
JTAG[1..4]  
TDO  
JTAG[1..4]  
TDO  
V3.3  
V3.3_EXT  
GND_EXT  
V3.3_EXT  
GND_EXT  
R13  
4k7  
GND  
Figure 15. eZ80L92 Module Schematic Diagram, #7 of 9—Headers  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
30  
V3.3  
common power plane  
V3.3  
GND  
V3.3  
V3.3  
GND  
C1  
47uF  
TAJC  
C2  
47uF  
TAJC  
C3  
C4  
C5  
C6  
100nF  
1nF  
100nF  
1nF  
GND  
GND  
common ground plane  
no power supply on board!  
Input: VDD(=V3.3) = 3.3V 5ꢀ  
Power: Pmax = 1.6W  
Ptyp = 0.4W  
Current: Imax = 200mA (IrDA not in use)  
Imax = 460mA (IrDA in use)  
Ityp = 100mA  
PCB1  
E-NET Module Rev.B  
98Cxxxx-xxx  
Figure 16. eZ80L92 Module Schematic Diagram, #8 of 9—Power Supply  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
31  
=
D[0..7]  
D[0..7]  
SD[0..7]  
SA[0..3]  
SD[0..7]  
SD[0..7]  
D[0..7]  
A[0..23]  
A[0..23]  
SA[0..3]  
SA[0..3]  
only A0,A1,A2,A3  
are used here  
A[0..23]  
=
=
=
=
A0  
A1  
A2  
A3  
SA0  
SA1  
SA2  
SA3  
-ETHRD  
-ETHRD  
PD[0..7]  
-ETHWR  
-ETHWR  
PD3 and PD5  
not used here  
PD[0..7]  
VDD  
=
PD4  
ETHIRQ  
ETHIRQ  
-RESET  
-WAIT  
-RESET  
-WAIT  
R14  
R15  
0R  
0R  
PD7  
PD6  
-SLEEP  
U6D  
-SLEEP  
-RD  
12  
13  
-ETHRD  
-ACTIVE  
11  
-ACTIVE  
-DIS_FL  
-DIS_IRDA  
-DIS_FL  
-DIS_IRDA  
don’t stuff  
74LCX32  
TSSOP14  
=
-RD  
-CS3  
-WR  
-CSETH  
-RD  
R35  
0
-WAIT  
-WR  
-WR  
IOCHRDY  
U6A  
1
2
-ETHWR  
3
-CS[0..3]  
-CS1 and-CS2  
not used  
here  
-CS[0..3]  
74LCX32  
TSSOP14  
=
=
PD0  
PD1  
IRDA_TXD  
IRDA_RXD  
IRDA_TXD  
IRDA_RXD  
VDD  
IRDA_SD  
IRDA_SD  
R30  
10k  
0603  
U2B  
U6B  
DIS_FL  
-DIS_FL  
3
4
4
5
-CSFLASH  
6
=
-CS0  
-RESET  
-RESFLASH  
-CSFLASH  
-RESFLASH  
-CSFLASH  
74LVC04/SO  
U2C  
74LCX32  
TSSOP14  
R17  
10k  
0603  
U6C  
DIS_IRDA  
PD2 IR_SD  
-DIS_IRDA  
5
6
9
IRDA_SD  
8
=
10  
74LVC04/SO  
74LCX32  
TSSOP14  
V3.3  
VDD  
VSS  
GND  
Figure 17. eZ80L92 Module Schematic Diagram, #9 of 9—Control Logic  
PS017005-0903  
PRELIMINARY  
Schematic Diagrams  
eZ80L925048MOD  
eZ80L92 Module Product Specification  
32  
Customer Feedback Form  
The eZ80L92 Module Product Specification  
If you experience any problems while operating this product, or if you note any inaccuracies  
while reading this Product Specification, please copy and complete this form, then mail or fax it to  
ZiLOG (see Return Information, below). We also welcome your suggestions!  
Customer Information  
Name  
Country  
Phone  
Fax  
Company  
Address  
City/State/Zip  
Email  
Product Information  
Serial # or Board Fab #/Rev. #  
Software Version  
Document Number  
Host Computer Description/Type  
Return Information  
ZiLOG  
System Test/Customer Support  
532 Race Street  
San Jose, CA 95126  
Phone: (408) 558-8500  
Fax: (408) 558-8536  
ZiLOG Customer Support  
Problem Description or Suggestion  
Provide a complete description of the problem or your suggestion. If you are reporting a specific  
problem, include all steps leading up to the occurrence of the problem. Attach additional pages  
as necessary.  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
_____________________________________________________________________________________________  
PS017005-0903  
P R E L I M I N A R Y  
Customer Feedback Form  
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