5P49V5901A702NLGI,PDF,5P49V5901A702NLGI PDF资料,Datasheet,下载5P49V5901A702NLGI技术资料

Programmable Clock Generator

IDT5P49V5901A

DATASHEET

Description

Features

The IDT5P49V5901A is a programmable clock generator

intended for high performance consumer, networking,

industrial, computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to four independent output frequencies

• High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

2

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

Programmable (OTP) memory or changed using I C

interface. This is IDTs fifth generation of programmable clock

®

technology (VersaClock 5).

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

• Four fractional output dividers (FODs)

• Independent Spread Spectrum capability on each output

pair

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

2

• I C serial programming interface

• One reference LVCMOS output clock

• Four universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

2

The device may be configured to use one of two I C

• I/O Standards:

addresses to allow multiple devices to be used in a system.

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os - LVPECL, LVDS and HCSL

Pin Assignment

• Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

• Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

24 23 22 21 20 19

1

2

V_DDO

2

18

17

16

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

CLKIN

CLKINB

XOUT

OUT2

• Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

3

4

OUT2B

EPAD

V_DDO3

XIN/REF

V_DDA

15

14

• Redundant clock inputs with manual switchover

• Programmable loop bandwidth

• Programmable output to output skew

• Programmable slew rate control

• Programmable crystal load capacitance

• Individual output enable/disable

• Power-down mode

5

6

OUT3

13

OUT3B

CLKSEL

8

9

10 11 12

7

• 1.8V, 2.5V or 3.3V core V

, V

DDA

DDD

24-pin VFQFPN

• Available in 24-pin VFQFPN 4mm x 4mm package

• -40° to +85°C industrial temperature operation

IDT5P49V5901A REVISION D 10/21/14

1

IDT5P49V5901A DATASHEET

Functional Block Diagram

V_DDO

OUT0_SEL_I2CB

_DDO1

0

XIN/REF

XOUT

V

OUT1

FOD1

FOD2

FOD3

FOD4

OUT1B

CLKIN

V_DDO2

CLKINB

OUT2

OUT2B

CLKSEL

SD/OE

PLL

V_DDO3

OUT3

OUT3B

SEL1/SDA

V_DDO4

OTP

and

Control Logic

SEL0/SCL

OUT4

OUT4B

V_DDA

V_DDD

Applications

• Ethernet switch/router

• PCI Express 1.0/2.0/3.0

• Broadcast video/audio timing

• Multi-function printer

• Processor and FPGA clocking

• Any-frequency clock conversion

• MSAN/DSLAM/PON

• Fiber Channel, SAN

• Telecom line cards

• 1 GbE and 10 GbE

PROGRAMMABLE CLOCK GENERATOR

2

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 1:Pin Descriptions

Number

Name

Type

Description

Internal

Pull-down

1

CLKIN

Input

Differential clock input. Weak 100kohms internal pull-down.

Internal

Pull-down

2

3

CLKINB

XOUT

Input

Complementary differential clock input. Weak 100kohms internal pull-down.

Crystal Oscillator interface output.

Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that

the input voltage is 1.2V max.Refer to the section “Overdriving the XIN/REF

Interface”.

4

5

XIN/REF

V_DDA

Input

Analog functions power supply pin.Connect to 1.8V to 3.3V. V_DDAand V_DDDshould

have the same voltage applied.

Power

Input clock select. Selects the active input reference source in manual switchover

mode.

Internal

Pull-down

6

CLKSEL

Input

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as shown in Table 4.

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE

pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be

either active HIGH or LOW only when pin is configured as OE (Default is active

LOW.) Weak internal pull down resistor. When configured as SD, device is shut

down, differential outputs are driven high/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs are disabled, the

outputs can be selected to be tri-stated or driven high/low, depending on the

programming bits as shown in the SD/OE Pin Function Truth table.

Internal

Pull-down

7

SD/OE

Internal

Configuration select pin, or I²C SDA input as selected by OUT0_SEL_I2CB. Weak

8

9

SEL1/SDA

SEL0/SCL

Input

Pull-down internal pull down resistor.

Internal

Configuration select pin, or I²C SCL input as selected by OUT0_SEL_I2CB. Weak

Pull-down internal pull down resistor.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT4/OUT4B.

10

11

12

V_DDO

4

Power

Output

OUT4

Output Clock 4. Please refer to the Output Drivers section for more details.

Complementary Output Clock 4. Please refer to the Output Drivers section for more

details.

OUT4B

Complementary Output Clock 3. Please refer to the Output Drivers section for more

details.

13

14

15

OUT3B

OUT3

Output

Power

Output Clock 3. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT3/OUT3B.

V_DDO

3

Complementary Output Clock 2. Please refer to the Output Drivers section for more

details.

16

17

18

OUT2B

OUT2

Output

Power

Output Clock 2. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT2/OUT2B.

V_DDO

2

Complementary Output Clock 1. Please refer to the Output Drivers section for more

details.

19

20

21

OUT1B

OUT1

Output

Power

Output Clock 1. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT1/OUT1B.

V_DDO

1

REVISION D 10/21/14

3

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Number

Name

Type

Description

Digital functions power supply pin. Connect to 1.8 to 3.3V. V_DDAand V_DDDshould

have the same voltage applied.

22

V_DDD

Power

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage

levels for OUT0.

23

V_DDO0

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9.

If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be

configured as hardware select pins, SEL1 and SEL0. If a weak pull down (10Kohms)

is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA

and SCL pins of an I²C interface. After power up, the pin acts as a LVCMOS

reference output.

Input/

Output

Internal

Pull-down

24

OUT0_SEL_I2CB

GND

ePAD

GND

Connect to ground pad.

PROGRAMMABLE CLOCK GENERATOR

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REVISION D 10/21/14

IDT5P49V5901A DATASHEET

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

PLL Features and Descriptions

Spread Spectrum

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

To help reduce electromagnetic interference (EMI), the

IDT5P49V5901A supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The IDT5P49V5901A implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

2

CLKSEL Polarity can be changed by I C programming as

shown in the table below.

PRIMSRC

CLKSEL

Source

XIN/REF

0

1

0

1

0

1

CLKIN, CLKINB

XIN/REF

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

PRIMSRC is bit 1 of Register 0x13.

Input Reference

Loop

Frequency–Fref BandwidthMin Bandwidth Max

(MHz)

1

(kHz)

40

(kHz)

126

350

300

1000

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

2

OUT0_SEL_I2CB SEL1 SEL0

@ POR

I C

REG0:7 Config

Access

1

0

1

X

0

1

0

1

X

No

Yes

0

1

0

1

2

3

I2C

defaults

0

X

Yes

0

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300nS

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

REVISION D 10/21/14

5

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Equation 1 and the table of XTAL[5:0] tuning capacitor

characteristics show that the parallel tuning capacitance can

be set between 4.5pF to 12.5pF with a resolution of 0.25 pF.

Consider two examples.

Reference Clock Input Pins and

Selection

The IDT5P49V5901A supports up to two clock inputs. One of

the clock inputs (XIN/ REF) can be driven by either an external

crystal or a reference clock. The second clock input (CLKIN,

CLKINB) can only be driven from an external reference clock.

The CLKSEL pin selects the input clock between either

XTAL/REF or (CLKIN, CLKINB).

For a crystal CL= 8pF, where CL is the parallel capacity

specified by the crystal vendor that sets the crystal frequency

to the nominal value. Under the assumptions that the stray

capacity between the crystal leads on the circuit board is zero

and that no external tuning caps are placed on the crystal

leads, then the internal parallel tuning capacity is equal to the

load capacity presented to the crystal by the VersaClock.

Equation 1 allows for the direct calculation that XTAL[5:0] = 14

(dec).

Either clock input can be set as the primary clock. The primary

clock designation is to establish which is the main reference

clock to the PLL. The non-primary clock is designated as the

secondary clock in case the primary clock goes absent and a

backup is needed. The PRIMSRC bit determines which clock

input will be selected as primary clock. When PRIMSRC bit is

“0”, XIN/REF is selected as the primary clock, and when “1”,

(CLKIN, CLKINB) as the primary clock.

In the case of a CL = 18pF crystal, the maximum internal

parallel tuning cap of 12.5pF will be insufficient. Two external

tuning capacitors must be added to the circuit board, one on

each of XIN and XOUT. For maximum turning range, set the

value of the two external tuning caps so that XTAL[5:0] is set

in the middle of its range, 8pF/2 = 4pF and XTAL[5:0] = 32

(dec). Using Equation 1, the internal tuning capacitor is set for

4.5pF + 4pF = 8.5pF. The remaining tuning capacity is 18pF -

8.5pF = 9.5pF. Each external tuning capacitor is then 2*9.5pF

= 19pF.

The two external reference clocks can be manually selected

using the CLKSEL pin. The SM bits must be set to “0x” for

manual switchover which is detailed in Manual Switchover

Mode section.

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

The internal load capacitors are true parallel-plate capacitors

for ultra-linear performance. Parallel-plate capacitors were

chosen to reduce the frequency shift that occurs when

non-linear load capacitance interacts with load, bias, supply,

and temperature changes. External non-linear crystal load

capacitors should not be used for applications that are

sensitive to absolute frequency requirements.

When a crystal is connected across the XIN/REF and XOUT

pins it is important to set the internal tuning capacitor values

correctly to achieve the highest clock frequency accuracy.

There are two equal valued tuning capacitors, one for XIN and

one for XOUT and each capacitor provides a parallel path for

its associated pin to the internal ground of the device. The

values of these capacitors are composed of a fixed capacity

plus a variable capacity set with the XTAL[5:0] register

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to switch

between the primary and secondary clock sources. The

primary and secondary clock source setting is determined by

the PRIMSRC bit. During the switchover, no glitches will occur

at the output of the device, although there may be frequency

and phase drift, depending on the exact phase and frequency

relationship between the primary and secondary clocks.

2

through the I C interface. Adjustment of the crystal tuning

capacitors through firmware allows for maximum flexibility to

accommodate crystals from various manufacturers. The

range of tuning capacitor values available are in accordance

with the following table.

XTAL[5:0] Tuning Capacitor Characteristics

Parameter

Bits

Step (pF)

Min (pF)

Max (pF)

XTAL

6

0.5

0

16

The AC voltages on the XIN and XOUT pins are out of phase,

which allows the two XTAL[5:0] tuning capacitors to be

translated into a single equivalent parallel load capacitor

across XIN and XOUT by dividing the tuning capacity by two.

Adding the fixed parallel capacity and the effective parallel

tuning capacity set by XTAL results in the total parallel tuning

capacity provided by the VersaClock.

XTAL load cap = 4.5pF + (XTAL[5:0]/2) (Eq. 1)

PROGRAMMABLE CLOCK GENERATOR

6

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

OTP Interface

Table 5: SD/OE Pin Function Truth Table

The IDT5P49V5901A can also store its configuration in an

internal OTP. The contents of the device's internal

programming registers can be saved to the OTP by setting

burn_start (W114[3]) to high and can be loaded back to the

internal programming registers by setting

SH bit SP bit OSn bit OEn bit SD/OE

OUTn

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

0

1

0

1

x

0

1

x

0

1

Tri-state²

usr_rd_start(W114[0]) to high.

Output active

Output driven High Low

Output active

2

To initiate a save or restore using I C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the

1

0

1

x

0

1

0

Tri-state²

Output active

IDT5P49V5901A will not generate Acknowledge bits. The

IDT5P49V5901A will acknowledge the instructions after it has

1

0

1

x

0

1

0

Tri-state²

Output active

Output driven High Low

Output driven High Low ¹

2

completed execution of them. During that time, the I C bus

should be interpreted as busy by all other users of the bus.

1

x

1

On power-up of the IDT5P49V5901A, an automatic restore is

performed to load the OTP contents into the internal

Note 1 : Global Shutdown

programming registers. The IDT5P49V5901A will be ready to

accept a programming instruction once it acknowledges its

7-bit I C address.

Note 2 : Tri-state regardless of OEn bits

2

Output Divides

2

Each output divide block has a synchronizing POR pulse to

provide startup alignment between outputs divides. This

allows alignment of outputs for low skew performance. This

low skew would also be realized between outputs that are

both integer divides from the VCO frequency. This phase

alignment works when using configuration with SEL1, SEL0.

Availability of Primary and Secondary I C addresses to allow

2

programming for multiple devices in a system. The I C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

2

Programming Guide provides detailed I C programming

guidelines and register map.

2

For I C programming, I C reset is required.

SD/OE Pin Function

An output divide bypass mode (divide by 1) will also be

provided, to allow multiple buffered reference outputs.

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

Each of the four output divides are comprised of a 12 bit

integer counter, and a 24 bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate a

clock frequency accurate to 50 ppb.

Each of the output divides also have structures capable of

independently generating spread spectrum modulation on the

frequency output.

SP

OUTn

SD/OE Input

The Output Divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

OEn

Global Shutdown

OSn

SH

For all outputs, there is a bypass mode, to allow the output to

behave as a buffered copy of the input.

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

REVISION D 10/21/14

7

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Output Skew

Device Start-up & Reset Behavior

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100 MHz output

and a 2800 MHz VCO, you can select how many 11.161pS

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

The IDT5P49V5901A has an internal power-up reset (POR)

circuit. The POR circuit will remain active for a maximum of

10ms after device power-up.

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The device will load internal registers according to Table 3.

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

dependent on the VCO period and the output period.

Output Drivers

Power Up Ramp Sequence

The OUT1 to OUT4 clock outputs are provided with

register-controlled output drivers. By selecting the output drive

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

VDDA and VDDD must ramp up together. VDDO0~4 must

ramp up before, or concurrently with, VDDA and VDDD. All

power supply pins must be connected to a power rail even if

the output is unused. All power supplies must ramp in a linear

fashion and ramp monotonically.

The operating voltage ranges of each output is determined by

its independent output power pin (V

) and thus each can

DDO

have different output voltage levels. Output voltage levels of

2.5V or 3.3V are supported for differential HCSL, LVPECL

operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS

and differential LVDS operation.

VDDO0~4

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

VDDA

VDDD

LVCMOS Operation

When a given output is configured to provide LVCMOS levels,

then both the OUTx and OUTxB outputs will toggle at the

selected output frequency. All the previously described

configuration and control apply equally to both outputs.

Frequency, phase alignment, voltage levels and enable /

disable status apply to both the OUTx and OUTxB pins. The

OUTx and OUTxB outputs can be selected to be

phase-aligned with each other or inverted relative to one

another by register programming bits. Selection of

phase-alignment may have negative effects on the phase

noise performance of any part of the device due to increased

simultaneous switching noise within the device.

Device Hardware Configuration

The IDT5P49V5901A supports an internal One-Time

Programmable (OTP) memory that can be pre-programmed

at the factory with up to 4 complete device configuration.

These configurations can be over-written using the serial

interface once reset is complete. Any configuration written via

the programming interface needs to be re-written after any

power cycle or reset. Please contact IDT if a specific

factory-programmed configuration is desired.

PROGRAMMABLE CLOCK GENERATOR

8

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

2

I C Mode Operation

2

The device acts as a slave device on the I C bus using one of

2

the two I C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

2

For full electrical I C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

A

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data 1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar= none acknowledge

P = stop

I²C Slave Read and Write Cycle Sequencing

REVISION D 10/21/14

9

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 6:I²C Bus DC Characteristics

Symbol

VIH

Parameter

Conditions

Min

0.7xVDDD

Typ

Max

Unit

V

Input HIGH Level

Input LOW Level

VIL

0.3xVDDD

VHYS

IIN

VOL

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

0.05xVDDD

-1

V

µA

V

30

0.4

IOL = 3 mA

Table 7:I²C Bus AC Characteristics

Symbol

FSCLK

tBUF

Parameter

Serial Clock Frequency (SCL)

Bus free time between STOP and START

Min

10

Typ

Max

400

Unit

kHz

µs

1.3

0.6

0.1

0

tSU:START Setup Time, START

tHD:START Hold Time, START

tSU:DATA Setup Time, data input (SDA)

tHD:DATA Hold Time, data input (SDA) 1

µs

tOVD

CB

tR

tF

tHIGH

tLOW

Output data valid from clock

0.9

400

300

µs

pF

ns

µs

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

20 + 0.1xCB

0.6

1.3

0.6

LOW Time, clock (SCL)

µs

tSU:STOP Setup Time, STOP

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH(MIN) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

PROGRAMMABLE CLOCK GENERATOR

10

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 8:Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the IDT5P49V5901A. These ratings, which are standard values for

IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated

in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect

product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Item

Rating

Supply Voltage, V_DDA,V_DDD,V_DDO

3.465V

Inputs

XIN/REF

CLKIN, CLKINB

Other inputs

0V to 1.2V voltage swing

0V to 1.2V voltage swing single-ended

-0.5V to V_DDD

Outputs, V_DDO(LVCMOS)

Outputs, I_O(SDA)

-0.5V to V_DDO+ 0.5V

10mA

Package Thermal Impedance, _JA

Package Thermal Impedance, _JC

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

42C/W (0 mps)

41.8C/W (0 mps)

-65C to 150C

2000V

125°C

Table 9:Recommended Operation Conditions

Symbol

Parameter

Min

1.71

Typ

1.8

2.5

3.3

Max

1.89

Unit

V

Power supply voltage for supporting 1.8V outputs

Power supply voltage for supporting 2.5V outputs

Power supply voltage for supporting 3.3V outputs

Power supply voltage for core logic functions

V

DDOX

2.375

3.135

1.71

2.625

3.465

V

DDD

DDA

Analog power supply voltage. Use filtered analog power

supply.

V

1.71

V

Operating temperature, ambient

T

-40

+85

15

°C

pF

A

Maximum load capacitance (3.3V LVCMOS only)

External reference crystal

C

LOAD_OUT

F

8

5

40

MHz

IN

External reference clock CLKIN, CLKINB

350

5

Power up time for all V_DDs to reach minimum specified

voltage (power ramps must be monotonic)

t

0.05

ms

PU

Note: V_DDO1, V_DDO2, V_DDO3, and V_DDO4 must be powered on either before or simultaneously with V_DDD, V_DDAand V_DDO0.

REVISION D 10/21/14

11

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 10:Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down

Resistance ^(T= +25 °C)

A

Symbol

Parameter

Min

Typ

Max

7

Unit

Input Capacitance (CLKIN, CLKINB, CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL)

CIN

3

pF

CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL, CLKIN, CLKINB,

OUT0_SEL_I2CB

Pull-down Resistor

ROUT

100

0

300

kΩ

LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)

Programmable capacitance at XIN/REF and XOUT (X1 in parallel

with X2)

17

Ω

XIN/REF, XOUT

8

pF

Table 11:Crystal Characteristics

Parameter

Mode of Oscillation

Test Conditions

Minimum

Typical Maximum

Fundamental

Units

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

8

25

10

40

100

7

MHz

Ω

pF

Load Capacitance (CL) @ <=25 MHz

Load Capacitance (CL) >25M to 40M

Maximum Crystal Drive Level

6

8

12

8

100

pF

µW

Table 12:DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

100 MHz on all outputs, 25 MHz

REFCLK

Iddcore³

Core Supply Current

30

42

37

18

17

16

29

28

16

14

12

36

27

16

10

34

47

42

21

20

19

33

18

16

14

42

32

19

14

mA

LVPECL, 350 MHz, 3.3V VDDOx

LVPECL, 350 MHz, 2.5V VDDOx

LVDS, 350 MHz, 3.3V VDDOx

LVDS, 350 MHz, 2.5V VDDOx

LVDS, 350 MHz, 1.8V VDDOx

HCSL, 250 MHz, 3.3V VDDOx, 2 pF load

HCSL, 250 MHz, 2.5V VDDOx, 2 pF load

Iddox

Output Buffer Supply Current

1,2

LVCMOS, 50 MHz, 3.3V, VDDOx

1,2

LVCMOS, 50 MHz, 2.5V, VDDOx

1,2

LVCMOS, 50 MHz, 1.8V, VDDOx

LVCMOS, 200 MHz, 3.3V VDDOx¹

LVCMOS, 200 MHz, 2.5V VDDOx^1,2

LVCMOS, 200 MHz, 1.8V VDDOx^1,2

SD asserted, I2C Programming

Iddpd

Power Down Current

1. Single CMOS driver active.

2. Measured into a 5” 50 Ohm trace with 2 pF load.

3. Iddcore = IddA+ IddD, no loads.

PROGRAMMABLE CLOCK GENERATOR

12

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 13:Electrical Characteristics – Differential Clock Input Parameters ^1,2(Supply

Voltage V

, V

, V 0 = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C)

DDO

DDA

DDD

Symbol

VIH

Parameter

Test Conditions

Min

0.55

Typ

Max

Unit

Input High Voltage - CLKIN, CLKINBSingle-ended input

Input Low Voltage - CLKIN, CLKINB Single-ended input

Input Amplitude - CLKIN, CLKINB Peak to Peak value, single-ended

Input Slew Rate - CLKIN, CLKINB Measured differentially

1.7

V

VIL

GND - 0.3

200

0.4

1200

8

V

mV

V/ns

µA

VSWING

dv/dt

IIL

0.4

Input Leakage Low Current

Input Leakage High Current

Input Duty Cycle

VIN = GND

-5

5

IIH

VIN = 1.7V

20

µA

dTIN

Measurement from differential waveform

45

55

%

1. Guaranteed by design and characterization, not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

1

Table 14:DC Electrical Characteristics for 3.3V LVCMOS (V

= 3.3V±5%, TA = -40°C to +85°C)

DDO

Min

2.4

Symbol

Parameter

Test Conditions

Typ

Max

VDDO

0.4

Unit

V

IOH = -15mA

VOH

Output HIGH Voltage

IOL = 15mA

VOL

Output LOW Voltage

V

Tri-state outputs, VDDO = 3.465V

IOZDD

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

5

µA

Tri-state outputs, VDDO = 3.465V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

30

VIH

Input HIGH Voltage

0.7xVDDO

VDDD + 0.3

V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

VIL

VIH

VIL

VIH

VIL

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

GND - 0.3

2

0.8

V

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

VDDO0 + 0.3

GND - 0.3

0.8

0.4

1.2

0.4

Single-ended input - XIN/REF

GND - 0.3

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

TR/TF

Input Rise/Fall Time

300

nS

1. See “Recommended Operating Conditions” table.

Table 15:DC Electrical Characteristics for 2.5V LVCMOS (V

= 2.5V±5%, TA = -40°C to +85°C)

DDO

Symbol

VOH

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -12mA

Output HIGH Voltage

0.7xVDDO

IOL = 12mA

VOL

Output LOW Voltage

0.4

5

V

Tri-state outputs, VDDO = 2.625V

IOZDD

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

µA

Tri-state outputs, VDDO = 2.625V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

30

VIH

Input HIGH Voltage

1.7

VDDD + 0.3

V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

VIL

VIH

VIL

VIH

VIL

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

GND - 0.3

1.7

0.8

V

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

VDDO0 + 0.3

GND - 0.3

0.8

0.4

1.2

0.4

Single-ended input - XIN/REF

GND - 0.3

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

TR/TF

Input Rise/Fall Time

300

nS

REVISION D 10/21/14

13

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 16:DC Electrical Characteristics for 1.8V LVCMOS (V

= 1.8V±5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -8mA

VOH

Output HIGH Voltage

0.7 xVDDO

VDDO

IOL = 8mA

VOL

Output LOW Voltage

0.25 x VDDO

V

Tri-state outputs, VDDO = 3.465V

IOZDD

Output Leakage Current (OUT1~4)

Output Leakage Current (OUT0)

5

µA

Tri-state outputs, VDDO = 3.465V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

30

VIH

Input HIGH Voltage

0.65 * VDDD

VDDD + 0.3

V

Single-ended inputs - CLKSEL, SD/OE,

SEL1/SDA, SEL0/SCL

VIL

VIH

VIL

VIH

VIL

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input HIGH Voltage

Input LOW Voltage

GND - 0.3

0.65 * VDDD

GND - 0.3

0.8

0.25 * VDDD

V

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

VDDD0 + 0.3

0.4

1.2

0.4

Single-ended input - XIN/REF

CLKSEL, SD/OE, SEL1/SDA,

SEL0/SCL

GND - 0.3

TR/TF

Input Rise/Fall Time

300

nS

Table 17:DC Electrical Characteristics for LVDS^(V

= 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in V_OTbetween Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

V

(+)

(-)

OT

V

-247

OT

V

OT

V

1.125

1.25

1.375

50

OS

Change in V_OSbetween Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DDO

V

mV

mA

OS

I

9

6

24

OS

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

I

12

OSD

Table 18:DC Electrical Characteristics for LVDS (V

= 1.8V+5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in V_OTbetween Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

V

(+)

(-)

OT

V

-247

OT

V

OT

V

0.8

0.875

0.95

50

OS

Change in V_OSbetween Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DDO

V

mV

mA

OS

I

9

6

24

OS

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

I

12

OSD

Table 19:DC Electrical Characteristics for LVPECL (V

= 3.3V+5% or 2.5V+5%, TA = -40°C to

DDO

+85°C)

Symbol

Parameter

Min

Typ

Max

Unit

V

Output Voltage HIGH, terminated through 50 tied to V_DD- 2 V

Output Voltage LOW, terminated through 50 tied to V_DD- 2 V

Peak-to-Peak Output Voltage Swing

V

- 1.19

- 1.94

V

- 0.69

DDO

OH

DDO

V

- 1.4

DDO

V

OL

V

0.55

0.993

V

SWING

PROGRAMMABLE CLOCK GENERATOR

14

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 20:Electrical Characteristics – DIF 0.7V Low Power HCSL Differential Outputs

(V

= 3.3V±5%, 2.5V±5%, TA = -40°C to +85°C)

DDO

Symbol Parameter

Conditions

Min

Typ

Max

4

Units

V/ns

%

Notes

1,2,3

dV/dt

Slew Rate

Scope averaging on

1

Scope averaging on

20

Δ

Statistical measurement on single-ended

signal using oscilloscope math function

(Scope averaging ON)

VHIGH

VLOW

VMAX

VMIN

Voltage High

660

850

150

mV

1,6,7

1,6

1

Voltage Low

-150

Maximum Voltage

Minimum Voltage

1150

Measurement on single-ended signal using

absolute value (Scope averaging off)

-300

300

250

1

Scope averaging off

VSWING Voltage Swing

1,2,6

1,4,6

1,5

VCROSS Crossing Voltage Value

550

140

VCROSS

Crossing Voltage variation

Δ

1. Guaranteed by design and characterization. Not 100% tested in production

2. Measured from differential waveform.

3. Slew rate is measured through the V_SWINGvoltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4. V_CROSSis defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge

(i.e. Clock rising and Clock# falling).

5. The total variation of all V_CROSSmeasurements in any particular system. Note that this is a subset of V_CROSSmin/max (V_CROSSabsolute)

allowed. The intent is to limit V_CROSSinduced modulation by setting V_CROSSto be smaller than V_CROSSabsolute.

6. Measured from single-ended waveform.

7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max.

REVISION D 10/21/14

15

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 21:AC Timing Electrical Characteristics

(V_DDO= 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)

(Spread Spectrum Generation = OFF)

Symbol

Min.

Typ.

Max.

40

Units

MHz

Parameter

Test Conditions

1

Input frequency limit (XIN)

Input frequency limit (REF)

Input frequency limit (CLKIN, CLKINB)

fIN ¹

Input Frequency

200

350

200

Single ended clock output limit (LVCMOS)

Differential cock output limit (LVPECL/

LVDS/HCSL)

fOUT

Output Frequency

MHz

1

350

fVCO

fPFD

fBW

t2

VCO Frequency

PFD Frequency

Loop Bandwidth

Input Duty Cycle

2600

2800

3000

150

0.9

MHz

%

VCO operating frequency range

PFD operating frequency range

Input frequency = 25MHz

1 ¹

0.06

45

50

55

Duty Cycle

All differential outputs except Reference

output

45

40

30

55

60

70

%

Measured at VDD/2, all outputs except

Reference output 2.5V and 3.3V

Measured at VDD/2, all outputs except

Reference output 1.8V

50

t3 ⁵

Output Duty Cycle

Measured at VDD/2, Reference output

(150.1MHz - 200MHz) with 50% input

Measured at VDD/2, Reference output(s)

(120.1MHz - 200MHz)

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Rise Times

2.6

2.4

2.3

2.2

1.7

1.5

1.4

1.3

2.6

2.4

2.3

2.2

300

400

4.0

3.8

1.5

1.3

1.2

1.0

0.8

0.7

0.6

1.5

1.3

1.2

1.0

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDD=3.3V

3.7

3.6

2.7

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDD=2.5V

2.5

t4 ²

V/ns

2.45

2.39

4.0

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDD=1.8V

3.8

3.75

3.67

LVDS, 20% to 80%

LVDS, 80% to 20%

LVPECL, 20% to 80%

LVPECL, 80% to 20%

Fall Times

t5

ps

Rise Times

Fall Times

PROGRAMMABLE CLOCK GENERATOR

16

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

differential outputs (1.8V to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

46

ps

OUT2=125MHz

OUT3=156.25MHz

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

LVCMOS outputs (1.8 to 3.3V nominal

output voltage)

OUT0=25MHz

OUT1=100MHz

74

OUT2=125MHz

OUT3=156.25MHz

t6

Clock Jitter

RMS Phase Jitter (12kHz to 5MHz

integration range) reference clock (OUT0),

25 MHz LVCMOS outputs (1.8 to 3.3V

nominal output voltage).

OUT0=25MHz

0.5

OUT1=100MHz

OUT2=125MHz

OUT3=156.25MHz

RMS Phase Jitter (12kHz to 20MHz

integration range) differential output, VDDO

= 3.465V, 25MHz crystal, 156.25MHz

output frequency

OUT0=25MHz

OUT1=100MHz

0.75

75

1.5

ps

OUT2=125MHz

OUT3=156.25MHz

Skew between the same frequencies, with

outputs using the same driver format and

phase delay set to 0 ns.

t7

Output Skew

t8 ³

t9 ⁴

Lock Time

PLL lock time from power-up

10

3

20

4

ms

PLL lock time from shutdown mode

1. Practical lower frequency is determined by loop filter settings.

2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.

3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.

4. Actual PLL lock time depends on the loop configuration.

5. Duty Cycle is only guaranteed at max slew rate settings.

REVISION D 10/21/14

17

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 22:PCI Express Jitter Specifications (V

= 3.3V+5% or 2.5V+5%, T = -40°C to +85°C)

DDO

A

Symbol

Parameter

Conditions

Min Typ Max PCIe Industry Units Notes

Specification

t_J

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

30

86

ps

1,4

Phase Jitter

Peak-to-Peak

(PCIe Gen1)

t_{REFCLK_HF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS High Band: 1.5MHz - Nyquist (clock

frequency/2)

2.56

3.10

ps

2,4

t_{REFCLK_LF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS

0.27

0.8

3.0

1.0

ps

2,4

3,4

Low Band: 10kHz - 1.5MHz

t_{REFCLK_RMS}

(PCIe Gen3)

ƒ = 100MHz, 25MHz Crystal Input

Phase Jitter RMS

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test

socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these

conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results

for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS}(Low

Band).

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010

specification, and is subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Table 23:Jitter Specifications ^1,2,3

(VDDx = 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

Parameter

Symbol

J_GbE

Test Condition

Crystal in = 25 MHz, All CLKn at 125 MHz⁵

CLKIN = 19.44 MHz, All CLKn at 155.52 MHz⁵

Total Jitter⁶

RMS Jitter⁶, 10 kHz to 1.5MHz

RMS Jitter⁶, 1.5MHz to 50MHz

RMS Jitter⁶

Min

Typ

0.79

0.32

0.69

9.1

Max

0.95

0.5

Unit

ps

GbE Random Jitter (12 kHz–20 MHz)⁴

GbE Random Jitter (1.875–20 MHz)

OC-12 Random Jitter (12 kHz–5 MHz)

PCI Express 1.1 Common Clocked

-

R_JGbE

J_OC12

ps

0.95

12

ps

0.1

0.3

ps

PCI Express 2.1 Common Clocked

PCI Express 3.0 Common Clocked

0.9

1.1

ps

0.2

0.4

ps

Notes:

¹All measurements w ith Spread Spectrum Off.

²For best jitter performance, keep the single ended clock input slew rates at more than 1.0 V/ns and the differential clock input slew rates more than 0.3 V/ns.

³All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase

due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact

IDT for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter.

⁴DJ for PCI and GbEis < 5 ps pp.

⁵Output FOD in Integer mode.

⁶All output clocks 100 MHz HCSL format. Jitter is from the PCIEjitter filter combination that produces the highest jitter. Jitter is measured w ith the Intel Clock Jitter Tool,

Ver. 1.6.6.

PROGRAMMABLE CLOCK GENERATOR

18

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 24:Spread Spectrum Generation Specifications

Symbol

Parameter

Output Frequency

Mod Frequency

Spread Value

Description

Min Typ Max

Unit

MHz

kHz

Output Frequency Range

Modulation Frequency

f

5

300

OUT

f

30 to 63

MOD

Amount of Spread Value (programmable) - Center Spread

Amount of Spread Value (programmable) - Down Spread

f

±0.25% to ±2.5%

-0.5% to -5%

%f

OUT

SPREAD

Test Circuits and Loads

V_DDOx

V_DDD

V_DDA

OUTx

CLK_OUT

0.1µF

C_L

GND

HCSL Differential Output Test Load

Zo=100ohm differential

33

2pF

33

50

HCSL Output

Test Circuits and Loads for Outputs

REVISION D 10/21/14

19

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Typical Phase Noise at 100MHz (3.3V, 25°C)

NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.

PROGRAMMABLE CLOCK GENERATOR

20

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

IDT5P49V5901A Application Schematic

The following figure shows an example of IDT5P49V5901A application schematic. Input and output terminations shown are intended as

examples only and may not represent the exact user configuration. In this example, the device is operated at V_DDD,V_DDA= 3.3V. The

decoupling capacitors should be located as close as possible to the power pin. A 12pF parallel resonant 8MHz to 40MHz crystal is used in this

example. Different crystal frequencies may be used. The C1 = C2 = 5pF are recommended for frequency accuracy. If different crystal types

are used, please consult IDT for recommendations. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency

accuracy.

As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power

supply isolation is required. IDT5P49V5901A provides separate power supplies to isolate any high switching noise from coupling into the

internal PLL.

In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB

as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The

other components can be on the opposite side of the PCB.

Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter

performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a

specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be

adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests

adding bulk capacitance in the local area of all devices.

The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables

in the datasheet to ensure the logic control inputs are properly set.

REVISION D 10/21/14

21

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

IDT5P49V5901A Reference Schematic

V D D O 4

V D D O 3

V D D O 2

V D D O 1

V D D O 0

1 0

1 5

1 8

2 1

2 3

E P A D

V D D A

V D D D

5

2 2

PROGRAMMABLE CLOCK GENERATOR

22

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Overdriving the XIN/REF Interface

LVCMOS Driver

The XIN/REF input can be overdriven by an LVCMOS driver

or by one side of a differential driver through an AC coupling

capacitor. The XOUT pin can be left floating. The amplitude of

the input signal should be between 500mV and 1.2V and the

slew rate should not be less than 0.2V/ns. Figure General

Diagram for LVCMOS Driver to XTAL Input Interface shows an

example of the interface diagram for a LVCMOS driver.

This configuration has three properties; the total output

impedance of Ro and Rs matches the 50 ohm transmission

line impedance, the Vrx voltage is generated at the CLKIN

inputs which maintains the LVCMOS driver voltage level

across the transmission line for best S/N and the R1-R2

voltage divider values ensure that the clock level at XIN is less

than the maximum value of 1.2V.

VDD

XOUT

C3

Ro

Rs

Zo = 50 Ohm

R1

V_XIN

XIN / REF

Ro + Rs

LVCMOS

=

50 ohms

0. 1 uF

R2

General Diagram for LVCMOS Driver to XTAL Input Interface

Table 25 Nominal Voltage Divider Values vs LVCMOS VDD for

XIN shows resistor values that ensure the maximum drive

level for the XIN/REF port is not exceeded for all combinations

of 5% tolerance on the driver VDD, the VersaClock VDDA and

5% resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the voltage divider attenuation

as long as the minimum drive level is maintained over all

tolerances. To assist this assessment, the total load on the

driver is included in the table.

Table 25: Nominal Voltage Divider Values vs LVCMOS VDD for XIN

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

V_XIN (peak) Ro+Rs+R1+R2

3.3

2.5

1.8

0.97

1.00

0.97

255

250

242

50.0

100

130

50.0

REVISION D 10/21/14

23

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

LVPECL Driver

Figure General Diagram for LVPECL Driver to XTAL Input

Interface shows an example of the interface diagram for a

+3.3V LVPECL driver. This is a standard LVPECL termination

with one side of the driver feeding the XIN/REF input. It is

recommended that all components in the schematics be

placed in the layout; though some components might not be

used, they can be utilized for debugging purposes. The

datasheet specifications are characterized and guaranteed by

using a quartz crystal as the input. If the driver is 2.5V

LVPECL, the only change necessary is to use the appropriate

value of R3.

XOUT

C1

Zo = 50 Ohm

XIN / REF

0. 1 uF

Zo = 50 Ohm

R1

50

R2

50

+3.3V LVPECL Dr iv er

R3

50

General Diagram for +3.3V LVPECL Driver to XTAL Input Interface

CLKIN Equivalent Schematic

Figure CLKIN Equivalent Schematic below shows the basis of

the requirements on VIH max, VIL min and the 1200 mV p-p

single ended Vswing maximum.

• The CLKIN and CLKINB Vih max spec comes from the

cathode voltage on the input ESD diodes D2 and D4, which

are referenced to the internal 1.2V supply. CLKIN or

CLKINB voltages greater than 1.2V + 0.5V =1.7V will be

clamped by these diodes. CLKIN and CLKINB input

voltages less than -0.3V will be clamped by diodes D1 and

D3.

• The 1.2V p-p maximum Vswing input requirement is

determined by the internally regulated 1.2V supply for the

actual clock receiver. This is the basis of the Vswing spec in

Table 13.

PROGRAMMABLE CLOCK GENERATOR

24

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

CLKIN Equivalent Schematic

Wiring the Differential Input to Accept Single-Ended Levels

Figure Recommended Schematic for Wiring a Differential

Input to Accept Single-ended Levels shows how a differential

input can be wired to accept single ended levels. This

configuration has three properties; the total output impedance

of Ro and Rs matches the 50 ohm transmission line

impedance, the Vrx voltage is generated at the CLKIN inputs

which maintains the LVCMOS driver voltage level across the

transmission line for best S/N and the R1-R2 voltage divider

values ensure that Vrx p-p at CLKIN is less than the maximum

value of 1.2V.

VDD

Ro

Rs

Zo = 50 Ohm

R1

Vrx

CLKIN

Ro + Rs = 50

LVCMOS

CLKINB

R2

VersaClock 5 Receiver

Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

REVISION D 10/21/14

25

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Table 26 Nominal Voltage Divider Values vs Driver VDD

shows resistor values that ensure the maximum drive level for

the CLKIN port is not exceeded for all combinations of 5%

tolerance on the driver VDD, the VersaClock Vddo_0 and 5%

resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the impedance of the R1-R2

divider. To assist this assessment, the total load on the driver

is included in the table.

Table 26: Nominal Voltage Divider Values vs Driver VDD

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

Vrx (peak) Ro+Rs+R1+R2

3.3

2.5

1.8

0.97

1.00

0.97

255

250

242

50.0

100

130

50.0

HCSL Differential Clock Input Interface

CLKIN/CLKINB will accept DC coupled HCSL signals.

Zo=50ohm

Q

CLKIN

Zo=50ohm

nQ

CLKINB

VersaClock 5 Receiver

CLKIN, CLKINB Input Driven by an HCSL Driver

3.3V Differential LVPECL Clock Input Interface

The logic levels of 3.3V LVPECL and LVDS can exceed VIH

max for the CLKIN/B pins. Therefore the LVPECL levels must

be AC coupled to the VersaClock differential input and the DC

bias restored with external voltage dividers. A single table of

bias resistor values is provided below for both for 3.3V

LVPECL and LVDS. Vbias can be VDDD, V or any other

available voltage at the VersaClock receiver that is most

conveniently accessible in layout.

DDOX

Vbias

Rpu1

Rpu2

C5

0.01µF

Zo=50ohm

CLKIN

C6

0.01µF

CLKINB

R9

50ohm

R10

50ohm

+3.3V LVPECL

Driver

VersaClock 5 Receiver

R13

4.7kohm

R15

4.7kohm

RTT

50ohm

CLKIN, CLKINB Input Driven by a 3.3V LVPECL Driver

PROGRAMMABLE CLOCK GENERATOR

26

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Vbias

Rpu1

Rpu2

C1

0.1µF

Zo=50ohm

CLKIN

C2

0.1µF

Rterm

100ohm

CLKINB

VersaClock 5 Receiver

LVDS Driver

R2

4.7kohm

R1

4.7kohm

CLKIN, CLKINB Input Driven by an LVDS Driver

Table 27: Bias Resistors for 3.3V LVPECL and LVDS Drive to CLKIN/B

Vbias

(V)

Rpu1/2

(kohm)

CLKIN/B Bias Voltage

(V)

3.3

2.5

1.8

22

15

10

0.58

0.60

0.58

2.5V Differential LVPECL Clock Input Interface

The maximum DC 2.5V LVPECL voltage meets the VIH max

CLKIN requirement. Therefore 2.5V LVPECL can be

connected directly to the CLKIN terminals without AC coupling

Zo=50ohm

CLKIN

Zo=50ohm

CLKINB

+2.5V LVPECL

Driver

Versaclock 5 Receiver

R1

50ohm

R2

50ohm

RTT

18ohm

CLKIN, CLKINB Input Driven by a 2.5V LVPECL Driver

REVISION D 10/21/14

27

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90. and 132. The

actual value should be selected to match the differential

impedance (Zo) of your transmission line. A typical

point-to-point LVDS design uses a 100 parallel resistor at the

receiver and a 100. differential transmission-line

environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must

be placed as close to the receiver as possible. The standard

termination schematic as shown in figure Standard

Termination or the termination of figure Optional Termination

can be used, which uses a center tap capacitance to help filter

common mode noise. The capacitor value should be

approximately 50pF. In addition, since these outputs are LVDS

compatible, the input receiver's amplitude and common-mode

input range should be verified for compatibility with the IDT

LVDS output. If using a non-standard termination, it is

recommended to contact IDT and confirm that the termination

will function as intended. For example, the LVDS outputs

cannot be AC coupled by placing capacitors between the

LVDS outputs and the 100 ohm shunt load. If AC coupling is

required, the coupling caps must be placed between the 100

ohm shunt termination and the receiver. In this manner the

termination of the LVDS output remains DC coupled.

Z_O Z_T

LVDS

Z_T

LVDS

Driver

Receiver

Standard Termination

Z_T

2

Z_O Z_T

LVDS

Driver

LVDS

Receiver

Z_T

2

C

Optional Termination

PROGRAMMABLE CLOCK GENERATOR

28

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs generate ECL/LVPECL compatible

outputs. Therefore, terminating resistors (DC current path to

ground) or current sources must be used for functionality.

These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize

operating frequency and minimize signal distortion. The figure

below show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist and

it would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

3.3V

Zo=50ohm

+

-

LVPECL

Input

R1

50ohm

R2

50ohm

RTT

50ohm

3.3V LVPECL Output Termination (1)

3.3V

R3

R4

125ohm

Zo=50ohm

+

-

Zo=50ohm

Input

LVPECL

R1

84ohm

R2

84ohm

3.3V LVPECL Output Termination (2)

REVISION D 10/21/14

29

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Termination for 2.5V LVPECL Outputs

Figures 2.5V LVPECL Driver Termination Example (1) and (2)

show examples of termination for 2.5V LVPECL driver. These

terminations are equivalent to terminating 50 to V_DDO– 2V.

For V_DDO= 2.5V, the V_DDO– 2V is very close to ground level.

The R3 in Figure 2.5V LVPECL Driver Termination Example

(3) can be eliminated and the termination is shown in example

(2).

V_DDO= 2.5V

2.5V

V_DDO= 2.5V

Zo=50ohm

2.5V

R1

250ohm

R3

250ohm

+

-

Zo=50ohm

+

-

2.5V LVPECL

Driver

Zo=50ohm

R1

50ohm

R2

50ohm

2.5V LVPECL

Driver

R2

62.5ohm

R4

62.5ohm

R3

18ohm

2.5V LVPECL Driver Termination Example (3)

2.5V LVPECL Driver Termination Example (1)

V_DDO= 2.5V

2.5V

Zo=50ohm

+

Zo=50ohm

-

2.5V LVPECL

R1

50ohm

R2

50ohm

Driver

2.5V LVPECL Driver Termination Example (2)

PROGRAMMABLE CLOCK GENERATOR

30

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

PCI Express Application Note

For PCI Express Gen2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in RMS. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below

shows the most frequently used Common Clock Architecture

in which a copy of the reference clock is provided to both ends

of the PCI Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes

PLLs are modeled as well as the phase interpolator in the

receiver. These transfer functions are called H1, H2, and H3

respectively. The overall system transfer function at the

receiver is:

Hts = H3s  H1s – H2s

The jitter spectrum seen by the receiver is the result of

applying this system transfer function to the clock spectrum

X(s) and is:

Ys = Xs  H3s  H1s – H2s

In order to generate time domain jitter numbers, an inverse

Fourier Transform is performed on X(s)*H3(s) * [H1(s) -

H2(s)].

PCIe Gen2A Magnitude of Transfer Function

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

PCIe Gen1 Magnitude of Transfer Function

REVISION D 10/21/14

31

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

PCIe Gen3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI Express

Reference Clock Requirements.

Marking Diagram

5901A

XXX

YWW**$

1. Line 1 is the truncated part number.

2. “xxx” denotes dash code.

3. “YWW” is the last digit of the year and week that the part was assembled.

4. “**” denotes sequential lot number.

5. “$” denotes mark code.

PROGRAMMABLE CLOCK GENERATOR

32

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Package Outline and Package Dimensions (24-pin 4mm x 4mm VFQFPN)

REVISION D 10/21/14

33

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Package Outline and Package Dimensions (24-pin 4mm x 4mm VFQFPN), cont.

PROGRAMMABLE CLOCK GENERATOR

34

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Ordering Information

Part / Order Number

5P49V5901AxxxNLGI

5P49V5901AxxxNLGI8

Marking

see page 32

Shipping Packaging

Trays

Package

24-pin VFQFPN

Temperature

-40° to +85C

Tape and Reel

Note: for the specific “xxx” order codes, refer to the VersaClock 5 Ordering Product Information Guide.

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

Revision History

Rev.

A

Date

Originator Description of Change

03/10/14 B. Chandhoke Initial release.

B

06/04/14 B. Chandhoke Updated datasheet with latest document template.

C

09/03/14 B. Chandhoke 1. Extensive updates to AC/DC tables per latest characterization data.

2. Added new Jitter Specifications table.

3. Update device marking.

C

D

10/0114 B. Chandhoke 1. Updated Package Outline and Dimensions drawings to the latest 24VFQFPN document.

2. Updated “Table 3: Configuration Table” and added associated notes.

3. Added “Input Rise/Fall Time” specs to tables 14, 15, and 16.

10/21/14 B. Chandhoke 1. Removed 2.45mm Sq. EPAD option for landing pattern.

2. Updated LVPECL IDD limits.

3. Updated text and examples for Output Skew section.

4. Added SD-OE logic diagram.

REVISION D 10/21/14

35

PROGRAMMABLE CLOCK GENERATOR

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

Sales

Tech Support

email: clocks@idt.com

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether

express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected

names, logos and designs, are the property of IDT or their respective third party owners.

厂商	型号	描述	页数
IDT	5P40040DCGI	[ Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8 ]	12 页
IDT	5P40040DCGI8	[ Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8 ]	12 页
IDT	5P40040DVGI	[ Clock Generator, 200MHz, CMOS, PDSO8, 3 MM, GREEN, MSOP-8 ]	12 页
IDT	5P40040DVGI8	[ Clock Generator, 200MHz, CMOS, PDSO8, 3 MM, GREEN, MSOP-8 ]	12 页
IDT	5P40040NBGI	[ Clock Generator, 200MHz, CMOS, PDSO8, 2 X 2 MM, 0.50 MM PITCH, GREEN, DFN-8 ]	12 页
IDT	5P40040NBGI8	[ Clock Generator, 200MHz, CMOS, PDSO8, 2 X 2 MM, 0.50 MM PITCH, GREEN, DFN-8 ]	12 页
IDT	5P40041DCGI	[ Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8 ]	11 页
IDT	5P40041DCGI8	[ Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8 ]	11 页
IDT	5P40041DVGI	[ Clock Generator, 200MHz, CMOS, PDSO8, 3 MM, GREEN, MSOP-8 ]	11 页
IDT	5P40041DVGI8	[ Clock Generator, 200MHz, CMOS, PDSO8, 3 MM, GREEN, MSOP-8 ]	11 页