®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
speed
10/12ns
Input Pulse Levels
0.2V to Vcc-0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
VCC/2
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
tRC
UNIT
LY61L20498A-10
LY61L20498A-12
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
10
-
-
-
10
10
4.5
-
12
-
-
-
12
12
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
-
-
*
*
*
*
2
0
-
3
0
-
-
-
5
-
4
-
4
-
5
2
-
2
-
(2) WRITE CYCLE
PARAMETER
SYM.
tWC
tAW
tCW
tAS
UNIT
LY61L20498A-10
LY61L20498A-12
MIN.
10
8
MAX.
MIN.
12
10
10
0
MAX.
Write Cycle Time
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
8
-
0
-
-
tWP
tWR
tDW
tDH
tOW
8
-
10
0
-
-
0
-
6
-
7
-
0
-
0
-
*
2
-
2
-
tWHZ
*
-
4
-
5
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
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