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LZ23H3V1

型号:

LZ23H3V1

描述:

三分之一式隔行彩色CCD传感器面积为1 090的k个像素[ 1/3-type Interline Color CCD Area Sensor with 1 090 k Pixels ]

品牌:

SHARP[ SHARP ELECTRIONIC COMPONENTS ]

页数:

20 页

PDF大小:

155 K

LZ23H3V1  
1/3-type Interline Color CCD Area  
Sensor with 1 090 k Pixels  
LZ23H3V1  
• Built-in overflow drain voltage circuit and reset  
gate voltage circuit  
• Variable electronic shutter  
• Package :  
16-pin shrink-pitch WDIP [Ceramic]  
(WDIP016-N-0500C)  
Row space : 12.70 mm  
DESCRIPTION  
The LZ23H3V1 is a 1/3-type (6.0 mm) solid-state  
image sensor that consists of PN photo-diodes  
and CCDs (charge-coupled devices). With  
approximately 1 090 000 pixels (1 217 horizontal x  
893 vertical), the sensor provides a stable high-  
resolution color image.  
PIN CONNECTIONS  
FEATURES  
• Optical size :  
16-PIN SHRINK-PITCH WDIP  
TOP VIEW  
Number of effective pixels  
– Approx. 1 000 k; 6.6 mm  
– Approx. 790 k; 5.9 mm (compatible with XGA  
format)  
OD  
GND  
OFD  
PW  
1
2
3
4
5
6
7
8
16 OS  
15 GND  
14 ØV1A  
13 ØV1B  
12 ØV2  
1 000 k pixels  
(5.9 mm)  
6.6 mm  
ØRS  
790 k pixels  
NC  
11 ØV3A  
10 ØV3B  
(1 024)  
1 156  
ØH1  
ØH2  
9
ØV4  
• Interline scan format  
• Square pixel  
(WDIP016-N-0500C)  
• Number of effective pixels : 1 174 (H) x 884 (V)  
• Number of optical black pixels  
– Horizontal : 3 front and 40 rear  
– Vertical : 7 front and 2 rear  
• Number of dummy bits  
PRECAUTIONS  
• The exit pupil position of lens should be 15 to 50  
mm from the top surface of the CCD.  
• Refer to "PRECAUTIONS FOR CCD AREA  
SENSORS" for details.  
– Horizontal : 22  
– Vertical : 2  
• Pixel pitch : 4.6 µm (H) x 4.6 µm (V)  
• R, G, and B primary color mosaic filters  
• Supports monitoring mode  
• Low fixed-pattern noise and lag  
• No burn-in and no image distortion  
• Blooming suppression structure  
• Built-in output amplifier  
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in  
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.  
1
LZ23H3V1  
PIN DESCRIPTION  
SYMBOL  
PIN NAME  
Output transistor drain  
OD  
OS  
Output signals  
ØRS  
Reset transistor clock  
Vertical shift register clock  
Horizontal shift register clock  
Overflow drain  
ØV1A, ØV1B, ØV2, ØV3A, ØV3B, ØV4  
ØH1, ØH2  
OFD  
PW  
P-well  
GND  
NC  
Ground  
No connection  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
Output transistor drain voltage  
Overflow drain voltage  
(TA = +25 ˚C)  
UNIT NOTE  
V
SYMBOL  
VOD  
VOFD  
VØRS  
VØV  
RATING  
0 to +18  
Internal output  
Internal output  
VPW to +18  
–0.3 to +12  
–29 to 0  
0 to +15  
–40 to +85  
–20 to +70  
V
V
1
2
Reset gate clock voltage  
Vertical shift register clock voltage  
Horizontal shift register clock voltage  
Voltage difference between P-well and vertical clock  
Voltage difference between vertical clocks  
Storage temperature  
V
V
V
VØH  
VPW-VØV  
VØV-VØV  
TSTG  
V
3
˚C  
˚C  
Ambient operating temperature  
TOPR  
NOTES :  
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is  
applied below 27 Vp-p.  
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is  
applied below 8 Vp-p.  
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be  
below 28 V.  
2
LZ23H3V1  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
Ambient operating temperature  
Output transistor drain voltage  
Overflow drain clock p-p level  
Ground  
SYMBOL  
MIN.  
TYP. MAX. UNIT NOTE  
TOPR  
VOD  
VØOFD  
25.0  
14.55 15.0 15.45  
24.5  
˚C  
V
26.5  
V
V
V
1
2
GND  
0.0  
P-well voltage  
VPW  
–10.0  
–9.5  
VØVL  
–8.5  
VØV1AL, VØV1BL, VØV2L  
VØV3AL, VØV3BL, VØV4L  
VØV1AI, VØV1BI, VØV2I  
VØV3AI, VØV3BI, VØV4I  
VØV1AH, VØV1BH  
VØV3AH, VØV3BH  
VØH1L, VØH2L  
VØH1H, VØH2H  
VØRS  
LOW level  
–9.0  
0.0  
V
V
V
Vertical shift  
register clock  
INTERMEDIATE level  
HIGH level  
14.55 15.0 15.45  
Horizontal shift  
register clock  
LOW level  
HIGH level  
Reset gate clock p-p level  
–0.05  
4.5  
4.5  
0.0  
5.0  
0.05  
5.5  
V
V
5.0  
5.5  
V
1
3
4
3
4
3
4
fØV1A, fØV1B, fØV2  
fØV3A, fØV3B, fØV4  
10.88  
13.47  
14.32  
18.00  
14.32  
18.00  
kHz  
kHz  
MHz  
MHz  
MHz  
MHz  
Vertical shift register clock frequency  
Horizontal shift register clock frequency  
fØH1, fØH2  
fØRS  
Reset gate clock frequency  
NOTES :  
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.  
2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected  
to VL of V driver IC.  
3. Operation frequency is 14.32 MHz.  
4. Operation frequency is 18.00 MHz.  
* To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on PW first and then turn on other powers  
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.  
3
LZ23H3V1  
CHARACTERISTICS (Drive method : 1/30 s frame accumulation)  
(TA = +25 ˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".  
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)  
PARAMETER  
Standard output voltage  
Photo response non-uniformity  
SYMBOL  
VO  
PRNU  
MIN.  
TYP. MAX. UNIT NOTE  
150  
mV  
%
2
3
10  
450  
330  
530  
410  
0.5  
0.5  
150  
–75  
mV  
mV  
mV  
mV  
mV  
dB  
%
4
5
1, 6  
1, 7  
8
9
10  
11  
Saturation output voltage  
VSAT  
Dark output voltage  
Dark signal non-uniformity  
Sensitivity (green channel)  
Smear ratio  
VDARK  
DSNU  
R
SMR  
AI  
ABL  
IOD  
LCR  
3.0  
2.0  
105  
500  
–65  
1.0  
Image lag  
Blooming suppression ratio  
Output transistor drain current  
Line crawling  
4.0  
8.0  
3.0  
mA  
%
12  
NOTES :  
• Within the recommended operating conditions of VOD,  
VOFD of the internal output satisfies with ABL larger than  
500 times exposure of the standard exposure conditions,  
and VSAT larger than 330 mV.  
7. The image area is divided into 10 x 10 segments under  
non-exposure conditions. DSNU is defined by (Vdmax –  
Vdmin), where Vdmax and Vdmin are the maximum and  
minimum values of each segment's voltage respectively.  
8. The average output voltage of G signal when a 1 000  
lux light source with a 90% reflector is imaged by a lens  
of F4, f50 mm.  
9. The sensor is exposed only in the central area of V/10  
square with a lens at F4, where V is the vertical image  
size. SMR is defined by the ratio of the output voltage  
detected during the vertical blanking period to the  
maximum output voltage in the V/10 square.  
10. The sensor is exposed at the exposure level  
corresponding to the standard conditions. AI is defined  
by the ratio of the output voltage measured at the 1st  
field during the non-exposure period to the standard  
output voltage.  
11. The sensor is exposed only in the central area of V/10  
square, where V is the vertical image size. ABL is  
defined by the ratio of the exposure at the standard  
conditions to the exposure at a point where blooming is  
observed.  
1. TA = +60 ˚C  
2. The average output voltage of G signal under uniform  
illumination. The standard exposure conditions are  
defined as when Vo is 150 mV.  
3. The image area is divided into 10 x 10 segments under  
the standard exposure conditions. Each segment's  
voltage is the average output voltage of all pixels within  
the segment. PRNU is defined by (Vmax – Vmin)/Vo,  
where Vmax and Vmin are the maximum and minimum  
values of each segment's voltage respectively.  
4. The image area is divided into 10 x 10 segments. Each  
segment's voltage is the average output voltage of all  
pixels within the segment. VSAT is the minimum  
segment's voltage under 10 times exposure of the  
standard exposure conditions. The operation of OFDC is  
high. (for still image capturing)  
5. The image area is divided into 10 x 10 segments. Each  
segment's voltage is the average output voltage of all  
pixels within the segment. VSAT is the minimum  
segment's voltage under 10 times exposure of the  
standard exposure conditions. The operation of OFDC is  
low.  
12. The sensor is exposed at the exposure level  
corresponding to the standard conditions. LCR is defined  
by (∆VG/VO) x 100, where ∆VG is the difference  
between the average output voltage of G signal at the  
1st field, and that of G signal at the 2nd field.  
6. The average output voltage under non-exposure  
conditions.  
4
LZ23H3V1  
PIXEL STRUCTURE  
OPTICAL BLACK  
(2 PIXELS)  
OPTICAL BLACK  
(3 PIXELS)  
OPTICAL BLACK  
(40 PIXELS)  
1 174 (H) x 884 (V)  
1 pin  
OPTICAL BLACK  
(7 PIXELS)  
COLOR FILTER ARRAY  
(1, 884)  
(1 174, 884)  
Pin arrangement  
of the vertical  
readout clock  
ØV3B  
G
B
G
B
G
B
G
B
G
B
ØV1A  
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
ØV3A  
G
ØV1B  
R
ØV3B  
G
R
ØV1A  
ØV3A  
ØV1B  
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
ØV3B  
ØV1A  
ØV3A  
ØV1B  
(1, 1)  
(1 174, 1)  
5
LZ23H3V1  
TIMING CHART  
TIMING CHART EXAMPLE  
Pulse diagram in more detail is shown in the figure q to tafter next page.  
Field accumulation mode Frame accumulation  
Frame accumulation mode  
Field accumulation Field accumulation  
mode at first  
mode at first  
mode  
q
q
w
e
r
e'  
t
q
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
(at OFD shutter operation)  
OFDC  
OS  
(Number of  
vertical line)  
Frame accumulation mode  
Not for use Not for use  
(NOTE 1) (NOTE 1)  
Not for use  
Field accumulation  
Field accumulation mode  
.
..  
.
.
..  
.
.
..  
.
.
..  
.
.
..  
.
(2 3 882 883) (2 3 882 883)  
(2 4 882 884)  
(1 3 881 883)  
mode (2 3 882 883)  
(NOTE 2)  
NOTES :  
1. Do not use these signals immediately after field accumulation mode is transferred to frame  
accumulation mode for still image capturing.  
2. Do not use these signals immediately after frame accumulation mode is transferred to field  
accumulation mode for monitoring mode image.  
* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.  
q
VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FIELD ACCUMULATION MODE¡  
Shutter speed  
1/1 000 s  
453 1  
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
874 875 878 879 882 883 OB2  
GB RG GB RG GB RG  
OB1 OB2 OB5 OB6  
2
3
6
7
10 11 14 15 18 19  
GB RG GB RG GB RG GB RG GB RG  
OS  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
6
LZ23H3V1  
w
VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FRAME ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/1 000 s  
453  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
874 875 878 879 882 883 OB2  
GB RG GB RG GB RG  
OS  
Not for use  
* Do not use the frame signals immediately after field accumulation is transferred to frame  
accumulation mode.  
e, e' VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(2nd FIELD)  
453 454  
459  
463  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
OS e  
Not for use  
Not for use  
872 874 876 878 880 882 884 OB2  
GB GB GB GB GB GB GB  
OB2 OB4 OB6  
1
3
5
7
9
11 13 15 17 19  
RG RG RG RG RG RG RG RG RG RG  
OS e'  
* Do not use the frame signals immediately after field accumulation mode is transferred to frame  
accumulation mode.  
7
LZ23H3V1  
r
VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(1st FIELD)  
900  
906  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
Charge swept transfer (658 stages)  
OFDC  
OB1 OB3 OB5 OB7  
2
4
6
8
10 12 14  
GB GB GB GB GB GB GB  
OS  
Not for use  
* Do not use the frame signals immediately after field accumulation mode is transferred to frame  
accumulation mode.  
t
VERTICAL TRANSFER TIMING FOR 14.3 MHz OPERATION ¿FIELD ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/1 000 s  
906 1  
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
873 875 877 879 881 883 OB1  
RG RG RG RG RG RG  
OS  
Not for use  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
8
LZ23H3V1  
READOUT TIMING FOR 14.3 MHz OPERATION ¿FIELD ACCUMULATION MODE¡  
1316, 1  
HD  
132  
1316, 1  
588 660  
48 80  
392  
536  
ØV1A  
ØV1B  
ØV2  
64 96  
40 88  
408  
552  
436 508  
544  
384  
ØV3A  
ØV3B  
ØV4  
56 104  
400  
560  
5.03 µs  
(72 bits)  
30.5 µs (436 bits)  
41.1 µs (588 bits)  
5.03 µs  
(72 bits)  
91.9 µs (1 316 bits)  
READOUT TIMING FOR 14.3 MHz OPERATION ¿FRAME ACCUMULATION MODE AT FIRST¡  
132  
1316, 1  
1316, 1  
HD  
588 660  
48 80  
392  
536  
ØV1A  
ØV1B  
64 96  
40 88  
408  
552  
ØV2  
436 508  
544  
384  
ØV3A  
ØV3B  
ØV4  
56 104  
400  
560  
5.03 µs  
(72 bits)  
30.5 µs (436 bits)  
41.1 µs (588 bits)  
5.03 µs  
(72 bits)  
91.9 µs (1 316 bits)  
9
LZ23H3V1  
READOUT TIMING FOR 14.3 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(1st FIELD)  
132  
1316, 1  
1
HD  
48  
64  
80  
96  
ØV1A  
ØV1B  
ØV2  
476 548  
40  
56  
88  
104  
ØV3A  
ØV3B  
ØV4  
(2nd FIELD)  
HD  
5.03 µs  
(72 bits)  
33.2 µs (476 bits)  
132  
1316, 1  
1
476 548  
48 80  
64 96  
40 88  
48 80  
64 96  
40 88  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
56 104  
56 104  
ØV4  
5.03 µs  
33.2 µs (476 bits)  
(72 bits)  
HORIZONTAL TRANSFER TIMING FOR 14.3 MHz OPERATION  
1316, 1  
132  
HD  
ØH1  
ØH2  
ØRS  
OS  
40  
117.5  
PRE SCAN (22)  
OB (3)  
OUTPUT (1 174) 1πππ  
..  
1174  
OB (40)  
48  
80  
ØV1A  
ØV1B  
64  
96  
ØV2  
40  
88  
ØV3A  
ØV3B  
56  
104  
ØV4  
92  
72  
ØOFD  
10  
LZ23H3V1  
CHARGE SWEPT TRANSFER TIMING FOR 14.3 MHz OPERATION  
900H  
1
901H 902H  
• • • • •  
905H 906H 1H 2H 3H 4H 5H 6H  
1316  
132  
HD  
2
14 26 38 50  
20 32 44  
1306  
ØV1A  
ØV1B  
8
1312  
ØV2  
2
14 26 38 50  
20 32 44  
1306  
ØV3A  
ØV3B  
8
1
1312  
ØV4  
2
3
4
• • • • • • •  
656  
657  
658  
q
VERTICAL TRANSFER TIMING FOR 18.0 MHz OPERATION ¿FIELD ACCUMULATION MODE¡  
Shutter speed  
1/1 000 s  
442  
449  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
858 859 862 863 866 867 870 871 874 875 878 879 882 883 OB2  
GB RG GB RG GB RG GB RG GB RG GB RG GB RG  
OB1 OB2 OB5 OB6  
2
3
6
7
10 11  
GB RG GB RG GB RG  
OS  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
11  
LZ23H3V1  
w
VERTICAL TRANSFER TIMING FOR 18.0 MHz OPERATION ¿FRAME ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/1 000 s  
442  
449  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
OS  
858 859 862 863 866 867 870 871 874 875 878 879 882 883 OB2  
GB RG GB RG GB RG GB RG GB RG GB RG GB RG  
Not for use  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
e, e' VERTICAL TRANSFER TIMING FOR 18.0 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(2nd FIELD)  
449 450  
455  
459  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
OS e  
OS e'  
Not for use  
Not for use  
856 858 860 862 864 866 868 870 872 874 876 878 880 882 884 OB2  
GB GB GB GB GB GB GB GB GB GB GB GB GB GB GB  
OB2 OB4 OB6  
1
3
5
7
9
11  
RG RG RG RG RG RG  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
12  
LZ23H3V1  
r
VERTICAL TRANSFER TIMING FOR 18.0 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(1st FIELD)  
888  
898  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
Charge swept transfer (668 stages)  
OFDC  
OB1 OB3 OB5 OB7  
2
4
6
8
GB GB GB GB  
OS  
Not for use  
* Do not use the frame signals immediately after field accumulation mode is transferred to frame  
accumulation mode.  
t
VERTICAL TRANSFER TIMING FOR 18.0 MHz OPERATION ¿FIELD ACCUMULATION MODE AT FIRST¡  
Shutter speed  
1/1 000 s  
898  
1
6
10  
HD  
VD  
ØV1A  
ØV1B  
ØV2  
ØV3A  
ØV3B  
ØV4  
ØOFD  
OFDC  
OS  
857 859 861 863 865 867 869 871 873 875 877 879 881 883 OB1  
RG RG RG RG RG RG RG RG RG RG RG RG RG RG  
Not for use  
* Do not use the field signals immediately after frame accumulation mode is transferred to field  
accumulation mode.  
13  
LZ23H3V1  
READOUT TIMING FOR 18.0 MHz OPERATION ¿FIELD ACCUMULATION MODE¡  
1336, 1  
132  
1336, 1  
HD  
725 815  
50 90  
480  
660  
ØV1A  
ØV1B  
ØV2  
70 110  
40 100  
500  
680  
535 625  
670  
470  
ØV3A  
ØV3B  
ØV4  
490  
690  
60 120  
5.00 µs  
(90 bits)  
29.7 µs (535 bits)  
41.1 µs (588 bits)  
5.00 µs  
(90 bits)  
74.2 µs (1336 bits)  
READOUT TIMING FOR 18.0 MHz OPERATION ¿FRAME ACCUMULATION MODE AT FIRST¡  
1336, 1  
132  
1336, 1  
HD  
725 815  
50 90  
480  
660  
ØV1A  
ØV1B  
70 110  
40 100  
500  
680  
ØV2  
535 625  
670  
470  
ØV3A  
ØV3B  
ØV4  
490  
690  
60 120  
5.00 µs  
(90 bits)  
29.7 µs (535 bits)  
41.1 µs (588 bits)  
5.00 µs  
(90 bits)  
74.2 µs (1 336 bits)  
14  
LZ23H3V1  
READOUT TIMING FOR 18.0 MHz OPERATION ¿FRAME ACCUMULATION MODE¡  
(1st FIELD)  
1
132  
1336, 1  
HD  
50  
70  
90  
110  
ØV1A  
ØV1B  
ØV2  
585 675  
ØV3A  
ØV3B  
40  
60  
100  
120  
ØV4  
5.00 µs  
32.5 µs (585 bits)  
132  
(90 bits)  
(2nd FIELD)  
1
1336, 1  
HD  
585 675  
50 90  
50 90  
ØV1A  
ØV1B  
70 110  
40 100  
60 120  
70 110  
ØV2  
40 100  
ØV3A  
ØV3B  
60 120  
ØV4  
5.00 µs  
32.5 µs (585 bits)  
(90 bits)  
HORIZONTAL TRANSFER TIMING FOR 18.0 MHz OPERATION  
1336, 1  
132  
HD  
ØH1  
ØH2  
ØRS  
OS  
40  
137.5  
PRE SCAN (22)  
OB (3)  
OUTPUT (1 174) 1πππππππ  
..  
1174  
OB (40)  
50  
90  
ØV1A  
ØV1B  
70  
110  
ØV2  
40  
100  
ØV3A  
ØV3B  
60  
120  
ØV4  
105  
80  
ØOFD  
15  
LZ23H3V1  
CHARGE SWEPT TRANSFER TIMING FOR 18.0 MHz OPERATION  
888H  
1
889H 890H  
• • • • •  
897H 898H 1H 2H 3H 4H 5H 6H  
1336  
132  
HD  
2
18 34 50 66  
1322  
ØV1A  
ØV1B  
10 26 42 58  
18 34 50 66  
10 26 42 58  
1330  
ØV2  
2
1322  
ØV3A  
ØV3B  
1330  
ØV4  
1
2
3
4
• • • • • • •  
666  
667  
668  
16  
LZ23H3V1  
SYSTEM CONFIGURATION EXAMPLE  
+
OS  
OD  
GND  
ØV1A  
ØV1B  
ØV2  
GND  
OFD  
PW  
ØRS  
NC  
ØV3A  
ØV3B  
ØV4  
ØH1  
ØH2  
+
+
POFD  
VMb  
VL  
VOFDH  
VH3BX  
OFDX  
V2X  
V2  
V4  
V1X  
NC  
V3B  
V3A  
V1B  
V1A  
VMa  
VH  
VH1AX  
V3X  
VDD  
+
GND  
VH3AX  
V4X  
VH1BX  
+
17  
PACKAGES FOR CCD AND CMOS DEVICES  
PACKAGE  
(Unit : mm)  
16 WDIP (WDIP016-N-0500C)  
Center of effective imaging area  
±0.15  
7.00  
Glass Lid  
and center of package  
±0.60  
1.40  
(◊ : Lid's size)  
9
16  
CCD  
Package (Cerdip)  
θ
CCD  
0.04  
Cross Section A-A'  
1
8
MAX.  
Rotation error of die : ¬ = 1.5˚  
±0.10  
11.20  
(◊)  
±0.15  
14.00  
A
±0.10  
TYP.  
0.25  
P-1.78  
A'  
TYP.  
TYP.  
±0.25  
0.46  
0.90  
12.70  
0.25  
M
18  
PRECAUTIONS FOR CCD AREA SENSORS  
PRECAUTIONS FOR CCD AREA SENSORS  
(In the case of plastic packages)  
1. Package Breakage  
– The leads of the package are fixed with  
package body (plastic), so stress added to a  
lead could cause a crack in the package  
body (plastic) in the jointed part of the lead.  
In order to prevent the package from being broken,  
observe the following instructions :  
1) The CCD is a precise optical component and  
the package material is ceramic or plastic.  
Therefore,  
Glass cap  
Package  
ø Take care not to drop the device when  
mounting, handling, or transporting.  
Lead  
Fixed  
ø Avoid giving a shock to the package.  
Especially when leads are fixed to the socket  
or the circuit board, small shock could break  
the package more easily than when the  
package isn’t fixed.  
Stand-off  
2) When applying force for mounting the device or  
any other purposes, fix the leads between a  
joint and a stand-off, so that no stress will be  
given to the jointed part of the lead. In addition,  
when applying force, do it at a point below the  
stand-off part.  
3) When mounting the package on the housing,  
be sure that the package is not bent.  
– If a bent package is forced into place  
between a hard plate or the like, the pack-  
age may be broken.  
4) If any damage or breakage occurs on the sur-  
face of the glass cap, its characteristics could  
deteriorate.  
(In the case of ceramic packages)  
– The leads of the package are fixed with low  
melting point glass, so stress added to a  
lead could cause a crack in the low melting  
point glass in the jointed part of the lead.  
Therefore,  
ø Do not hit the glass cap.  
ø Do not give a shock large enough to cause  
distortion.  
ø Do not scrub or scratch the glass surface.  
– Even a soft cloth or applicator, if dry, could  
cause dust to scratch the glass.  
Low melting point glass  
Lead  
2. Electrostatic Damage  
As compared with general MOS-LSI, CCD has  
lower ESD. Therefore, take the following anti-static  
measures when handling the CCD :  
Fixed  
1) Always discharge static electricity by grounding  
the human body and the instrument to be used.  
To ground the human body, provide resistance  
of about 1 M$ between the human body and  
the ground to be on the safe side.  
Stand-off  
2) When directly handling the device with the  
fingers, hold the part without leads and do not  
touch any lead.  
19  
PRECAUTIONS FOR CCD AREA SENSORS  
3) To avoid generating static electricity,  
a. do not scrub the glass surface with cloth or  
plastic.  
ø The contamination on the glass surface  
should be wiped off with a clean applicator  
soaked in Isopropyl alcohol. Wipe slowly and  
gently in one direction only.  
b. do not attach any tape or labels.  
c. do not clean the glass surface with dust-  
cleaning tape.  
– Frequently replace the applicator and do not  
use the same applicator to clean more than  
one device.  
4) When storing or transporting the device, put it in  
a container of conductive material.  
◊ Note : In most cases, dust and contamination  
are unavoidable, even before the device  
is first used. It is, therefore, recommended  
that the above procedures should be  
taken to wipe out dust and contamination  
before using the device.  
3. Dust and Contamination  
Dust or contamination on the glass surface could  
deteriorate the output characteristics or cause a  
scar. In order to minimize dust or contamination on  
the glass surface, take the following precautions :  
1) Handle the CCD in a clean environment such  
as a cleaned booth. (The cleanliness level  
should be, if possible, class 1 000 at least.)  
2) Do not touch the glass surface with the fingers.  
If dust or contamination gets on the glass  
surface, the following cleaning method is  
recommended :  
4. Other  
1) Soldering should be manually performed within  
5 seconds at 350 °C maximum at soldering iron.  
2) Avoid using or storing the CCD at high tem-  
perature or high humidity as it is a precise  
optical component. Do not give a mechanical  
shock to the CCD.  
ø Dust from static electricity should be blown  
off with an ionized air blower. For anti-  
electrostatic measures, however, ground all  
the leads on the device before blowing off  
the dust.  
3) Do not expose the device to strong light. For  
the color device, long exposure to strong light  
will fade the color of the color filters.  
20  
厂商 型号 描述 页数 下载

YAGEO

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YAGEO

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YAGEO

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