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Audio Processor for Digital

Hearing Aids and Hearables

EZAIRO 8300

Introduction

®

Ezairo 8300 includes six programmable or semi−programmable

processing cores, providing a high degree of parallelism and

flexibility:

www.onsemi.com

• The CFX is an open−programmable dual−Harvard 24 bits digital

signal processor (DSP) providing support for any type of audio signal

processing

®

• The Arm Cortex −M3 processor is a 32−bit RISC processor

providing support for general processing and interfacing to external

components

• The HEAR configurable accelerator core is optimized for

pre−programmed functions that are frequently needed in audio signal

processing

WLCSP87

CASE 567ZN

VFBGA78

CASE 138AW

MARKING DIAGRAMS

• The Filter Engine allows time domain filtering and supports an

ultra−low−delay audio path

• The LPDSP32 is an open−programmable dual−Harvard 32−bit DSP

AWLYYWW

• The Neural Network Accelerator that allows the Ezairo 8300 to

perform neural network computations in a highly efficient and

flexible way.

ZZ

G

WLCSP87

Ezairo 8300 includes 4 ADCs with signal detection mode and 2

direct digital output drivers, with high quality and ultra−low power

performances. Ezairo 8300 also includes peripherals and interfaces

needed to make it a complete hardware platform, when combined with

non−volatile memory and wireless transceivers.

XXXXXXX

AWLYYWW

CCCCC

G

VFBGA78

o

= Pin 1 indicator

XXXX = Specific Device Code

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

ZZ = Wafer Number

CCC = Country of Origin

A

G

= Pb−Free Package

ORDERING INFORMATION

Device

Package

Shipping

E8300−

101WC78−ABG

Bare Die

(Pb−Free)

5000 / Tape

and Reel

E8300−

101B78−ABG

VFBGA

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

1

Publication Order Number:

June, 2021 − Rev. 3

E8300/D

EZAIRO 8300

Key Features

• High Performance: Best in class MIPS/mW.

• High fidelity audio system: 108 dB system dynamic

range, up to 64 KHz of sampling frequency

• Output drivers: capable of driving multiple types of

speakers.

• Programmable Flexibility: the open−programmable

DSP−based system can be customized to the specific

signal processing needs of manufacturers. Algorithms

and features can be modified or completely new

concepts implemented without having to modify the

chip.

• Versatile Memory Architecture: a total of 1433 kB of

memory, shared between the six programmable or

semi−programmable cores.

• Highly−integrated SoC: the six−core architecture

includes a CFX DSP, an Arm Cortex−M3 Processor, a

HEAR Configurable Accelerator, a programmable

Filter Engine, a LPDSP 32 DSP and a Neural Network

Accelerator. The system also includes an efficient

input/output controller (IOC), system memories, input

and output stages along with a full complement of

peripherals and interfaces.

• CFX DSP: a highly cycle−efficient, programmable

core that uses a 24−bit fixed−point, dual−MAC,

dual−Harvard architecture. The CFX can be used as the

master of the whole Ezairo 8300 SoC.

• Arm Cortex−M3 Processor: a complete subsystem

that can be used as the master of the whole Ezairo 8300

SoC.

• HEAR Configurable Accelerator: a highly optimized

signal processing engine designed to perform common

signal processing operations and complex standard

filterbanks.

• Data Security: sensitive program data can be

encrypted for storage in external NVM to prevent

unauthorized parties from gaining access to proprietary

algorithm and intellectual property.

• Multiple Audio Input Sources: four analog input

channels (AI0 to AI3) that can be used simultaneously

for omni−directional and directional microphones,

telecoils, bone conducting microphones, an input from

a remote control interface, or a direct audio input.

• Signal Detection Mode: ultra−low−power detection

system for signals on any analog inputs.

• High Throughput Communication Interface: fast

2

I C−based and SWJ−DP interfaces for quick download,

debugging and general communication.

• Highly Configurable Interfaces: two PCM interfaces,

2

3

three I C interfaces, two I C interfaces, two SPI

interfaces, a UART interface, an eMMC interface with

custom interface buffering, up to 36 GPIOs and 8

LSAD inputs.

• Programmable Filter Engine: a filtering system that

allows applying a various range of pre− or

post−processing filtering, such as IIR, FIR and biquad

filters.

• LPDSP32: a highly cycle−efficient, programmable

core that uses a 32−bit fixed−point, dual−MAC,

dual−Harvard architecture.

• Neural Network Accelerator (NNA): a configurable

hardware accelerator dedicated to support neural

networks with high energy efficiency.

• Selectable System Clock Speeds: from 2.56 MHz up

to 61.44 MHz, with clock throttling capabilities to

optimize the computing performance versus power

consumption ratio.

• Asynchronous Sample Rate Converter (ASRC):

provides a mean of synchronizing the audio sample rate

between an external radio chip and the Ezairo 8300.

• Two Audio Sink Clock Counters: Can be used to

measure the timing of the frame periods of an external

radio relative to the internal audio sampling rate.

• Fitting Support: support for Microcard, HI−PRO 2,

HI−PRO USB, QuickCom, and NOAHlink, including

NOAHlink’s audio streaming feature.

• Integrated Development Environment (IDE): a

graphical user interface with the capabilities to edit,

build and debug applications. It is the main

programming interface for the Software Development

Kit (SDK).

• Adaptive Voltage Scaling: automatically adjusts the

digital supply voltage (VDDC) level using a critical

path speed measurement block. This feature allows to

optimize the SoC’s power consumption in all situations.

• Ultra−low Delay path: the programmable Filter

Engine supports an ultra−low−delay audio path of min

10.4 ms (analog input to analog output) for features

such as active noise cancellation.

• Ultra−low Power Consumption: <0.7 mA @ 15.24

MHz system clock (CFX 97%, Arm Cortex−M3

processor 40%, HEAR 77%, FENG 9%, 2 ADC @

20 kHz, 1 OD, 1 LSAD)

• Complete C−development tool chain for the CFX

and the LPDSP32. Includes a C−compiler, an

instruction set simulator, an assembler/disassembler, a

linker and the IDE debugger integrated in the Ezairo

8300 SDK.

• Sample Code: The SDK includes several sample

applications and libraries to demonstrate key features of

Ezairo 8300. The libraries are typically provided in

compiled form with source code also available.

• Pb−Free Device

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2

EZAIRO 8300

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Typ

−

Max

Unit

V

Notes

Power supply voltage

Output driver power supply voltage

I/O supply voltage

VBAT

−

1.98

VBATOD

−

1.98

V

VDDO1/2/3/4

VSSA

−

1.98

V

0

−

V

Analog ground

VSSOD

VSSC

0

−

V

Output driver ground

Digital ground

0

−

V

VSSO

0

VSSO−0.1

−0.1

−

VDDO+0.3

1.98

V

I/O ground

Vin

−

V

Digital input pin voltage

Operational temperature

Extended op. temperature (Note 1)

Storage temperature

−

V

Toperation

Tfunctional

Tstorage

0

25

−

50

°C

−40

85

−40

125

Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V) The device in VFBGA package meets 250 V CDM level, JESD22−C101.

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. The IC is functional in the extended temperature range, however some parameters may not meet the specifications. E.g. bandgap voltage,

oscillator frequency, ADC noise...

Table 2. OVERALL OPERATING CONDITIONS

Parameter

VBAT

Min

0.9

−

Typ

1.25

15.36

Max

1.98

61.44

−

Unit

V

Notes

Supply voltage, measured at the VBAT pin (Note 2)

Output driver supply voltage (Note 3)

I/O voltage (Note 4)

VBATOD

V

VDDO1/2/3/4

System clock

VDDC retention

V

MHz

V

System clock frequency

0.50

0.53

(Note 5)

Digital supply voltage, when memories are in retention mode

VDDC limit

0.50

0.76

0.50

0.76

0.51

−

0.88

−

V

Digital supply voltage limit for adaptive voltage scaling

(Note 5)

VDDC active

VDDM retention

VDDM standby

VDDM active

0.78

(Note 5)

Digital supply voltage in active mode; used as upper limit for

adaptive voltage scaling

0.58

(Note 5)

Memories supply voltage, when memories are in retention mode

0.80

(Note 5)

−

Memory supply voltage in standby mode

0.78

(Note 5)

0.88

Memory supply voltage in active mode (Note 6)

2. With VBAT below 1.0V, the performance will be degraded. E.g. reduced PSRR, line & load regulations.

3. At system boot, VBATOD is internally connected to VBAT for 5 ms. In case VBATOD is supplied at 1.8 V and VBAT is supplied at 1.25 V,

a current of ~130 mA will flow from VBATOD to VBAT. This current does not represent a reliability risk for a typical usage of the chip of 10 boots

per day over 10 years.

4. With VDDO below 1.0 V, the performance will be degraded, e.g. the drive strength will be reduced.

5. These values indicate the target trimming values.

6. The VDDM voltage should be higher or equal to the core voltage (VDDC).

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3

EZAIRO 8300

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = 1.25 V. The system clock

(SYS_CLK) was set to 15.36 MHz. Parameters marked as screened are tested on each chip.

CURRENT CONSUMPTION

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Current

consumption

I

CFX load 97%, Arm Cortex−M3 processor load

40%, HEAR load 77%, Filter Engine load 9%

−

0.7

0.9

mA

a

VBAT

2 ADC @ 20 kHz, 1 OD, 1 LSAD

SYS_CLK=15.36 MHz, CCO mult = 2

Standby Current

I

Using ON Semiconductor’s macro

−

90

120

mA

a

STDB

CFX power

consumption

I

Running 31−tap FIR, processing 4 output

points in parallel

13.7

−

mA/MHz

CFX

Arm Cortex−M3

processor pow-

er consumption

I

Running 31−tap FIR, taking advantage of sym-

metrical coefficients

−

8.3

−

mA/MHz

CM3

HEAR power

consumption

I

Running 31−tap FIR, HEAR FIR_R function

Running 31−tap FIR

−

18.7

12.0

−

mA/MHz

HEAR

Filter Engine

power con-

sumption

FENG

LPDSP32 pow-

er consumption

I

Running G.722 decoding

−

10.0

17.5

−

mA/MHz

LPDSP32

NNA power

consumption

I

256−input, 256−output layer, tanh activation

function, 8−bit inputs and outputs, 8−bit uncom-

pressed weights

NNA1

I

256−input, 256−output layer, tanh activation

function, 8−bit inputs and outputs, 4−bit loga-

rithmic encoded weights

−

19.7

−

mA/MHz

NNA2

NOTE: SYS_CLK = 15.36 MHz using adaptive voltage scaling.

NOTE: Currents are on VBAT at 1.25 V

VREG

Parameter

Symbol

Conditions

< 200 mA, trimmed

Min

Typ

Max

Unit

Screened

Output voltage

VREG

50 mA < I

0.89

0.9

0.91

V

a

LOAD

bandgap (Note 7)

Load current

I

−

6

−

2

5

mA

mV/V

mV/mA

dB

LOAD

Line regulation

Load regulation

PSRR @ 1 kHz

LINE

I

= 1 mA

REG

LOAD

5 mA < I

< 2 mA

−

10

−

REG

LOAD

PSRR

I

= 1 mA, VBAT > 1.05 V

80

LOAD

7. VBAT ≥ 1 V is required to have VREG at 0.9 V. Trimming steps: 5 mV. The typical (Typ) value shown for VREG is its target trimming value.

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4

EZAIRO 8300

VDDA

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Output voltage

VDDA

Standby Mode (STBY), I

<

1.7

1.8

1.9

V

a

LOAD

100 mA, VBAT > 0.90 V

Low−Power Mode (LPM), I

100 mA, VBAT > 0.92 V

=

1.7

1.8

−

1.9

V

LOAD

High-Power Mode (HPM), I

4 mA, VBAT > 0.95 V

<

a

LOAD

Typical output volt-

age trimming range

VDDA

LPM, Typical Process, 25°C,

1.57

1.98

RANGE

VBAT = 1.25 V; I

= 100 mA

LOAD

Trimming steps

Load current

VDDA

I

−

6.5

−

100

500

4

mV

mA

STEP

STBY

LPM

LOAD

100

−

mA

HPM

mA

Load regulation

Line regulation

LOAD

LPM, VBAT = 1.20 V;

100 mA < I < 500 mA

4

10

mV/mA

REG

LOAD

HPM, VBAT = 1.20 V;

1 mA < I < 2 mA

−

4

10

4

10

36

10

−

mV/mA

mV/V

dB

LOAD

LINE

SDBY, 1.2 V < VBAT < 1.86 V;

= 100 mA

REG

I

LOAD

LPM, 1.2 V < VBAT < 1.86 V;

= 100 mA

−

I

LOAD

HPM, 1.2 V < VBAT < 1.86 V;

= 1 mA

−

4

I

LOAD

PSRR

VDDA

VBAT = 1.2 V; @ 1 kHz

40

−

PSSR

VDDIF

Parameter

Symbol

VDDIF

Conditions

Min

Typ

Max

Unit

Screened

Output voltage

(high−power mode)

VBAT > 0.95 V; I

(Note 8)

< 5 mA

1.7

1.8

(2xVBAT –

100 mV)

(Note 9)

V

LOAD

VBAT > 1.05V; I

< 15 mA

1.7

1.8

(2xVBAT –

200 mV)

(Note 9)

V

a

LOAD

Typical output volt-

age trimming range

VDDIF

1.57

−

1.98

RANGE

Trimming steps

Load current

VDDIF

−

6.5

−

1

mV

mA

STEP

I

Low−power mode

High−power mode

VBAT = 1.2 V; HPM, I

LOAD

−

15

10

20

−

mA

Load regulation

LOAD

= 5 mA

−

5

mV/mA

mV/V

dB

REG

LOAD

VBAT = 1.2 V; LPM; I

VBAT > 1.2 V; I

= 500 mA

−

17

4

Line regulation

PSRR

LINE

VDDIF

= 100 mA

−

LOAD

VBAT = 1.2 V; @ 1 kHz, I

= 5 mA

30

−

PSSR

LOAD

8. VBAT voltage on IC pin

9. VDDIF max can’t exceed 1.98 V

NOTE: Low Power Mode (LPM): Switching frequency = 128 kHz / itrim = 0X00

High Power Mode (HPM): Switching frequency = 320 kHz / itrim = 0X10

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5

EZAIRO 8300

VMIC

The output voltage on the VMIC pin can be chosen from

5 different sources:

• VMIC regulator powered by VBAT

• VMIC regulator powered by VDDA

• VREG

• VDDA

• VDDIF

VMIC

Parameter

Symbol

Conditions

Min

50

Typ

100

−

Max

250

1.3

Unit

W

Screened

Switch impedance

VMIC

Measured with a 250 mA load current

IMP

Typical output volt-

age trimming range

VMIC

Regulator powered by VBAT.

Maximum Output: VBAT−0.1 V

0.8

V

a

Regulator powered by VDDA

0.8

−

25

−

1.3

−

V

mV

Trimming steps

Load current

VMIC

STEP

I

−

500

10

−

uA

LOAD

Line regulation

Load regulation

LINE

LOAD

−

mV/V

mV/mA

dB

REG

−

5

REG

Regulator VDDA

PSRR

VMIC

Regulated from VDDA

60

−

PSSR

Regulator VBAT

PSRR

Regulated from VBAT, VBAT−VMIC >

0.1 V

80

−

dB

NOTE: The resistor between GND_MIC and VSSA is 50 Ohm.

VDDOD

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Typical output volt-

age trimming range

VDDOD

Maximum Output: VBAT−0.2 V

0.8

−

1.4

V

a

Trimming steps

Load current

Line regulation

Load regulation

PSRR

VDDOD

−

25

−

mV

mA

STEP

I

25

10

−

LOAD

LINE

−

mV/V

mV/mA

dB

REG

LOAD

−

1

REG

VMIC

40

−

PSSR

NOTE: We recommend to always enable the VDDOD regulator. It improves the PSRR when large transient currents are drawn elsewhere

in the Ezairo 8300 based system and gives an audio output level that is independent of the battery voltage.

VDDM/VDDC

Parameter

Symbol

VDDM

Conditions

Min

Typ

Max

Unit

Screened

Typical output volt-

age trimming range

,

(Note 10)

0.45

−

0.88

V

a

RANGE

VDDC

RANGE

Trimming steps

VDDM

VDDC

,

−

2

−

mV

STEP

Load regulation

Line regulation

Load current

LOAD

−

7

−

10

5

mV/mA

mV/V

mA

REG

LINE

I

−

LOAD

PSRR @ 1 kHz

VDDM

VDDC

,

VBAT = 1.25 V, VDDC/M = 0.80 V,

= 500 mA

25

−

dB

PSRR

I

LOAD

10.The voltage of VDDC and VDDM shall not go beyond the values specified in the operating conditions.

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6

EZAIRO 8300

REGULATORS TEMPERATURE STABILITY

Parameter

Symbol

Conditions

Temperature range of −5 to 50°C.

Min

Typ

Max

Unit

Screened

Temperature Stability

−0.5

−

0.5

%

NOTE: Temperature stability for VREG, VDDA (LPM and HPM), VMIC, VDDOD, VDDC (using the band gap as reference) and VDDM

(using the band gap as reference):

REGULATORS TEMPERATURE STABILITY

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Temperature Stability

Temperature range of −5 to 50°C.

−2

−

2

%

NOTE: Temperature stability for VDDA (STBY), VDDC (using the PMU as reference) and VDDM (using the PMU as reference):

POWER−ON−RESET

Description

Symbol

Vth

Conditions

Min

Typ

Max

Unit

Screened

VBAT startup voltage: High

threshold voltage

0.68

0.77

0.86

V

a

High

VBAT shutdown voltage: Low

threshold voltage

Vth

0.63

0.72

0.81

V

a

Low

NOTE: Typical time duration between application of VBAT and first NVM access: 77 ms

INPUT STAGE

Parameter

Symbol

IN

Conditions

Min

Typ

Max

Unit

Screened

Nominal input referred

noise 16 kHz SF, RMS

A−weighted 100 Hz−8 kHz, 16 kHz

SF, nominal current setting

−

2

4

mVrms

IRN

Nominal input referred

noise 32 kHz SF, RMS

A−weighted 100 Hz−16 kHz, 32 kHz

−

3

10

mVrms

dB

a

SF, maximum current setting

(Note 11)

HiQ input referred noise

16 kHz SF, RMS

A−weighted 100 Hz−8 kHz, 16 kHz

SF, maximum current setting

1.5

3

HiQ input referred noise

48 kHz SF, RMS

A−weighted 20 Hz−20 kHz, 48 kHz

SF, maximum current setting

10

(Note 12)

a

Nominal dynamic range

IN

DR

A−weighted 100 Hz−8 kHz, nominal

current setting

109

112

−

HiQ dynamic range

A−weighted 100 Hz−8 kHz, maxi-

mum current setting

dB

Input range

IN

At VDDA 1.8 V

0

10

−

1.6

−

V

RANGE

Input impedance

Peak THDN

R

Nominal and HiQ mode

MW

dB

IN

−85

−

−70

0.1

a

THDN

Channel gain mismatch

Calibrated (using digital gain factor,

1 kHz) or not calibrated.

−

Channel delay mismatch

At 1 kHz ( approx. max 0.54 deg)

−

1.5

ms

Ultrasonic immunity, in-

put referred aliased level

A−weighted 100 Hz − 16 kHz aliased

level with a −40 dBV input signal

swept from 20 kHz to 50 kHz

−95

−85

dBV

Signal detection mode

input referred noise

A−weighted 100 Hz−10 kHz, 1 MHz

operation, current setting at 0x1 (4 mA)

−

10

20

mVrms

Microphone bias voltage

MIC

In order to maximize dynamic range of

the input stage, the microphone bias

should be set to the typical value.

0.2

0.75

1.0

V

BIAS

NOTE: Input Stage specifications are A−weighted, bandwidth 100 Hz−fs/2, sampling frequencies 16/32/48 kHz, with ADC_CLK =

3.84 MHz. The CCO multiplier doesn’t affect the specifications of the ADC as long as the ADC_CLK is around 4 MHz.

NOTE: The specifications at 20 kHz are between the specifications at 16 and 32 kHz.

11. By characterization, the Max value is 5 mVrms.

12.By characterization, the Max value is 5 mVrms.

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7

EZAIRO 8300

OUTPUT STAGE

Parameter

Symbol

Conditions

= 1 mA. High and Low side

LOAD

Min

Typ

Max

Unit

Screened

Output resistance

R

I

−

2

−

W

OD

combined.

Output Dynamic Range

OD

103

−

108

105

100

−72

−61

−81

−

dB

mV

High impedance load (>1 kW),

DR

XSDM0 mode

Low impedance speaker mode,

36R load, XSDM0 mode

High impedance load (>1 kW),

OD_DELAY mode

95

−

Peak THD+N

OD

@ 1 kHz, high impedance load

(>1 kW), XSDM0 mode

−61

(Note 13)

a

THDN

@ 1 kHz, low impedance speaker

mode, 36R load, XSDM0 mode

−

@ 1 kHz, high impedance load

(>1 kW), OD_DELAY mode

−

−75

4.3

Output noise RMS

OD

At 1.25 V VBATOD; scales linear-

ly with VBATOD

−

ORN

Output Bandwidth

OD

−

24

25

kHz

mA

BW

Maximum output current

I

This current can be drawn but

with degraded audio quality.

OD

Power supply rejection

ratio (PSRR)

OD

−

−30

−85

−

dB

PSRR

Using VDDOD regulator

−75

NOTE: Output stage specifications are A−weighted, bandwidth 100 Hz−fs/2, sampling frequencies 16/32/48 kHz, with SDM_CLK =

15.36 MHz, SYS_CLK = 15.36 MHz (CCO multiplier = 1), and with VDDOD = 1.0 V

NOTE: The performances of the OD are optimized when the SDM_CLK operates on the CCO base frequency (the un−multiplied frequency).

13.By characterization, the Max value is −65 dB.

LSAD

Parameter

ADC Resolution

Input signal level

Sampling rate

Symbol

Conditions

Min

8

Typ

12

−

Max

14

Unit

Bits

V

Screened

LSAD

Depends on frequency setting

RES

LSAD

0

1.8

−

a

RANGE

LSAD

For a sample clock of 128 kHz

(20 cycles per measurement)

−

6.4

kHz

SF

lsad_clk frequency

INL

LSAD

−

−2

−1

1

100

−

128

+2

+1

−

kHz

mV

MW

CLK

LSAD

INL

DNL

LSAD

−

DNL

Input Impedance

LSAD

−

INI

IOs

Parameter

Symbol

Conditions

Min

−

Typ

−

Max

0.7x VDDO

−

Unit

V

Screened

Voltage level of high input

Voltage level of low input

Voltage level of high output

Voltage level of low output

Weak pull−up Impedance

V

IH

a

V

IL

0.3x VDDO

0.8x VDDO

VSSO

225

−

V

OH

−

VDDO

0.2x VDDO

275

V

OL

V

IMP

250

50

kW

WUP

MUP

Medium pull−up

Impedance

45

60

Medium pull−down

Impedance

IMP

45

50

60

kW

a

MDW

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8

EZAIRO 8300

IOs

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Strong pull−up

Impedance

IMP

0.8

1

1.2

kW

a

SUP

Pad Input Delay

IN

VDDO=1.8V

−

0.76

1.23

1.24

ns

DELAY

VDDO=1.2V

Pad Output Delay

OUT

DELAY

VDDO=1.8V

1x drive strength, 1 pF load

2x drive strength, 2 pF load

4x drive strength, 4 pF load

8x drive strength, 8 pF load

VDDO=1.2V

−

1.74

8

ns

1x drive strength, 1pF load

2x drive strength, 2 pF load

4x drive strength, 4 pF load

8x drive strength, 8 pF load

Drive Strength

DRIVE

Configurable with 1x, 2x, 4x, 8x

Nominal drive strength: 1 mA

1

Multiple

of the

nominal

drive

strength

Maximum

SYS_CLK

Max Switching

Frequency

IOFR

−

Max

Glitch filter : additional

rise delay

DELAY

−

169

245

ns

RAISE

Glitch filter : additional

fall delay

DELAY

FALL

NOTE: DC Characteristics of the digital pad at VDDO 1.08/1.8/1.98V

NOTE: The glitch filter cuts glitches with duration shorter than 50 ns

CURRENT CONTROLLED OSCILLATOR (CCO)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Recommended Working

Frequency

SYS_CLK

For recommended VDDC and

VDDM

2.56

−

61.44

MHz

Boot frequency

SYS_CLK

5

7.68

0.10

10

MHz

%

a

Oscillator frequency

trimming precision

−

0.20

Frequency stability in

temperature

Temp: 0°C and 50°C. After cali−

−1.5

−4

−

1.5

4

%

bration at room temperature (25°C)

Temp: −40°C and 85°C. After cali−

bration at room temperature (25°C)

Period jitter (rms)

RMS, at 5.12 MHz, before

multiplication

200

ps

RMS, at 5.12 MHz, after

multiplied by 2 and divided by a

multiple of 2

−

RMS, at 5.12 MHz, after

multiplied by 4 and divided by a

multiple of 4

−

200

ps

Output duty cycle

Max frequency

With multiplier setting 1x or 2x

With multiplier setting 4x

Un−multiplied

45

40

−

55

60

−

%

30

MHz

LOW DELAY PATH (using the low delay path of the Filter Engine)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Screened

Analog to analog delay

Fs=48kHz FENG delay: one sample

−

10.4

−

ms

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9

EZAIRO 8300

EZAIRO 8300 INTERNAL ARCHITECTURE

The architecture of the Ezairo 8300 is shown on the following diagram:

Figure 1. Ezairo 8300 Architecture

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10

EZAIRO 8300

ARCHITECTURE OVERVIEW

The Ezairo 8300 system is an asymmetric 6−core

• Dual address generator units

architecture, mixed−signal system−on−chip designed

specifically for the audio processing needs ultra−lower

power portable devices. It centers around 6 processing

cores: the CFX Digital Signal Processor (DSP), the Arm

Cortex−M3 Processor, the LPDSP32 Digital Signal

Processor (DSP), the HEAR Configurable Accelerator, the

Filter Engine and the Neural Network Accelerator.

• A wide range of addressing modes:

♦ Direct

♦ Indirect with post−modification

♦ Modulo addressing

♦ Bit reverse

Software development on the CFX is done in C or assembly,

and the development tools are available in the Ezairo 8300

SDK.

CFX DSP Core

The CFX DSP is a user−programmable general−purpose

DSP core that uses a 24−bit fixed−point, dual−MAC,

dual−Harvard architecture. It is able to perform two MACs,

two memory operations and two pointer updates per cycle,

making it well−suited to computationally intensive

algorithms.

The CFX DSP is used for custom signal processing

applications. The CFX DSP core can also be used as the

master of the Ezairo 8300 SoC, by configuring the system

and the other cores, by managing the Interrupts and by

coordinating the flow of signal data progressing through the

system.

In cases where the Arm Cortex−M3 processor is used as

the master of the system, the CFX is slave to the Arm

Cortex−M3 processor. The inter−processor communication

methods between the CFX processor and the rest of Ezairo

8300 are based on shared memories and interrupts.

CFX DSP Architecture

The CFX employs a parallel instruction set for

simultaneous control of multiple computation units. The

DSP can execute up to four computation operations in

parallel with two data transfers (including rounding and/or

saturation as well as complex address updates), while

simultaneously changing control flow.

The CFX architecture encompasses various memory

types and sizes, peripherals, interrupt controllers, and

interfaces.

Figure 2 illustrates the basic architecture of the CFX. The

control lines shown exiting the PCU indicate that control

signals go from the PCU to essentially all other parts of the

CFX.

The CFX features:

• Dual−MAC 24−bit load−store DSP core

• Four 56−bit accumulators

• Four 24−bit input registers

• Support for hardware loops nested up to four deep

• Combined XY memory space (48 bits wide)

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EZAIRO 8300

Figure 2. CFX DSP Core Architecture

Arm Cortex−M3 Processor

accelerator (NNA), or the LPDSP32 DSP (which is

expected to be used for codecs, a neural network, and

similar use cases).

The Arm Cortex−M3 processor is a low−power processor

that features low gate count, low interrupt latency, and

low−cost debugging. It is intended for deeply embedded

applications that require fast interrupt response features.

GNU tools provide build and link support for C programs

that run on the Arm Cortex−M3 processor.

The Arm Cortex−M3 processor implements the

ARMv7−M architecture. For power management, the

processor can be placed into a sleep mode under firmware

control in which the processor clock is disabled. The Nested

Vectored Interrupt Controller (NVIC) continues to run to

enable exiting sleep on an interrupt.

The Arm Cortex−M3 processor typically performs one or

more of the following roles:

• The system master, configuring the system and the

other cores, by managing the interrupts, and by

coordinating the flow of signal data progressing

through the system

In cases where the CFX is used as the master of the system,

the Arm Cortex−M3 processor is slave to the CFX. The

inter−processor communication methods between the Arm

Cortex−M3 processor and the rest of Ezairo 8300 are based

on shared memories and interrupts.

HEAR Configurable Accelerator

The HEAR coprocessor is designed to perform both

common signal processing operations and complex standard

filterbanks such as the WOLA filterbank, reducing the load

on the system programmable DSP cores.

The HEAR Configurable Accelerator is a highly optimized

signal processing engine that is configured through the CFX

or Arm Cortex−M3 processor. It offers high speed, high

flexibility and high performance, while maintaining low

power consumption. For added computing precision, the

HEAR supports block floating point processing.

Configuration of the HEAR is performed using the HEAR

Configuration Tool (HCT). For further information on the

usage of the HEAR, refer to the HEAR Configurable

Accelerator Reference Manual.

• A coprocessor to the CFX DSP that provides additional

microcontroller computation for interface drivers and

protocols executing on those interfaces

• A controller for managing hardware acceleration

peripherals such as the Reed−Solomon, G.722 blocks,

the asynchronous sample rate converter (ASRC), the

audio sink clock counters (ASCC), the neural network

The HEAR is optimized for advanced algorithms

including but not limited to the following:

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EZAIRO 8300

Filter Engine

• Dynamic range compression

• Directional processing

• Feedback cancellation

• Noise reduction

To execute these and other algorithms efficiently, the HEAR

excels at the following:

The Filter Engine is a core that provides low−delay path

and basic filtering capabilities for the Ezairo 8300 system.

The Filter Engine can implement filters (either FIR or IIR)

with a total of up to 320 coefficients. FIR filters are

implemented using a direct−form structure. IIR filters are

implemented with a cascade of second−order sections

(biquads), each implemented as a direct−form I filter.

The Filter Engine is programmable, but does not include

direct debugging access. The CFX and the Arm Cortex−M3

Processor can monitor the Filter Engine state through

control and configuration registers on the program memory

bus.

• Processing using a weighted overlap add (WOLA)

filterbank

• Time domain filtering

• Subband filtering

• Attack/release filtering

• Vector addition/subtraction/multiplication

• Signal statistics (such as average, variance and

correlation)

Figure 3. Filter Engine: Audio Filtering and Multipliexing

LPDSP32 DSP

peripherals. Once initialized, the CFX DSP and/or the Arm

Cortex−M3 processor control the LPDSP32 DSP’s

execution state.

LPDSP32 is a C−programmable, 32−bit DSP developed

by ON Semiconductor. LPDSP32 is a high efficiency, dual

Harvard DSP that supports both single (32−bit) and double

precision (64−bit) arithmetic.

LPDSP32’s dual MAC unit, load store architecture is

specifically optimized to support audio processing tasks

such as audio codecs that might be required for wireless

audio communication tasks, Artificial Intelligence (AI)

functions, and other advanced developments requiring the

additional processing power that this core provides. The

advanced architecture also provides:

Software development on the LPDSP32 is done in C.

Neural Network Accelerator (NNA)

The Neural Network Accelerator (NNA) is a hardware

accelerator block that allows complex neural networks to

run in an energy efficient manner. The accelerator can

execute a single layer of a fully populated or sparsely

populated neural network in a single task without any

processor intervention. Layers with up to 1023 inputs and

1023 outputs are supported.

The NNA contains 16 multipliers, 16 accumulators, 16

input registers and 16 coefficient registers. It includes input

and coefficient “fetchers” that, once configured, manage the

data and coefficients memory access automatically. Support

for coefficient compression/decompression and pruning is

included and help minimize the amount of coefficient

needed.

• Two 72−bit ALUs capable of doing single and double

precision arithmetic and logical operations

• Two 32−bit integer/fractional multipliers

• Four 64−bit accumulators with 8−bit overflow

(extension bits)

The LPDSP32 relies on the CFX DSP or the Arm

Cortex−M3 processor to initialize its memories and

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13

EZAIRO 8300

Memory Structure

The following figure shows the system memory structure. The individual blocks are described in the sections that follow.

IOC0, IOC1

FIFO

Controller

A0, A1, B0 and B1 Memory (RAM)

4096 x 48−bit each

C0, C1, D0 and D1 Memory

(RAM)

Shared

Memory

Bus

4096 x 48−bit each

Shared Memory Buses (2 x 48−bit)

H0, H1, H2, H3, H4 and H5 Memory

(RAM)

Controller

1024x 48−bit each

HEAR

Configurable

Accelerator

SIN/COS Tables (ROM)

1024 x 48−bit

1536 x 48−bit (Radix−3)

Microcode Memory Buses (2 x 32−bit)

Instruction Memory Bus (32−bit)

Microcode Memory (RAM)

8192 x 32−bit

CFX Program Memory (ROM)

4096 x 32−bit

CFX Program Memory (RAM)

P Memory Bus (32−bit)

32768 x 32−bit

Filter Engine Program Memory

(RAM)

CFX DSP

Core

Filter Engine

Filter Engine P Memory Bus (36−bit)

Core

256 x 36−bit

X Memory (RAM)

65536 x 24−bit

X Memory Bus (24−bit)

Y Memory Bus (24−Bit)

Y Memory (RAM)

16384 x 24−bit

Arm Cortex−M3 Program Memory

(RAM)

Bus Bridge

(Arm Cortex−M3 System

Bus to CFX Buses)

Bus Bridge

(CFX P Bus to Arm

Cortex−M3 Buses)

Bus Bridge

(to FIFO)

DMA

98304 x 32−bit

Arm Cortex−M3 Program Memory

(ROM)

128 x 32−bit

I−Code, D−Code Buses (32−bit)

System Bus (32−bit)

Arm

Cortex−M3

Processor

Arm Cortex−M3 Data Memory

(RAM)

24576 x 32−bit

eMMC Buffer (RAM)

LPDSP32 P

Memory (RAM)

20480 x 32−bit

512 x 32−bit

A Memory

(RAM)

53240 x 32−bit

LPDSP32

Core

NNA

2 x 32−bit

B Memory

(RAM)

8192 x 32−bit

Figure 4. System Memory Architecture

FIFO Controller

The Ezairo 8300 system’s FIFO controller provides the

ability to define up to 32 FIFO buffers. These FIFOs are

defined as up to eight FIFOs in each of the A0, A1, B0 and

B1 memories.

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EZAIRO 8300

These FIFOs may be used as:

the eight FIFO interrupts that are available for the CFX

DSP, eight FIFO events that are available for the

HEAR, and eight FIFO interrupts that are available for

the Arm Cortex−M3 core.

• Input FIFOs as used by the IOC

• Output FIFOs as used by the IOC

• Intermediate FIFOs for transferring data between the

CFX, HEAR and Arm Cortex−M3 processor

• Software FIFOs for the CFX DSP or Arm Cortex−M3

processor through the use of access registers

• Each individual FIFO is associated with a set of FIFO

configuration registers that are mapped into X memory.

Each FIFO can also be associated with one or more of

Ezairo 8300 Memory Structure

• The following tables list the memory structures

attached to the CFX, the Arm Cortex−M3 Core, the

HEAR, the LPDSP32, the FENG and the eMMC

interface. They include the size and width of each

memory structure.

Table 4. CFX MEMORY INSTANCES

Memory Structure

Program memory (ROM)

Program memory (RAM)

X memory (ROM)

Data Width

Memory Instances

Memory Size

32

24

−

4096

PRAM0, PRAM1

2 x 16384 (4 x 16384) (Note 14)

−

1280

4 x 16384

8192

X memory (RAM)

Y memory (RAM)

YRAM0

YRAM1, YRAM2

2 x 4096

14.The CFX program memory can be extended by assigning the Arm Cortex−M3 processor’s program memory sections 0 and 1 to the CFX.

Table 5. Arm CORTEX−M3 CORE MEMORY STRUCTURES

Memory Structure

Program memory (ROM)

Program memory (RAM)

Data Width

Name

Memory Size

32

−

128

5 x 16384 (3 x 16384) (Note 15)

2 x 8192

CM3_PRAM0 to CM3_PRAM4

CM3_PRAM5, CM3_PRAM6

CM3_DRAM0, CM3_DRAM1

CM3_DRAM2, CM3_DRAM3

Data memory (RAM)

32

2 x 8192

2 x 4096

15.Sections 0 and 1 of the Arm Cortex−M3 processor’s program memory can be assigned to the CFX DSP.

Table 6. HEAR Memory Structures

Memory Structure

Data Width

Name

Memory Size

Microcode memory (RAM)

32

HEAR_MICROCODE_PMEM0,

HEAR_MICROCODE_PMEM1

2 x 4096

Data memory (RAM)

FiFo Memory (RAM)

Coefficient Memory (RAM)

Data ROM

48

H0, H1, H2, H3, H4, H5 memories

A0, A1, B0, B1 memories

C0, C1, D0, D1 memories

SIN/COS LUT

6 x 1024

4 x 4096

1024

SIN/COS Radix−3 LUT

1536

Table 7. LPDSP32 CORE MEMORY STRUCTURES

Memory Structure

Program memory (RAM)

Data Width

Name

Memory Size

2 x 2048

4 x 4096

2 x 8192

2 x 16384

2 x 2048

32

DSP_PRAM0, DSP_PRAM1

DSP_PRAM2 to DSP_PRAM5

DSP_ARAM0, DSP_ARAM1

DSP_ARAM2, DSP_ARAM3

DSP_ARAM4, DSP_ARAM5

DSP_BRAM0, DSP_BRAM1

DSP_BRAM2

A memory (RAM)

B Memory (RAM)

32

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EZAIRO 8300

Table 8. OTHER MEMORY STRUCTURES

Memory Structure

Data Width

Memory Size

FENG Program memory (RAM)

eMMC interface buffer (RAM)

Filter Engine State

36

32

24

28

256

512

320

64

Filter Engine Temp

Filter Engine Coefficients

320

Input/Output Controllers (IOC)

♦ A 24−bit counter

The IOCs are responsible for handling input/output audio

data. Samples can be routed along a number of different

paths using the multiplexing options available in the Ezairo

8300 system.

♦ A 3−bit prescale factor that increases by a factor of 2

at each step, scaling between a prescaler of 1 and 128.

♦ Three operating modes: single−shot/multiple−shot,

free−run, and DIO interrupt capture

♦ A dedicated interrupt that can be used to signal

timer expiration

♦ Dedicated configuration and status registers

Direct Memory Access (DMA) Controller

The direct memory access controller (DMA) module

allows background data transfers between components on

the peripheral bus and memories without any processor

intervention. This allows the processors to be used for other

computational needs while enabling high speed sustained

transfers to and from the peripherals/memories. The DMA

has 8 independent configurable channels.

Watchdog Timer

The watchdog timer is a programmable hardware timer

that operates from the system clock and is used to ensure

system sanity. It is always active and must be periodically

acknowledged as a check that an application is still running.

Once the watchdog times out, it generates an interrupt. If

left to time out a second consecutive time without

acknowledgement, a system reset will occur.

Each channel can be configured for one of four modes:

• Data transferred from peripheral−to−memory

• Data transferred from memory−to−peripheral

• Data transferred between peripherals

• Data transferred between memory locations

Interrupts

The Ezairo 8300 system contains an interrupt controller

linked to the CFX DSP. This controller services all of the

Ezairo 8300 interrupt sources, except the private peripheral

interrupts and faults of the Arm Cortex−M3 processor.

The Arm Cortex−M3 processor can be used as the master

of the Ezairo 8300 system. The Arm Cortex−M3 processor

is closely tied to a nested vectored interrupt controller

(NVIC), which is an integral part of the processor and

provides the interrupt handling functionality. The NVIC

services the private peripheral interrupts and faults of the

Arm Cortex−M3 processor and all other Ezairo 8300

interrupt sources. The LPDSP32 is linked to an interrupt

controller that services interrupts from the DMA,

inter−processor communications, and the NNA.

Algorithm and Data Security

Algorithm software code and user data that requires

permanent retention is stored off the Ezairo 8300 chip in

separate non−volatile memory. To support this, the Ezairo

8300 chip can gluelessly interface to an external SPI, DSPI

or QSPI EEPROM, Flash, or eMMC flash (referred here as

external non−volatile memory or NVM).

To prevent unauthorized access to the sensitive

intellectual property (IP) stored in the external non−volatile

memory, a comprehensive system is in place to protect

manufacturer’s application code and data.

To protect the IP stored in the external non−volatile

memory, the system supports decoding algorithm and data

sections belonging to an application that have been

encrypted using the Advanced Encryption Standard (AES)

and stored in non−volatile memory. While system access

restrictions are in place, the keys used in the decryption of

these sections will be secured from external access by the

regular access restrictions.

When the system is externally “unlocked” these keys will

be cleared, preventing their use in decoding an application

by unauthorized parties. After un−restricting access in this

way the system may then be restored by re−programming

the decryption keys.

Hear Function Chain Controller

The HEAR function chain controller responds to

commands from the CFX or from the Arm Cortex−M3

processor, and events from the FIFO controller. It must be

configured by the CFX or by the Arm Cortex−M3 processor

to enable the triggering of particular function chains within

a microcode configuration.

Input Stage

Timers

The input stage of an Ezairo 8300 provides four audio

input channels that supply signal data to the rest of the Ezairo

8300 system. Each input channel includes:

The Ezairo 8300 system provides five timers, including:

• The SysTick timer from the Arm Cortex−M3 processor

• Four general−purpose timers, each of them providing:

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EZAIRO 8300

input or output. Each GPIO pad can be configured to

generate interrupts to the CFX DSP and/or Arm Cortex−M3

processor.

• Input selection using an analog multiplexer to select

between the input source from the available input

sources and reference inputs

• Available line−out for the selected input signal

PCM Interface

• An over−sampling analog−to−digital converter (ADC)

which uses a programmable sampling frequency and

provides a configurable sampling delay, useful in

beam−forming applications.

The Ezairo 8300 system includes two highly−

configurable pulse code modulation (PCM) interfaces that

can be used to stream signal, control and configuration data

in and out of the device.

Each PCM interface connects to the processors through

the Arm Cortex−M3 processor’s peripheral bus. There are

three possible ways PCM interfaces can handle transmission

and reception buffers:

• By using the internally available data transmission and

reception interrupts.

• Selectable digital microphone inputs and bypass

registers that can source data in place of the ADCs

• High−quality decimation filtering at all selectable

sampling rates

• Selectable input muting

Each of the input channels from the Ezairo 8300 system can

optionally source their input data from a digital microphone

(DMIC input) instead of the channel’s ADC.

• By connecting to the DMA with two channels

supporting transmit and receive operations.

• By connecting to the IOC with four FIFOs supporting

transmit and receive operations. Each data channel for

PCM transmit and receive buffers requires its own

FIFO−as opposed to the case for using DMA, which

allows one DMA channel to support both channel 0 and

channel 1 for PCM.

Output Stage

The output stage of Ezairo 8300 provides two audio

output channels that post−process signal data from the rest

of the Ezairo 8300 system, and provide it to external

receivers or speakers. The output channels include:

• High−quality interpolation filtering that automatically

tracks the selected sample rate of the sigma−delta

Modulator

Each PCM interface can be configured to generate interrupts

to the CFX DSP and/or Arm Cortex−M3 processor.

SPI Interface

• An ultra−low−power, high fidelity, over−sampled

sigma−delta modulator with programmable sample rate

• A low−impedance direct digital output driver, driven by

a pulse−density modulated signal, for zero−bias hearing

aid or headset receivers

The Ezairo 8300 system includes two Serial Peripheral

Interfaces (SPIs). Each SPI interface supports single and

dual I/O modes, as well as the ability to add two additional

I/O pins in a quad I/O mode.

The SPI interfaces allow the system to communicate with

external components, including external analog front ends,

external controllers, wireless transceivers, and non−volatile

memories (NVMs).

The SPI interfaces support master/slave configuration as

well as half/full duplex mode.

Each SPI interface can be configured to generate

interrupts to the CFX DSP and/or Arm Cortex−M3

processor. Similarly, data transfers can be controlled by any

of the host processors.

• Selectable digital microphone outputs that can sink data

in parallel with either output channel

Digital Input/Output (DIO) Pads

The Ezairo 8300 system contains 36 digital input/output

(DIO) pads that can be configured:

• To support the external interfaces, output clocks, and

other I/Os

• As general−purpose I/Os (GPIO)

• Analog input/output function

The 36 DIOs are split into four power domains. The voltages

for these 4 power domains are given by the VDDO1 pad (for

DIO0 to DIO11), the VDDO2 pad (for DIO12 to DIO23),

the VDDO3 pad (for DIO24 to DIO29) and the VDDO4 pad

(for DIO30 to DIO35).

UART Interface

The general−purpose UART interface provides support

for communicating with devices that use standard UART

and RS−232 transmission protocols.

The UART Interface can be configured to generate

interrupts to the CFX DSP and/or Arm Cortex−M3

processor. Similarly, data transfers can be controlled by any

of the host processors.

The NRESET, SDA and SCL pads are on the VDDO4

power domain.

EXTERNAL INTERFACEs

Low−Speed A/D Converters (LSAD)

The purpose of the LSAD converters is to sample voltages

that typically change slowly, such as the voltage associated

with a potentiometer−based volume control.

The LSADs provide an analog to digital conversion of up

to eight signals, from a combination of four internal signals

General−Purpose Input/Output (GPIO)

Ezairo 8300 can configure any, or all, of the 36 DIO pads

as software−controlled general−purpose DIO (GPIO) pads.

The function of these GPIO pads is defined by the user

application, which can use them for any general−purpose

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EZAIRO 8300

and four external signals. The LSAD provided 14 bits of

resolution, at sampling rates up to 8 kHz.

same bus. Each debug port will respond to debug commands

on its I2C address.

The LSAD can be configured to generate interrupts to the

CFX DSP and/or Arm Cortex−M3 processor. Similarly, data

can be read by any of the host processors.

SWJ−DP Debug Port for the Arm Cortex−M3

The Ezairo 8300 system contains a standard Core Sight

SWJ−DP debug port for the Arm Cortex−M3 processor.

This debug controller is used to provide access to all of the

Arm Cortex−M3 processor registers, and to all of the Ezairo

8300 memories through the memory buses attached to the

Arm Cortex−M3 processor. By default, the SWJ−DP is

accessed using the JTAG connection that uses DIOs 30 to 33,

to form a 4−wire JTAG interface. This debug port can be

reconfigured for serial−wire mode using only DIOs 30 and

31.

I²C Interface

2

The Ezairo 8300 includes 3 instances of I C interface,

which are compatible with the Inter−IC Bus Specification

2

from NXP Semiconductors. I C interfaces are typically used

for communication with external sensors and storage

devices, and as control signals for wireless radios.

2

The I C Interface can be configured to generate interrupts

to the CFX DSP and/or Arm Cortex−M3 processor.

Similarly, data transfers can be controlled by any of the host

processors. Maximum I C SCL frequency is provided in the

The Arm Cortex−M3 processor’s SWJ−DP debug port

can be used as a bridge to the CFX I C debug port through

2

Ezairo 8300 Hardware Reference Manual.

a memory−mapped register.

I³C Interface

Standard JTAG debug port for the LPDSP32

The LPDSP32 is supported by a JTAG debug interface

that can be assigned to a set of DIO pads.

3

The Ezairo 8300 includes 2 instances of I C interface

which are compatible with the Improved Inter−IC Bus

Specification from the MIPI Alliance. The I C uses a

two−wire interface including a bidirectional clock line

3

Other Peripherals

3

(SCL) and a bidirectional data line (SDA). I C is designed

Clock−Generation Circuitry and Synchronization

The main system clock is typically generated by a

current−controlled oscillator (CCO) that can be configured

for frequencies from 1.28 MHz to 61.44 MHz. Other needed

clocks are derived from the main system clock.

An Asynchronous Sample Rate Converter (ASRC) and

Audio Sink Clock Counters blocks to provide a means of

synchronizing the audio sample rate between the radio link

and the host device.

to enhance sensor system design architectures in mobile

wireless products by providing a fast, low cost, low power,

two−wire digital interface for sensors.

3

The I C Interface can be configured to generate interrupts

to the CFX DSP and/or Arm Cortex−M3 processor.

Similarly, data transfers can be controlled by any of the host

processors.

eMMC Interface

eMMC memory (Embedded MultiMedia Card memory)

is a low−cost, high performance Flash memory that is

designed for a wide range of applications in consumer

electronics such as mobile phones, handheld computers,

navigational systems, portable gaming and even industrial

uses.

The eMMC interface of Ezairo 8300 implements the Host

Controller portion of an eMMC link and can also be used to

access SD cards.

The eMMC Interface can be configured to generate

interrupts to the CFX DSP and/or Arm Cortex−M3

processor. Similarly, data transfers can be controlled by any

of the host processors.

Power Supervisory Unit

The power supervisory unit monitors the battery supply

voltage (VBAT) and the internal analog and digital supply

voltages (VDDA, VDDC, VDDM), safely shutting down

the system without user intervention when the supply

voltages are below the thresholds required for valid system

operation.

This unit is used to ensure that the system operates

correctly and is not damaged by the power supply

fluctuations that are encountered when a battery is inserted

or removed from a hearing aid.

Power−on−Reset (POR)

The Ezairo 8300 device uses a power−on−reset (POR)

sequence to ensure proper system behavior during startup,

and to ensure proper system configuration after startup. At

the start of the POR sequence, audio output is disabled and

all configuration and control registers are asynchronously

reset to their default values.

At the start of the POR sequence, the core registers for all

five of the system’s cores are cleared and the contents of all

RAM is unspecified.

Debug Ports

I2C Debug Ports for the CFX and the Arm Cortex−M3

The I2C debug ports for the Ezairo 8300 system provide

both the CFX DSP and Arm Cortex−M3 processor with a

full debugging capacity.

The CFX DSP debug port coexists with the Arm

Cortex−M3 processor debug port on the same I2C bus. One

of the three general purpose I2C interface can be used on the

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18

EZAIRO 8300

EZAIRO 8300 PAD SPECIFICATIONS

Power

Domain

Pad Name

VBAT

Description

Battery input voltage

Type

P

Pull

Pad #, WLCSP

Pad #, BGA

VBAT

C2, D2

B2

C1

B1

A1

B3

B4

B5

A2

A3

A4

A5

E2

D1

E1

F1

D6, C7, D7

B8

VDDA

Analog power supply

VDDA

P

VDDA_C0

VDDA_C1

VREG

VMIC

Analog charge pump cap terminal 0

Analog charge pump cap terminal 1

Regulated voltage output

Microphone power supply

Analog ground

A

B9

A

A9

AO

P

B7

B6

VSSA

A8, C6

B5

GNDMIC

AI0

Input Transducer ground

ADC analog input 0

AO

AI

A7

AI1

ADC analog input 1

AI

A6

AI2

ADC analog input 2

AI

A5

AI3

ADC analog input 3

AI

A4

VDDIF

VDDIF_C0

VDDIF_C1

OD0_P

OD0_N

OD1_P

OD1_N

VBATOD

VSSOD

DIO30

DIO31

DIO32

DIO33

DIO34

DIO35

VDDO4

NRESET

SDA

Interface power supply

VDDIF

P

D8

Interface power supply cap terminal 0

Interface power supply cap terminal 1

Output Driver: Receiver Output 0 Positive

Output Driver: Receiver Output 0 Negative

Output Driver: Receiver Output 1 Positive

Output Driver: Receiver Output 1 Negative

Output driver power supply

Output driver ground

A

D9

A

C9

VBATOD

AO

P

E8

G1

H1

J1

F8

G8

H8

H2, J2

G2, K1

J4

F9 ,G9

E9, H9, J9

F6

P

Digital input / output 30

VDDO4

I/O

P

U

Digital input / output 31

K4

L4

G6

Digital input / output 32

H6

Digital input / output 33

H3

J3

E6

Digital input / output 34

F7

Digital input / output 35

K3

L3

H7

I/O domain 4 power supply

Reset pin

J6

I

U

K2

L2

G7

Debug port data

I/O

I

J7

SCL

Debug port clock

L1

J8

DIO24

DIO25

DIO26

DIO27

DIO28

DIO29

VDDO3

Digital input / output 24

VDDO3

I/O

P

K7

L7

H3

Digital input / output 25

J3

Digital input / output 26

J6

G3

Digital input / output 27

K6

J5

J4

Digital input / output 28

G5

Digital input / output 29

K5

L5

H4

I/O domain 3 power supply

J5

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19

EZAIRO 8300

EZAIRO 8300 PAD SPECIFICATIONS

Power

Domain

Pad Name

DIO12

DIO13

DIO14

DIO15

DIO16

DIO17

DIO18

DIO19

DIO20

DIO21

DIO22

DIO23

VDDO2

VDDM

DIO0

Description

Digital input / output 12

Type

I/O

P

Pull

U

Pad #, WLCSP

Pad #, BGA

D4

E2

VDDO2

F8

Digital input / output 13

Digital input / output 14

Digital input / output 15

Digital input / output 16

Digital input / output 17

Digital input / output 18

Digital input / output 19

Digital input / output 20

Digital input / output 21

Digital input / output 22

Digital input / output 23

I/O domain 2 power supply

Memory power supply

Digital input / output 0

Digital input / output 1

Digital input / output 2

Digital input / output 3

Digital input / output 4

Digital input / output 5

Digital input / output 6

Digital input / output 7

Digital input / output 8

Digital input / output 9

Digital input / output 10

Digital input / output 11

I/O domain 1 power supply

RESERVED

U

G8

U

G9

F2

U

H7

F4

U

H8

F3

U

H9

F1

U

J7

G4

G2

H2

H1

J2

U

J8

U

K8

U

K9

U

L8

U

L9

J1

J9

G1

E1

NA

P

F9

VDDO1

I/O

P

U

A7

B3

DIO1

A8

A2

DIO2

A9

A1

DIO3

B7

C5

B2

DIO4

B8

DIO5

C7

C4

C3

C2

D5

D3

C1

D2

B1

DIO6

C8

DIO7

C9

DIO8

D7

DIO9

D8

DIO10

DIO11

VDDO1

RESERVED

VDDC

VSSO

VSSC

D9

E8

B9

B6

I

D

B4

Digital core power supply

IO Ground

NA

P

E9

D1

P

A6, G6, F7, L6

E5, F2, F3, F4

A3, C8, E3, E7,

H5

Digital Core Ground

P

NOTES: Legend:

Type: A=analog; D=digital; I=input; O=output; P=power

Active: H=active high; L=active low

Pull: U=pull up; D=pull down

All digital pads have a Schmitt trigger input

SCL, SDA and all DIO pads have a programmable I2C low pass filter

VSSO is the ground of all four IO power domains

Center WLCSP ground bumps (E5, F3, F4, F7, G6) are optional to be connected

Dummy balls on the WLCSP package (C5, D5, E4, E6, F5, F6, G4, G5, H5) can be left floating or can be connected to VSSC or

VSSO.

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20

EZAIRO 8300

Ezairo 8300 DIO Assignment

Some of the DIOs of Ezairo 8300 have a default assignment to a given interface, as shown in the table below.

DIOs: DEFAULT ASSIGNMENT

VDDO1

VDDO2

VDDO3

VDDO4

DIO0: SPI_CLK; EMMC_CLK

DIO1: SPI_CS; EMMC_CMD

DIO2: SPI_IO0; EMMC_DATA0

DIO3: SPI_IO1

DIO12: Unassigned

DIO13: Unassigned

DIO14: Unassigned

DIO15: Unassigned

DIO16: Unassigned

DIO17: Unassigned

DIO18: Unassigned

DIO19: Unassigned

DIO20: Unassigned (*)

DIO21: Unassigned (*)

DIO22: Unassigned (*)

DIO23: Unassigned (*)

DIO24: Unassigned

DIO25: Unassigned

DIO26: Unassigned

DIO27: Unassigned

DIO28: Unassigned

DIO29: Unassigned

DIO30: SW_TCK (**)

DIO31: SW_TMS (**)

DIO32: JTDI (**)

DIO33: JTDO (**)

DIO4: Unassigned

DIO34: Unassigned

DIO35: Unassigned (***)

DIO5: Unassigned

DIO6: Unassigned

DIO7: Unassigned

DIO8: Unassigned (*)

DIO9: Unassigned (*)

DIO10: Unassigned (*)

DIO11: Unassigned (*)

*LSAD capability: this functionality is not available on other DIOs.

**SWJ−DP capability: this functionality is not available on other DIOs.

***EXTCLK capability: this functionality is not available on other DIOs.

Ezairo 8300 Passive Components

The following 7 capacitors are mandatory:

MANDATORY CAPACITORS

Cap (VBAT − VSSC)

Cap (VBATOD − VSSC)

Cap (VDDC − VSSC)

Cap (VDDM − VSSC)

Cap (VDDA − VSSA)

VBAT decoupling

VBATOD decoupling

VDDC decoupling

VDDM decoupling

VDDA decoupling

Analog charge pump

VREG decoupling

1 mF

4.7 mF

20%

100 nF

2.2 mF

Cap (VDDA_C0 − VDDA_C1)

Cap (VREG − VSSA)

100 nF (Note 16)

1 mF

16.The startup current limit can be increased with a higher capacitor value. Recommended maximum value is 470 nF.

Depending on the amount of current and the current

profile needed by an external IC, VDDA can be used to

supply this IC, and VDDIF is not needed. This will be the

case for an external device that requires a low and constant

current to operate.

Some use cases will require the usage of VDDIF, for

example when a radio system is used. When VDDIF is used,

the following 2 capacitors are needed:

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21

EZAIRO 8300

VDDIF CAPACITORS

Cap (VDDIF_C0- VDDIF_C1)

Cap (VDDIF–VSSO)

Interfaces charge pump

VDDIF decoupling

0.47 mF

2.2 mF

20%

Special care is needed at the system level to avoid audio

artefacts.

of which are already decoupled). This adds up to 4 optional

capacitors:

The VDDO supplies need decoupling capacitors if the

supplies are not derived from VBAT, VDDA, or VDDIF (all

VDDOX CAPACITORS

Cap (VDDO1−VSSO)

Cap (VDDO2− VSSO)

Cap (VDDO3− VSSO)

Cap (VDDO4− VSSO)

VDDO1 decoupling

VDDO2 decoupling

VDDO3 decoupling

VDDO4 decoupling

2.2 mF

20%

A cap on VMIC will be used if the VMIC regulator is used:

Cap (VMIC−VSSA)

VMIC decoupling

1 mF

20%

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22

EZAIRO 8300

VMIC

AI0

OD0_P

OD0_N

Speaker/Receiver

MIC 1

AI1

MIC 2

GNDMIC

Charger

supply

Ezairo 8300

Battery Pack

PACK+

VDDP

Debug/Fitting

Connector

DIO24

DIO25

DIO26

DIO27

SWOUT¹

WARN

CLK

DS_EN

VHA

SWIN

SDA

SCL

VBAT

VSSO

HPM10

R⁴

T²

VBAT

CVBAT

VBATOD

VDDO4

VDDO3

VDDO2

VDDO1

C⁴

VSS_GND

CHA

CVBAT

Ezairo

VSSOD

VDDIF³

VBAT

DIO0

PACK-

DIO12

DIO13

DIO14

DIO15

DIO16

DIO17

DIO18

DIO19

DIO1

VDD

DIO2

SCK

CS

SI

DIO0

DIO1

DIO3

RSL10

DIO3

DIO9

DIO10

DIO11

DIO12

DIO13

DIO14

LE25S161

SO

DIO4

DIO20

DIO21

DIO22

DIO23

VSS_GND

RES

NRESET

VDDO2

VDDO1

VSS GND

VSS_GND

Notes:

1. SWIN, SWOUT, WARN and CLK are optional (design dependant)

2. The Thermistor in the battery pack may be connected to a LSAD input of the Ezairo 8300 SL for A/D conversion using the volt-

age divider.

3. If any of the VDDO* domains on Ezairo 8300 are not referenced to VDDIF or VBAT, they require a 2.2 uF decoupling capacitor.

4. Recommended component values for the RC filter and required DIO configuration:

a. R = 3K9 ohm, 1%; C = 0.56 uF, 10%

b. RC filter should be driven by a VBAT DIO from Ezairo with strong pull up, i.e. 1 Kohm

5. CHA is the decoupling capacitor for VHA and should be placed next to the VHA pad.

6. CVBAT is the decoupling capacitor for the battery and its value should always be 5*(CHA+CVBAT Ezairo)

7. Details of the capacitor selection for CHA and other capacitors not shown on this diagram for HPM10 can be found in «External

Components» Section of the HPM10 datasheet

8. Details of the decoupling capacitor selection for Ezairo can be found at section «Ezairo 8300 Passive Components»

9. Please contact ON Semiconductor for a review of your schematics.

Figure 5. Ezairo 8300 Application Diagram

www.onsemi.com

23

EZAIRO 8300

BUMP AND COATING SPECIFICATIONS

Subject

Specification

Bump metallization

SnAg (Ag = 1.8%)

Backside coating specification

Backside coating thickness

Lintec Adwill 2850

25 mm

Chip Identification

The Ezairo 8300 VFBGA package is constructed with all

RoHS compliant material and should be reflowed

accordingly.

System identification is used to identify different system

components. For the Ezairo 8300 chip, the key identifier

components and values are as follows:

• Chip Family: 0x0A

• Chip Version: 0x01

• Chip Revision: 0x0101

The WLCSP version is Moisture Sensitive Class MSL1

and the VFBGA version has been classified as Moisture

Sensitive Class MSL3 according to IPC/JEDEC standard

J−STD−020E, Joint Industry Standard: Re−flow Sensitivity

Classification for Nonhermetic Solid State Surface Mount

Devices. Handle parts according to J−STD−033D, Joint

Industry Standard: Handling, Packing, Shipping and Use of

Moisture, Reflow and Process Sensitive Devices. Hand

soldering is not recommended for this part.

For additional information on our Pb−free strategy and

soldering details, please download the ON Semiconductor

Soldering and Mounting Techniques Reference Manual,

SOLDERRM/D.

Electrostatic Discharge (ESD) Sensitive Device

CAUTION: ESD sensitive device. Permanent damage

may occur on devices subjected to high−energy electrostatic

discharges. Proper ESD precautions in handling, packaging

and testing are recommended to avoid performance

degradation or loss of functionality.

Inspection Criteria

MIL−STD−883 Method 2010 is followed.

Company or Product Inquiries

Solder Information

For more information about ON Semiconductor products

or services visit our Web site at http://onsemi.com.

For sales or technical support, contact your local

representative or authorized distributor.

The Ezairo 8300 chip, WLCSP version, is delivered

solder bumped, constructed with all RoHS compliant

material and should be reflowed accordingly.

Ezairo is registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

Arm and Cortex are registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

www.onsemi.com

24

EZAIRO 8300

PACKAGE DIMENSIONS

WLCSP87 2.643x3.053x0.354

CASE 567ZN

ISSUE B

www.onsemi.com

25

EZAIRO 8300

PACKAGE DIMENSIONS

VFBGA78 5x5

CASE 138AW

ISSUE B

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

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◊

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26

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