PX3519
Theory of operation
5
Theory of operation
The PX3519 functionality is enabled by the EN pin. When the EN pin voltage overcomes the rising voltage
threshold of the UVLO the driver begins to operate depending on the PWM status and the VCC pin status (VCC
has to be higher then the rising threshold voltage). For VCC is recommended to have a slope for the rising edge
higher than 5V/100ms around the rising UVLO threshold.
The VCC can range between 4.5V and 8V and it is the supply pin for both driver and logic sections.
The PX3519 functionality is driven by the PWM signal transitions. When the PWM signal performs a transition
between low state to high state (PWM voltage higher than 2.5V) the Low Side MOSFET is turned off, after the
turn off delay propagation time. Then the High Side MOSFET is turned on, after the turn on propagation delay
time. Once the on time is expired the PWM signal provides a transition between the high state to the low state
(PWM voltage lower than 0.8V). This will drive the High Side MOSFET from the ON state to the OFF state, after
the turn off propagation delay time. The PX3519 is also capable to drive the two external MOSFETs both in off
state. When the PWM signal enters in the shut down window or tri-state (typically between 1.2V and 2.0V) after
the shut down hold off time both MOSFETs are switched off. This feature is useful when the IC controller wants
to reduce the number of active phases in order to reduce the power consumption. In principle the tri-state status
can be used also to improve the transition between high loads to low load.
The PX3519 implements an embedded resistor network, which forces the PWM pin of the device in the middle
of the shut down window if the PWM input from the controller is floating.
In order to avoid cross conduction between the High Side MOSFET and the Low Side MOSFET an anti-shoot-
through control is implemented with the adaptive scheme. The adaptive scheme is implemented in order to use
a variety of different power MOSFETs for different kind of conversion. Nevertheless the dead time is kept as
short as possible in order to increase the efficiency of the overall solution.
The driver includes gate drive functionality to protect against shoot through. In order to protect the power stage
from overlap, both High Side and Low Side MOSFETs being on at the same time, the adaptive control circuitry
monitors the voltage at the “PHASE” pin. When the PWM signal goes low, the High Side MOSFET will begin to
turn off. Once the “PHASE” pin falls below 1V, the Low Side MOSFET is gated on. Additionally, the gate to
source voltage of the High Side MOSFET is also monitored. When VGS (High Side) is discharged below 1V, a
threshold known to turn the High Side MOSFET off, a secondary delay is initiated, which results in the Low Side
being gated “ON” regardless of the state of the “PHASE” pin. This way it will be ensured that the converter can
sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle.
During the start up depending on several factors it can be that the power input for the conversion (input rail)
rises before the VCC input. In this case it could happen that the high side has an induced turn on. In order to
avoid this undesirable effect the PX3519 embeds a resistance of 10 kOhm between UGATE pin and PHASE
pin.
In order to reduce the sensitivity to issues generated during the power on sequence (like the induced turn on of
the high side MOSFET) and to reduce further the power consumption an EN pin is implemented; in this case the
designer has the possibility to create a short delay time between the VCC and the EN pin voltage to ensure the
proper functionality. Moreover the EN pin can be used to disable the driver stage in case a very low
consumption is required.
5.1
Driver characteristics
The gate driver of the PX3519 has one supply voltage to simplify the layout of the system.The VCC pin is used
to power the section related to the logic for detecting the status of PWM pin and EN pin. The VCC pin is used
also to supply the power section related to the driver of the power mosfet.
The MOSFETs selected for this application are optimized for 5V gate drive, thus giving the end user optimized
high load as well as light load efficiency. Nevertheless the driving voltage can be increased up to 8V in order to
have a customized efficiency curve depending on the application conditions. The reference for the power
circuitry including the driver output stage and the reference for the gate driver control circuit is GND.
Proper response of the driver to the PWM signal is only guaranteed when UVLO have been cleared by the
respective supply voltages (ref to table 8). Therefore, it is strongly recommended to only issue pulses to PWM
when no UVLO conditions are present. The power down sequence should set PWM to HiZ with respect the
internal threshold, before ramping down VIN (see figure 6 for VIN connection), PVCC and VCC respectively.
Datasheet
13
Revision 2.3, 2015-10-21
