5P49V5908_17,PDF,5P49V5908_17 PDF资料,Datasheet,下载5P49V5908

Programmable Clock Generator

5P49V5908

DATASHEET

Description

Features

The 5P49V5908 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

• Generates up to four independent output frequencies with a

total of 11 differential outputs and one reference output

• Supports multiple differential output I/O standards:

– Three universal outputs pairs with each configurable

as one differential output pair (LVDS, LVPECL or

regular HCSL) or two LVCMOS outputs. Frequency

of each output pair can be individually programmed

2

Programmable (OTP) memory or changed using I C

interface. This is IDTs fifth generation of programmable clock

®

technology (VersaClock 5).

The frequencies are generated from a single reference clock

or crystal. Two select pins allow up to 4 different

– Eight copies of Low Power HCSL(LP-HCSL) outputs.

Programmable frequency

configurations to be programmed and accessible using

processor GPIOs or bootstrapping. The different selections

may be used for different operating modes (full function,

partial function, partial power-down), regional standards (US,

Japan, Europe) or system production margin testing.

– See Output Features and Descriptions for details

• One reference LVCMOS output clock

• High performance, low phase noise PLL, < 0.7 ps RMS

typical phase jitter on outputs:

2

The device may be configured to use one of two I C

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

addresses to allow multiple devices to be used in a system.

Pin Assignment

• Four fractional output dividers (FODs)

• Independent Spread Spectrum capability from each

fractional output divider (FOD)

• Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

2

• I C serial programming interface

• Input frequency ranges:

48 47 46 45 44 43

42 41 40 39 38 37

1

2

V_DDO2

36

35

34

33

32

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz

to 200MHz

OUT10B

OUT2

XOUT

XIN/REF

V_DDA

OUT2B

3

4

– Crystal frequency range: 8MHz to 40MHz

OEB_{7_10}

NC

• Output frequency ranges:

5

6

7

V_DDO

– LVCMOS Clock Outputs – 1MHz to 200MHz

31

30

V_DD

V_{DD_CORE}

OUT9

OUT9B

EPAD

– LP-HCSL Clock Outputs – 1MHz to 200MHz

29

28

27

26

OUT3

OUT3B

V_DDO

NC

OUT8

OUT8B

OUT7

8

9

– Other Differential Clock Outputs – 1MHz to 350MHz

• Programmable loop bandwidth

• Programmable crystal load capacitance

• Power-down mode

• Mixed voltage operation:

– 1.8V core

10

11

12

OUT7B

SD/OE

25

NC

14

19 20

21 22 23 24

15 16 17 18

13

– 1.8V VDDO for 8 LP-HCSL outputs

– 1.8V to 3.3V VDDO for other outputs

(3 programmable differential outputs and 1 reference

output)

48-pin VFQFPN

– See Pin Descriptions for details

• Available in 48-pin VFQFPN package (NDG48)

• -40° to +85°C industrial temperature operation

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5P49V5908 DATASHEET

Functional Block Diagram

V_DDO

OUT0_SEL_I2CB

_DDO1

0

XIN/REF

XOUT

V

OUT1

SD/OE

FOD1

FOD2

FOD3

OUT1B

SEL1/SDA

V

_DDO2

OTP

and

Control Logic

OUT2

SEL0/SCL

OUT2B

OEB_3,11

PLL

V_DDA

V_DDO

OUT3, 5, 6, 11

OE_buffer

OEB_{7_10}

V_DD

OUT7 - 10

V_{DD_CORE}

V_DDO

4

OUT4

FOD4

OUT4B

Typical Applications

• Ethernet switch/router

• PCI Express 1.0/2.0/3.0

• Broadcast video/audio timing

• Multi-function printer

• Processor and FPGA clocking

• Any-frequency clock conversion

• MSAN/DSLAM/PON

• Fiber Channel, SAN

• Telecom line cards

• 1 GbE and 10 GbE

PROGRAMMABLE CLOCK GENERATOR

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Table 1:Pin Descriptions

Number

Name

OUT10B

XOUT

Type

Description

1

2

3

Output

Input

Complementary output clock 10. Low-Power HCSL (LP-HCSL) output.

Crystal oscillator interface output.

XIN/REF

Input

Crystal oscillator interface input, or single-ended LVCMOS clock input. Ensure that the

input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF Interface”.

Analog functions power supply pin. Connect to 1.8V.

4

5

VDDA

VDDO

OUT9

Power

Output

Input

Connect to 1.8V. Power pin for outputs 3, 5-11.

6

Output clock 9. Low-Power HCSL (LP-HCSL) output.

7

OUT9B

OUT8

Complementary output clock 9. Low-Power HCSL (LP-HCSL) output.

Output clock 8. Low-Power HCSL (LP-HCSL) output.

8

9

OUT8B

OUT7

Complementary output clock 8. Low-Power HCSL (LP-HCSL) output.

Output clock 7. Low-Power HCSL (LP-HCSL) output.

10

11

12

OUT7B

SD/OE

Complementary output clock 7. Low-Power HCSL (LP-HCSL) output.

Internal Pull- Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit controls the

down

configuration of the SD/OE pin. The SH bit needs to be high for SD/OE pin to be configured

as SD. The SP bit (0x02) controls the polarity of the signal to be either active HIGH or LOW

only when pin is configured as OE (Default is active LOW.) Weak internal pull down resistor.

When configured as SD, device is shut down, differential outputs are driven high/low, and the

single-ended LVCMOS outputs are driven low. When configured as OE, and outputs are

disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the

programming bits as shown in the SD/OE Pin Function Truth table.

13

14

SEL1/SDA

SEL0/SCL

Input

Internal Pull- Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak internal

down pull down resistor.

Internal Pull- Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak internal

down

pull down resistor.

Connect to 1.8V.

15

16

17

18

19

20

21

22

23

24

VDD

VDDO

OUT6

Power

Output

Power

Output

Input

Connect to 1.8V. Power pin for outputs 3, 5-11.

Output Clock 6. Low-Power HCSL (LP-HCSL) output.

OUT6B

OUT5

Complementary Output Clock 6. Low-Power HCSL (LP-HCSL) output.

Output Clock 5. Low-Power HCSL (LP-HCSL) output.

OUT5B

VDDO4

OUT4

Complementary output clock 5. Low-Power HCSL (LP-HCSL) output.

Connect to 1.8V to 3.3V. VDD supply for OUT4.

Output clock 4. Please refer to the Output Drivers section for more details.

Complementary output clock 4. Please refer to the Output Drivers section for more details.

OUT4B

Internal Pull- Active low Output Enable pin for Outputs 3, 5, 6, 11.

OEB_3,11

down

1 = disable outputs, 0 = enable outputs. This pin has internal pull-down.

Do not connect.

25

26

27

28

29

30

31

32

33

NC

Input

—

Do not connect.

VDDO

OUT3B

OUT3

VDD_Core

VDD

Power

Output

Power

Input

Connect to 1.8V. Power pin for outputs 3, 5-11.

Complementary output Clock 3. Low-Power HCSL (LP-HCSL) output.

Output clock 3. Low-Power HCSL (LP-HCSL) output.

Connect to 1.8V.

NC

Do not connect.

Input

Internal Pull- Active low Output Enable pin for Outputs 7-10.

OEB_{7_10}

down

1 = disable outputs, 0 = enable outputs. This pin has internal pull-down.

34

35

36

37

OUT2B

OUT2

Output

Power

Output

Complementary output clock 2. Please refer to the Output Drivers section for more details.

Output clock 2. Please refer to the Output Drivers section for more details.

Connect to 1.8V to 3.3V. VDD supply for OUT2

VDDO2

OUT1B

Complementary output clock 1. Please refer to the Output Drivers section for more details.

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5P49V5908 DATASHEET

Pin Descriptions (cont.)

Number

Name

Type

Description

38

OUT1

Output

Power

Input

Output clock 1. Please refer to the Output Drivers section for more details.

Connect to 1.8V to 3.3V. VDD supply for OUT1

Do not connect.

39

VDDO1

NC

40

—

41

OUT11

OUT11B

VDDO

VDD

Output

Power

Input

Output clock 11. Low-Power HCSL(LP-HCSL) output.

Complementary output clock 11. Low-Power HCSL(LP-HCSL) output.

Connect to 1.8V. Power pin for outputs 3, 5-11

Connect to 1.8V

42

43

44

45

OE_buffer

Internal Pull- Active High Output enable for outputs 3, 5-11.

up

0 = disable outputs, 1=enable outputs. This pin has internal pull-up.

46

47

VDDO0

Power

Output

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage levels

for OUT0.

Internal Pull- Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB

down

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 13

and 14. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 13 and

14 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull

down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 13 and

14 will act as the SDA and SCL pins of an I2C interface. After power up, the pin

acts as a LVCMOS reference output.

48

OUT10

GND

Output

GND

Output clock 10. Low-Power HCSL (LP-HCSL) output.

EPAD

Connect to ground pad.

Table 3: Configuration Table

PLL Features and Descriptions

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5908 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5908 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output divider and any spread amount from

±0.25% to ±2.5% center spread and -0.5% to -5% down

spread.

programmed.

2

OUT0_SEL_I2CB SEL1 SEL0

@ POR

I C

REG0:7 Config

Access

1

0

1

X

0

1

0

1

X

No

0

1

0

1

2

3

No

Yes

I2C

defaults

Table 2: Loop Filter

0

X

Yes

0

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDA power supply so that they ramp with that

supply or are tied low (this is the same as floating the pins).

This will cause the register configuration to be loaded that is

selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10ms of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDA. The

SELx pins must be driven with a digital signal of < 300ns

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

Input Reference

Loop

Frequency–Fref BandwidthMin Bandwidth Max

(MHz)

5

(kHz)

40

(kHz)

126

350

300

1000

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

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You can write the following equations for the total capacitance

at each crystal pin:

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

C

= Ci + Cs + Ce

1 1 1

XIN

= Ci + Cs + Ce

XOUT

2

A crystal manufacturer will calibrate its crystals to the nominal

frequency with a certain load capacitance value. When the

oscillator load capacitance matches the crystal load

capacitance, the oscillation frequency will be accurate. When

the oscillator load capacitance is lower than the crystal load

capacitance, the oscillation frequency will be higher than

nominal and vice versa so for an accurate oscillation

frequency you need to make sure to match the oscillator load

capacitance with the crystal load capacitance.

Ci and Ci are the internal, tunable capacitors. Cs and Cs

2

are stray capacitances at each crystal pin and typical values

are between 1pF and 3pF.

1

2

1

Ce and Ce are additional external capacitors that can be

1

2

added to increase the crystal load capacitance beyond the

tuning range of the internal capacitors. However, increasing

the load capacitance reduces the oscillator gain so please

consult the factory when adding Ce and/or Ce to avoid

1

2

crystal startup issues. Ce and Ce can also be used to adjust

for unpredictable stray capacitance in the PCB.

To set the oscillator load capacitance there are two tuning

capacitors in the IC, one at XIN and one at XOUT. They can

be adjusted independently but commonly the same value is

used for both capacitors. The value of each capacitor is

composed of a fixed capacitance amount plus a variable

capacitance amount set with the XTAL[5:0] register.

Adjustment of the crystal tuning capacitors allows for

maximum flexibility to accommodate crystals from various

manufacturers. The range of tuning capacitor values available

are in accordance with the following table.

1

2

The final load capacitance of the crystal:

CL = C

× C

/ (C

+ C

)

XIN

XOUT

XIN

XOUT

For most cases it is recommended to set the value for

capacitors the same at each crystal pin:

C

= C

= Cx → CL = Cx / 2

XIN

XOUT

The complete formula when the capacitance at both crystal

pins is the same:

XTAL[5:0] Tuning Capacitor Characteristics

CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2

Parameter

Bits

Step (pF)

Min (pF)

Max (pF)

Example 1: The crystal load capacitance is specified as 8pF

and the stray capacitance at each crystal pin is Cs=1.5pF.

Assuming equal capacitance value at XIN and XOUT, the

equation is as follows:

XTAL

6

0.5

9

25

The capacitance at each crystal pin inside the chip starts at

9pF with setting 000000b and can be increased up to 25pF

with setting 111111b. The step per bit is 0.5pF.

8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2 →

0.5pF × XTAL[5:0] = 5.5pF → XTAL[5:0] = 11 (decimal)

You can write the following equation for this capacitance:

Ci = 9pF + 0.5pF × XTAL[5:0]

Example 2: The crystal load capacitance is specified as 12pF

and the stray capacitance Cs is unknown. Footprints for

external capacitors Ce are added and a worst case Cs of 5pF

is used. For now we use Cs + Ce = 5pF and the right value for

Ce can be determined later to make 5pF together with Cs.

The PCB where the IC and the crystal will be assembled adds

some stray capacitance to each crystal pin and more

capacitance can be added to each crystal pin with additional

external capacitors.

12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2 →

XTAL[5:0] = 20 (decimal)

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5P49V5908 DATASHEET

OTP Interface

Table 4: SD/OE Pin Function Truth Table

The 5P49V5908 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

SH bit SP bit OSn bit OEn bit SD/OE

OUTn

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

0

1

0

1

x

0

1

x

0

1

Tri-state²

Output active

Output driven High Low

Output active

2

To initiate a save or restore using I C, only two bytes are

transferred. The device address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5908 will

not generate Acknowledge bits. The 5P49V5908 will

1

0

1

x

0

1

0

Tri-state²

Output active

1

0

1

x

0

1

0

Tri-state²

acknowledge the instructions after it has completed execution

Output active

Output driven High Low

Output driven High Low ¹

2

of them. During that time, the I C bus should be interpreted as

busy by all other users of the bus.

1

x

1

On power-up of the 5P49V5908, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5908 will be ready to

accept a programming instruction once it acknowledges its

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

2

7-bit I C address.

Output Alignment

2

Availability of primary and secondary I C addresses to allow

Each output divider block has a synchronizing POR pulse to

provide startup alignment between outputs. This allows

alignment of outputs for low skew performance. The phase

alignment works both for integer output divider values and for

fractional output divider values.

2

programming for multiple devices in a system. The I C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

2

Programming Guide provides detailed I C programming

guidelines and register map.

Besides the POR at power up, the same synchronization reset

is also triggered when switching between configurations with

the SEL0/1 pins. This ensures that the outputs remain aligned

in every configuration. This reset causes the outputs to

suspend for a few hundred microseconds so the switchover is

not glitch-less. The reset can be disabled for applications

where glitch-less switch over is required and alignment is not

critical.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

2

When using I C to reprogram an output divider during

operation, alignment can be lost. Alignment can be restored

2

by manually triggering the reset through I C.

When alignment is required for outputs with different

SP

OUTn

frequencies, the outputs are actually aligned on the falling

edges of each output by default. Rising edge alignment can

also be achieved by utilizing the programmable skew feature

to delay the faster clock by 180 degrees. The programmable

skew feature also allows for fine tuning of the alignment.

SD/OE Input

OEn

Global Shutdown

OSn

SH

For details of register programming, please see VersaClock 5

Family Register Descriptions and Programming Guide for

details.

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

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Output Divides

Device Start-up & Reset Behavior

Each of the four output divides are comprised of a 12-bit

integer counter, and a 24-bit fractional counter. The output

divide can operate in integer divide only mode for improved

performance, or utilize the fractional counters to generate any

frequency with a synthesis accuracy better than 50ppb.

The 5P49V5908 has an internal power-up reset (POR) circuit.

The POR circuit will remain active for a maximum of 10ms

after device power-up.

Upon internal POR circuit expiring, the device will exit reset

and begin self-configuration.

The Output Divide also has the capability to apply a spread

modulation to the output frequency. Independent of output

frequency, a triangle wave modulation between 30 and 63kHz

may be generated.

The device will load internal registers using the configuration

stored in the internal One-Time Programmable (OTP)

memory.

Output Skew

Once the full configuration has been loaded, the device will

respond to accesses on the serial port and will attempt to lock

the PLL to the selected source and begin operation.

For outputs that share a common output divide value, there

will be the ability to skew outputs by quadrature values to

minimize interaction on the PCB. The skew on each output

can be adjusted from 0 to 360 degrees. Skew is adjusted in

units equal to 1/32 of the VCO period. So, for 100 MHz output

and a 2800 MHz VCO, you can select how many 11.161ps

units you want added to your skew (resulting in units of 0.402

degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so

on. The granularity of the skew adjustment is always

Power Up Ramp Sequence

VDDA and VDD must ramp up together. VDD0-2, VDDO4,

VDD_CORE and VDDO must ramp up before, or concurrently

with, VDDA and VDD. All power supply pins must be

connected to a power rail even if the output is unused. All

power supplies must ramp in a linear fashion and ramp

monotonically.

dependent on the VCO period and the output period.

Output Drivers

VDDO0-2, VDDO4,

The OUT1 to OUT4 clock outputs are provided with

register-controlled output drivers. By selecting the output drive

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

VDD_CORE and VDDO

The operating voltage ranges of each output is determined by

its independent output power pin (V

) and thus each can

VDD

VDDA

DDO

have different output voltage levels. Output voltage levels of

2.5V or 3.3V are supported for differential HCSL, LVPECL

operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS

and differential LVDS operation.

Each output may be enabled or disabled by register bits.

When disabled an output will be in a logic 0 state as

determined by the programming bit table shown on page 6.

LVCMOS Operation

When a given output is configured to provide LVCMOS levels,

then both the OUTx and OUTxB outputs will toggle at the

selected output frequency. All the previously described

configuration and control apply equally to both outputs.

Frequency, phase alignment, voltage levels and enable /

disable status apply to both the OUTx and OUTxB pins. The

OUTx and OUTxB outputs can be selected to be

phase-aligned with each other or inverted relative to one

another by register programming bits. Selection of

phase-alignment may have negative effects on the phase

noise performance of any part of the device due to increased

simultaneous switching noise within the device.

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2

I C Mode Operation

2

The device acts as a slave device on the I C bus using one of

2

the two I C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

2

For full electrical I C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

Abar

A

P

Sequential Read

S

Dev Addr + W

Reg start Addr

A

Sr

Dev Addr + R

A

Data 1

A

Data n

Abar

P

Sequential Write

S

Dev Addr + W

Data 0

A

Data 1

A

Data n

A

P

S = start

from master to slave

from slave to master

Sr = repeated start

A = acknowledge

Abar= none acknowledge

P = stop

I²C Slave Read and Write Cycle Sequencing

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Table 5: I²C Bus DC Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

For SEL1/SDA pin

and SEL0/SCL pin.

For SEL1/SDA pin

and SEL0/SCL pin.

5.5 ²

V_IH

Input HIGH Level

Input LOW Level

0.7xVDDD

V

V_IL

GND-0.3

0.3xVDDD

V

V_HYS

I_IN

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

0.05xVDDD

-1

V

µA

V

30

V_OL

I_OL= 3 mA

0.4

Table 6: I²C Bus AC Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

F_SCLK

Serial Clock Frequency (SCL)

10

400

kHz

µs

ns

µs

pF

ns

µs

t_BUF

Bus free time between STOP and START

1.3

0.6

100

0

t_SU:STARTSetup Time, START

t_HD:STARTHold Time, START

t_SU:DATA

t_HD:DATA

t_OVD

Setup Time, data input (SDA)

Hold Time, data input (SDA) ¹

Output data valid from clock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

0.9

400

300

C_B

t_R

20 + 0.1xC_B

t_F

20 + 0.1xC_B

t_HIGH

t_LOW

0.6

1.3

0.6

LOW Time, clock (SCL)

t_SU:STOP

Setup Time, STOP

Note 1: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V (MIN) of the SCL signal) to bridge the undefined region of the falling edge

IH

of SCL.

Note 2; I2C inputs are 5V tolerant.

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Table 7: Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P49V5908. These ratings, which are standard

values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other

conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the

recommended operating temperature range.

Item

Rating

Supply Voltage, V_DDA, V_DDD, V_DDO

3.465V

Inputs

XIN/REF

0V to 1.2V voltage swing

-0.5V to VDDO+ 0.5V

10mA

Outputs, V_DDO(LVCMOS)

Outputs, I_O(SDA)

Package Thermal Impedance,

Storage Temperature, T_STG

ESD Human Body Model

Junction Temperature

42°C/W (0 mps)

41.8°C/W (0 mps)

-65°C to 150°C

2000V

Θ_JA

Θ_JC

125°C

Table 8: Recommended Operation Conditions

Symbol

Parameter

Min

Typ

Max

Unit

V_DDx

Power supply voltage for supporting 1.8V outputs

Analog power supply voltage. Use filtered analog power

supply if available.

1.71

1.8

1.89

V

V_DDA

1.71

-40

1.89

V

T_A

C_{LOAD_OUT}

F_IN

Operating temperature, ambient

85

15

40

°C

pF

Maximum load capacitance (3.3V LVCMOS only)

External reference crystal

8

MHz

Power up time for all VDDs to reach minimum specified

voltage (power ramps must be monotonic)

t_PU

0.05

5

ms

Table 9: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down

Resistance ^(T= +25 °C)

A

Symbol

Parameter

Min

Typ

Max

7

Unit

pF

Input Capacitance (SD/OE, SEL1/SDA, SEL0/SCL)

CIN

3

Pull-down Resistor

100

300

kΩ

LVCMOS Output Driver Impedance (VDDO = 1.8V, 2.5V, 3.3V)

Programmable capacitance at XIN/REF

ROUT

17

Ω

XIN/REF

XOUT

9

25

pF

Programmable capacitance at XOUT

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Table 10:Crystal Characteristics

Parameter

Mode of Oscillation

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

Test Conditions

Minimum

Typical Maximum

Fundamental

25

Units

8

40

100

7

MHz

Ω

pF

10

Load Capacitance (CL) @ <=25 MHz

Load Capacitance (CL) >25M to 40M

Maximum Crystal Drive Level

6

8

12

8

100

pF

µW

Note: Typical crystal used is FOX 603-25-150. For different reference crystal options please go to www.foxonline.com.

Table 11: DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

100 MHz on all outputs, 25 MHz

REFCLK

Iddcore³

Core Supply Current

44

42

37

18

17

16

29

28

16

14

12

36

27

16

10

mA

LVPECL, 350MHz, 3.3V VDDOx

LVPECL, 350MHz, 2.5V VDDOx

LVDS, 350MHz, 3.3V VDDOx

47

42

21

20

19

33

18

16

14

42

32

19

14

LVDS, 350MHz, 2.5V VDDOx

LVDS, 350MHz, 1.8V VDDOx

HCSL, 250MHz, 3.3V VDDOx, 2 pF load

HCSL, 250MHz, 2.5V VDDOx, 2 pF load

Iddox

Output Buffer Supply Current

1,2

LVCMOS, 50MHz, 3.3V, VDDOx

1,2

LVCMOS, 50MHz, 2.5V, VDDOx

1,2

LVCMOS, 50MHz, 1.8V, VDDOx

LVCMOS, 200MHz, 3.3V VDDOx¹

LVCMOS, 200MHz, 2.5V VDDOx^1,2

LVCMOS, 200MHz, 1.8V VDDOx^1,2

SD asserted, I2C Programming

Iddpd

Power Down Current

1. Single CMOS driver active.

2. Measured into a 5” 50 Ohm trace with 2 pF load.

3. Iddcore = IddA+ IddD, no loads.

Outputs Features and Descriptions

OUT1/OUT1B, OUT2/OUT2B, and OUT4/OUT4B can form three output pairs. Each output pair has individually programmable

frequencies and can be configured as one differential pair (LVDS, LVPECL, regular HCSL) or two LVCMOS outputs. VDDO is

individually selectable from 1.8V to 3.3V for LVDS and LVCMOS, and 2.5V to 3.3V for LVPECL and regular current-mode HCSL

outputs.

OUT3, 5-11 are 8 Low-Power HCSL(LP-HCSL) differential output pairs. They are the same frequency which can be individually

programmed. They utilize the 1.8V LP-HCSL technology which can reduce supply current and termination resistor count.

LP-HCSL outputs are from 1MHz to 200MHz and other differential outputs are from 1MHz to 350MHz.

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1

Table 12: DC Electrical Characteristics for 3.3V LVCMOS (V

= 3.3V±5%, TA = -40°C to +85°C)

DDO

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -15mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current (OUT1,2,4)

Output Leakage Current (OUT0)

Input HIGH Voltage

2.4

VDDO

IOL = 15mA

0.4

V

Tri-state outputs, VDDO = 3.465V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

SD/OE, SEL1/SDA, SEL0/SCL

5

30

µA

V

0.7xVDDD

GND - 0.3

2

VDDD + 0.3

0.3xVDDD

VDDO0 + 0.3

0.4

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

GND - 0.3

0.8

V

VIH

Input HIGH Voltage

1.2

V

VIL

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

Input Rise/Fall Time

300

ns

1. See “Recommended Operating Conditions” table.

Table 13: DC Electrical Characteristics for 2.5V LVCMOS (V

= 2.5V±5%, TA = -40°C to +85°C)

DDO

Symbol

VOH

VOL

IOZDD

VIH

Parameter

Test Conditions

Min

Typ

Max

Unit

V

IOH = -12mA

Output HIGH Voltage

Output LOW Voltage

Output Leakage Current (OUT1,2,4)

Output Leakage Current (OUT0)

Input HIGH Voltage

0.7xVDDO

IOL = 12mA

0.4

V

Tri-state outputs, VDDO = 2.625V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

SD/OE, SEL1/SDA, SEL0/SCL

5

30

µA

V

0.7xVDDD

GND - 0.3

1.7

VDDD + 0.3

0.3xVDDD

VDDO0 + 0.3

0.4

VIL

Input LOW Voltage

V

VIH

Input HIGH Voltage

V

VIL

Input LOW Voltage

GND - 0.3

0.8

V

VIH

Input HIGH Voltage

1.2

V

VIL

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

Input Rise/Fall Time

300

ns

Table 14: DC Electrical Characteristics for 1.8V LVCMOS ^(V

= 1.8V±5%, TA = -40°C to +85°C)

DDO

Symbol

V_OH

Parameter

Test Conditions

IOH = -8mA

Min

Typ

Max

V_DDO

Unit

V

Output HIGH Voltage

Output LOW Voltage

0.7 xV_DDO

IOL = 8mA

V_OL

0.25 x V_DDO

V

Tri-state outputs, VDDO = 3.465V

Single-ended inputs - SD/OE

Output Leakage Current (OUT1,2,4)

Output Leakage Current (OUT0)

Input HIGH Voltage

5

30

I_OZDD

µA

V_IH

V_IL

0.7 * V_DDD

GND - 0.3

0.65 * V_DDO

GND - 0.3

0.8

V_DDD+ 0.3

0.3 * V_DDD

V_DDO0 + 0.3

0.4

V

Single-ended inputs - SD/OE

Single-ended input OUT0_SEL_I2CB

Single-ended input - XIN/REF

SEL0/SCL

Input LOW Voltage

V_IH

V_IL

Input HIGH Voltage

0

V

Input LOW Voltage

V

V_IH

V_IL

Input HIGH Voltage

1.2

V

Input LOW Voltage

GND - 0.3

0.4

V

TR/TF

Input Rise/Fall Time

300

ns

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Table 15: DC Electrical Characteristics for LVDS(V

= 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)

DDO

Symbol

Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in V_OTbetween Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

V

(+)

(-)

OT

V

-247

OT

V

OT

V

1.125

1.25

1.375

50

OS

Change in V_OSbetween Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DDO

V

mV

mA

OS

I

9

6

24

OS

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

I

12

OSD

Table 16: DC Electrical Characteristics for LVDS (V

= 1.8V+5%, TA = -40°C to +85°C)

DDO

Symbol Parameter

Min

247

Typ

Max

454

-454

50

Unit

mV

V

_OT(+)

_OT(-)

Differential Output Voltage for the TRUE binary state

Differential Output Voltage for the FALSE binary state

Change in VOT between Complimentary Output States

Output Common Mode Voltage (Offset Voltage)

-247

∆V_OT

V_OS

0.8

0.875

0.95

50

∆V_OS

I_OS

Change in VOS between Complimentary Output States

Outputs Short Circuit Current, V_OUT+ or V_OUT- = 0V or V_DD

mV

mA

9

6

24

I_OSD

Differential Outputs Short Circuit Current, V_OUT+ = V_OUT

-

12

Table 17: DC Electrical Characteristics for LVPECL (V

+85°C)

= 3.3V+5% or 2.5V+5%, TA = -40°C to

DDO

Symbol

Parameter

Min

Typ

Max

Unit

V

Output Voltage HIGH, terminated through 50 tied to V_DD- 2 V

Output Voltage LOW, terminated through 50 tied to V_DD- 2 V

Peak-to-Peak Output Voltage Swing

V

- 1.19

- 1.94

V

- 0.69

DDO

OH

DDO

V

- 1.4

DDO

V

OL

V

0.55

0.993

V

SWING

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Table 18: Electrical Characteristics – DIF 0.7V Regular HCSL Outputs (TA = -40°C to +85°C)

(For OUT1, OUT2 and OUT4 programmable differential output pairs when configured as HCSL outputs.),

TA = T_COMor T_IND;Supply voltage per VDD of normal operation conditions; see Test Loads for loading conditions

PARAMETER

SYMBOL

Trf

CONDITIONS

MIN

1

TYP MAX UNITS NOTES

V/ns

%

Slew rate

Slew rate matching

Scope averaging on

Slew rate matching, scope averaging on

4

20

1, 2, 3

1, 2, 4

Trf

Δ

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Voltage High

Voltage Low

V_HIGH

660

850

1,7

mV

V_LOW

-150

150

Max Voltage

Min Voltage

Vswing

Crossing Voltage (abs)

Crossing Voltage (var)

Vmax

Vmin

Vswing

Measurement on single ended signal using

absolute value. (Scope averaging off)

Scope averaging off

1150

1

mV

-300

300

250

mV

1,2,7

1,5,7

1, 6

Vcross_abs

Scope averaging off

550

140

-Vcross

Δ

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

∆

-

absolute) allowed. The intent is to limit Vcross induced modulation by setting Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

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Table 19: Electrical Characteristics–Low Power HCSL (LP-HCSL) Outputs

(For OUT3 and OUT5–11 LP-HCSL differential output pairs.)

TA = T_AMB; Supply voltage per VDD, VDDIO of normal operation conditions; see Test Loads for loading conditions

PARAMETER

Slew rate

SYMBOL

t_RF

CONDITIONS

MIN

1

TYP

2.5

7

MAX

4

UNITS

V/ns

%

NOTES

1,2,3

1,2,4

7

Scope averaging on

Slew rate matching

Voltage High

dV/dt

Slew rate matching, scope averaging on

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

20

V_HIGH

660

0

850

mV

Voltage Low

V_LOW

-150

0

150

7

Max Voltage

Min Voltage

Vswing

Vmax

Vmin

0

1150

7

Measurement on single ended signal using

absolute value. (Scope averaging off)

mV

-300

300

Vswing

Scope averaging off

mV

1,2

Crossing Voltage (abs) Vcross_abs

250

0

550

140

1,5

1,6

Crossing Voltage (var) ∆-Vcross

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the

average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge

(i.e. Clock rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)

allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

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Table 20: AC Timing Electrical Characteristics

(V

= 1.8V ±5%, TA = -40°C to +85°C)

DDO

(Spread Spectrum Generation = OFF)

Symbol

Min.

Typ.

Max.

40

Units

MHz

Parameter

Test Conditions

8

1

Input frequency limit (XIN)

Input frequency limit (REF)

Single ended clock output limit (LVCMOS)

Differential clock output limit

1

f_IN

Input Frequency

200

350

2900

150

0.9

1

f_OUT

Output Frequency

MHz

1

f_VCO

f_PFD

f_BW

t2

VCO Frequency

PFD Frequency

Loop Bandwidth

Input Duty Cycle

2500

MHz

%

VCO operating frequency range

PFD operating frequency range

Input frequency = 25MHz

1 ¹

0.06

45

55

Duty Cycle

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX = 2.5V or

3.3V

Measured at VDD/2, all outputs except

Reference output OUT0, VDDOX=1.8V

Measured at VDD/2, Reference output

OUT0 (5MHz - 120MHz) with 50% duty

cycle input

45

40

50

55

60

%

t3 ⁵

Output Duty Cycle

Measured at VDD/2, Reference output

OUT0 (150.1MHz - 200MHz) with 50% duty

cycle input

30

50

70

%

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Slew Rate, SLEW[1:0] = 00

Slew Rate, SLEW[1:0] = 01

Slew Rate, SLEW[1:0] = 10

Slew Rate, SLEW[1:0] = 11

Rise Times

2.2

2.3

2.4

2.7

1.3

1.4

1.7

0.7

0.8

0.9

1.2

300

400

1.0

1.2

1.3

1.7

0.6

0.7

0.6

1.0

0.3

0.4

0.7

Single-ended 3.3V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX = 3.3V

Single-ended 2.5V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX = 2.5V

t4 ²

V/ns

Single-ended 1.8V LVCMOS output clock

rise and fall time, 20% to 80% of VDDO

(Output Load = 5 pF) VDDOX = 1.8V

LVDS, 20% to 80%

LVDS, 80% to 20%

LVPECL, 20% to 80%

LVPECL, 80% to 20%

Fall Times

t5

ps

Rise Times

Fall Times

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Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

differential outputs

46

74

ps

Cycle-to-Cycle jitter (Peak-to-Peak),

multiple output frequencies switching,

LVCMOS outputs

RMS Phase Jitter (12kHz to 5MHz

integration range) reference clock (OUT0),

25 MHz LVCMOS outputs

t6

Clock Jitter

0.5

RMS Phase Jitter (12kHz to 20MHz

integration range) differential output, 25MHz

crystal, 156.25MHz on OUT2, and 100MHz

LP-HCSL outputs on OUT3, OUT5-11.

0.75

75

1.5

ps

Skew between the same frequencies , with

outputs using the same driver format and

phase delay set to 0 ns.

Skew between outputs at same frequency

and conditions

Output Skew between OUT1,

OUT2, OUT4

ps

t7

Output Skew between OUT3 and

OUT5-11

49.5

84

PLL lock time from power-up, measured

after all VDD's have raised above 90% of

their target value.

t8 ³

t9 ⁴

Startup Time

10

4

ms

3

Startup Time

PLL lock time from shutdown mode

1. Practical low er frequency is determined by loop filter settings.

2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.

3. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/w rite time.

4. Actual PLL lock time depends on the loop configuration.

5. Spread Spectrum generation is off unless otherw ise stated.

Table 21: PCI Express Jitter Specifications (V

(For LP-HCSL(OUT3, OUT5-11) outputs)

= 1.8V +5%, T = -40°C to +85°C)

A

DDO

PCIe Industry

Specification

Symbol

Parameter

Conditions

Min

Typ

Max

Units Notes

ƒ = 100MHz, 25MHz crystal input

evaluation band: 0Hz - Nyquist (clock

frequency/2)

Phase Jitter Peak-

to-Peak

t_J(PCIe Gen1)

23.85

86

ps

1,4

2,4

ƒ = 100MHz, 25MHz crystal input high

Phase Jitter RMS band: 1.5MHz - Nyquist (clock

frequency/2)

t_{REFCLK_HF_RMS}

(PCIe Gen2)

1.83

3.1

t_{REFCLK_LF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz crystal input low

Phase Jitter RMS

0.54

0.51

3

1

ps

2,4

3,4

band: 10kHz - 1.5MHz

ƒ = 100MHz, 25MHz crystal input

t_{REFCLK_RMS}

(PCIe Gen3)

evaluation band: 0Hz - Nyquist (clock

frequency/2)

Phase Jitter RMS

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained

transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation

band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t

(High Band) and 3.0ps RMS for t

(Low Band).

REFCLK_HF_RMS

REFCLK_LF_RMS

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is

subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

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Table 22: PCI Express Jitter Specifications (V

(For regular HCSL(OUT1, OUT2 and OUT4) outputs)

= 3.3V±5% or 2.5V±5%, T = -40°C to +85°C)

DDO

A

PCIe Industry

Specification

Symbol

Parameter

Conditions

Min

Typ

Max

Units Notes

ƒ = 100MHz, 25MHz crystal input

evaluation band: 0Hz - Nyquist (clock

frequency/2)

Phase Jitter Peak-

to-Peak

t_J(PCIe Gen1)

30

86

ps

1,4

2,4

ƒ = 100MHz, 25MHz crystal input high

Phase Jitter RMS band: 1.5MHz - Nyquist (clock

frequency/2)

t_{REFCLK_HF_RMS}

(PCIe Gen2)

2.25

3.1

t_{REFCLK_LF_RMS}

(PCIe Gen2)

ƒ = 100MHz, 25MHz crystal input low

Phase Jitter RMS

0.27

0.8

3

1

ps

2,4

3,4

band: 10kHz - 1.5MHz

ƒ = 100MHz, 25MHz crystal input

t_{REFCLK_RMS}

(PCIe Gen3)

evaluation band: 0Hz - Nyquist (clock

frequency/2)

Phase Jitter RMS

Note: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained

transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

1. Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1.

2. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation

band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t

(High Band) and 3.0ps RMS for t

(Low Band).

REFCLK_HF_RMS

REFCLK_LF_RMS

3. RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI_Express_Base_r3.0 10 Nov, 2010 specification, and is

subject to change pending the final release version of the specification.

4. This parameter is guaranteed by characterization. Not tested in production.

Table 23: Spread Spectrum Generation Specifications

Symbol Parameter

f_OUTOutput Frequency

f_MOD

Description

Min

Typ

Max

Unit

MHz

kHz

Output frequency range

1

300

Mod Frequency

Spread Value

Modulation frequency

30 to 63

Amount of spread value (programmable) - center spread

Amount of spread value (programmable) - down spread

±0.25% to ±2.5%

-0.5% to -5%

f_SPREAD

%f_OUT

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5P49V5908 DATASHEET

5P49V5908 Reference Schematic

2

1

2

E P A D

5 8

5 7

E P A D

5 6

5 5

E P A D

5 4

5 3

E P A D

5 2

1

2

E P A D

5 1

E P A D

5 0

E P A D

4 9

1

2

1

2

1

2

1

2

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Test Circuits and Loads

V_DDOx

V_DDD

V_DDA

OUTx

CLK_OUT

0.1µF

C_L

GND

HCSL Differential Output Test Load

Zo=100ohm differential

33

2pF

33

50

HCSL Output

Low-Power Differential Output Test Load

5 inches

Rs

Zo=100ohm

2pF

Alternate Differential Output Terminations

Rs

33

27

Zo

100

85

Units

Ohms

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Typical Phase Noise at 100MHz (3.3V, 25°C)

NOTE: All outputs operational at 100MHz, Phase Noise Plot with Spurs On.

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5P49V5908 DATASHEET

Overdriving the XIN/REF Interface

LVCMOS Driver

The XIN/REF input can be overdriven by an LVCMOS driver

or by one side of a differential driver through an AC coupling

capacitor. The XOUT pin can be left floating. The amplitude of

the input signal should be between 500mV and 1.2V and the

slew rate should not be less than 0.2V/ns. Figure General

Diagram for LVCMOS Driver to XTALInput Interface shows an

example of the interface diagram for a LVCMOS driver.

This configuration has three properties; the total output

impedance of Ro and Rs matches the 50 ohm transmission

line impedance, the Vrx voltage is generated at the CLKIN

inputs which maintains the LVCMOS driver voltage level

across the transmission line for best S/N and the R1-R2

voltage divider values ensure that the clock level at XIN is less

than the maximum value of 1.2V.

VDD

XOUT

C3

Ro

Rs

Zo = 50 Ohm

R1

V_XIN

XIN / REF

Ro + Rs

LVCMOS

=

50 ohms

0. 1 uF

R2

General Diagram for LVCMOS Driver to XTAL Input Interface

Table 24 Nominal Voltage Divider Values vs LVCMOS VDD for

XIN shows resistor values that ensure the maximum drive

level for the XIN/REF port is not exceeded for all combinations

of 5% tolerance on the driver VDD, the VersaClock VDDAand

5% resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the voltage divider attenuation

as long as the minimum drive level is maintained over all

tolerances. To assist this assessment, the total load on the

driver is included in the table.

Table 24: Nominal Voltage Divider Values vs LVCMOS VDD for XIN

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

V_XIN (peak)

Ro+Rs+R1+R2

3.3

2.5

1.8

0.97

1.00

0.97

255

250

242

50.0

100

130

50.0

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LVPECL Driver

Figure General Diagram for LVPECL Driver to XTAL Input

Interface shows an example of the interface diagram for a

+3.3V LVPECL driver. This is a standard LVPECL termination

with one side of the driver feeding the XIN/REF input. It is

recommended that all components in the schematics be

placed in the layout; though some components might not be

used, they can be utilized for debugging purposes. The

datasheet specifications are characterized and guaranteed by

using a quartz crystal as the input. If the driver is 2.5V

LVPECL, the only change necessary is to use the appropriate

value of R3.

XOUT

C1

Zo = 50 Ohm

XIN / REF

0. 1 uF

Zo = 50 Ohm

R1

50

R2

50

+3.3V LVPECL Dr iv er

R3

50

Table 25 Nominal Voltage Divider Values vs Driver VDD

shows resistor values that ensure the maximum drive level for

the CLKIN port is not exceeded for all combinations of 5%

tolerance on the driver VDD, the VersaClock Vddo_0 and 5%

resistor tolerances. The values of the resistors can be

adjusted to reduce the loading for slower and weaker

LVCMOS driver by increasing the impedance of the R1-R2

divider. To assist this assessment, the total load on the driver

is included in the table.

Table 25: Nominal Voltage Divider Values vs Driver VDD

LVCMOS Driver VDD

Ro+Rs

50.0

R1

130

100

62

R2

75

Vrx (peak)

0.97

Ro+Rs+R1+R2

3.3

2.5

1.8

255

250

242

50.0

100

130

1.00

50.0

0.97

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5P49V5908 DATASHEET

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

common mode noise. The capacitor value should be

approximately 50pF. In addition, since these outputs are LVDS

compatible, the input receiver's amplitude and common-mode

input range should be verified for compatibility with the IDT

LVDS output. If using a non-standard termination, it is

recommended to contact IDT and confirm that the termination

will function as intended. For example, the LVDS outputs

cannot be AC coupled by placing capacitors between the

LVDS outputs and the 100 shunt load. If AC coupling is

required, the coupling caps must be placed between the 100

shunt termination and the receiver. In this manner the

termination of the LVDS output remains DC coupled

termination impedance (Z ) is between 90. and 132. The

T

actual value should be selected to match the differential

impedance (Zo) of your transmission line. A typical

point-to-point LVDS design uses a 100 parallel resistor at the

receiver and a 100. differential transmission-line

environment. In order to avoid any transmission-line reflection

issues, the components should be surface mounted and must

be placed as close to the receiver as possible. The standard

termination schematic as shown in figure Standard

Termination or the termination of figure Optional Termination

can be used, which uses a center tap capacitance to help filter

Z

 Z

T

LVDS

Receiver

O

LVDS

Driver

Z

T

Standard Termination

Z

2

T

Z

 Z

T

O

LVDS

Driver

LVDS

Receiver

Z

2

T

C

Optional Termination

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5P49V5908 DATASHEET

PCI Express Application Note

PCI Express jitter analysis methodology models the system

response to reference clock jitter. The block diagram below

shows the most frequently used Common Clock Architecture

in which a copy of the reference clock is provided to both ends

of the PCI Express Link. In the jitter analysis, the transmit (Tx)

and receive (Rx) serdes PLLs are modeled as well as the

phase interpolator in the receiver. These transfer functions are

called H1, H2, and H3 respectively. The overall system

transfer function at the receiver is:

RMS. The two evaluation ranges for PCI Express Gen 2 are

10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High

Band). The plots show the individual transfer functions as well

as the overall transfer function Ht.

Hts = H3s  H1s – H2s

The jitter spectrum seen by the receiver is the result of

applying this system transfer function to the clock spectrum

X(s) and is:

Ys = Xs  H3s  H1s – H2s

In order to generate time domain jitter numbers, an inverse

Fourier Transform is performed on X(s)*H3(s) * [H1(s) -

H2(s)].

PCIe Gen2A Magnitude of Transfer Function

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and

the evaluation is performed over the entire spectrum. The

transfer function parameters are different from Gen 1 and the

jitter result is reported in RMS.

PCIe Gen1 Magnitude of Transfer Function

For PCI Express Gen2, two transfer functions are defined with

2 evaluation ranges and the final jitter number is reported in

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5P49V5908 DATASHEET

PCIe Gen3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI

Express Reference Clock Requirements.

Marking Diagram

IDT5P49V59

08BdddNDGI

#YYWW$

LOT

1. “ddd” denotes the dash code.

2. “G” denotes RoHS compliance.

3. “I” denotes industrial temperature.

4. “YYWW” is the two last digits of the year and week that the part was assembled.

5. “#” denotes the stepping code.

6. “$” denotes mark code.

7. “LOT” denotes lot number.

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Package Outline and Dimensions NDG48 (48-pin VFQFN)

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Package Outline and Dimensions NDG48 (48-pin VFQFN), cont.

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Ordering Information

Part / Order Number

5P49V5908BdddNDGI

5P49V5908BdddNDGI8

Shipping Packaging

Trays

Package

48-pin VFQFPN

Temperature

-40° to +85°C

Tape and Reel

“ddd” denotes the dash code.

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

Revision History

Date

Description of Change

March 10, 2017

1. Updated package outline drawings.

2. Updated legal disclaimer.

3. Corrected typos.

February 24, 2017

1. Added “Output Alignment” section.

2. Update “Output Divides” section

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Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-

lectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

5P49V5908 MARCH 10, 2017

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