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IX2113BTR

型号：

IX2113BTR

品牌：

IXYS[ IXYS CORPORATION ]

页数：

13 页

PDF大小：

297 K

下载PDF手册
IX2113  
600V High and Low Side  
Gate Driver  
INTEGRATED  
C
IRCUITS  
D
IVISION  
Driver Characteristics  
Description  
The IX2113 is a high voltage integrated circuit that can  
drive high speed MOSFETs and IGBTs that operate at  
up to +600V. The IX2113 is configured with  
independent high-side and low-side referenced output  
channels, both of which can source and sink 2A. The  
floating high-side channel can drive an N-channel  
power MOSFET or IGBT 600V from the common  
reference.  
Parameter  
VOFFSET  
Rating  
Units  
600  
2/2  
V
A
V
IO +/- (Source/Sink)  
V
10-20  
OUT  
t
/t  
113/100  
20  
ns  
ns  
on off  
Delay Matching (Max)  
Manufactured on IXYS Integrated Circuits Division's  
proprietary high-voltage BCDMOS on SOI (silicon on  
insulator) process, the IX2113 is extremely robust, and  
is virtually immune to negative transients. The UVLO  
circuit prevents the turn-on of the MOSFET or IGBT  
Features  
• Floating Channel for Bootstrap Operation to +600V  
with Absolute Maximum Rating of +700V  
• Outputs Capable of Sourcing and Sinking 2A  
• Gate Drive Supply Range From 10V to 20V  
• Enhanced Robustness due to SOI Process  
• Tolerant to Negative Voltage Transients:  
dV/dt Immune  
until there is sufficient V or V supply voltage.  
BS  
CC  
Propagation delays are matched for use in high  
frequency applications.  
• 3.3V Logic Compatible  
• Undervoltage Lockout for Both High-side and  
Low-Side Outputs  
The IX2113 is available in a 14-pin DIP package and  
in a 16-pin SOIC package.  
• Matched Propagation Delays  
Ordering Information  
Part  
Description  
IX2113G  
IX2113B  
14-Pin DIP (25/Tube)  
16-Pin SOIC (50/Tube)  
16-Pin SOIC (1000/Reel)  
IX2113BTR  
IX2113 Functional Block Diagram  
VDD  
VB  
Level  
Shift  
VDD / VCC  
UVLO  
High  
HIN  
SD  
Pulse  
Generator  
Voltage  
Level  
Shift  
R
VSS / COM  
Input Control Logic  
&
R
S
Buffer  
Q
HO  
Cycle-by-Cycle  
Edge-Triggered  
Shutdown  
VS  
UVLO  
VCC  
LIN  
VSS  
Level  
Shift  
VDD / VCC  
LS Delay  
Control  
Buffer  
LO  
VSS / COM  
COM  
DS-IX2113-R03  
www.ixysic.com  
1
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.1 Package Pinout: 16-Pin SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.2 Pin Description: 16-Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.3 Package Pinout: 14-Pin DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.4 Pin Description: 14-Pin DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
1.7 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.8 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.9 Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2. Typical Performance Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
3.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
2
www.ixysic.com  
R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
1 Specifications  
1.1 Package Pinout: 16-Pin SOIC Package  
1.3 Package Pinout: 14-Pin DIP Package  
LO - 1  
16  
LO - 1  
14  
COM - 2  
15 - VSS  
14 - LIN  
13 - SD  
12 - HIN  
11 - VDD  
10  
COM - 2  
13 - VSS  
12 - LIN  
11 - SD  
10 - HIN  
9 - VDD  
8
V
CC - 3  
4
5
V
CC - 3  
4
VS - 6  
VB - 7  
HO - 8  
VS - 5  
VB - 6  
9
HO - 7  
1.2 Pin Description: 16-Pin SOIC Package  
1.4 Pin Description: 14-Pin DIP Package  
Pin#  
Name  
Description  
Pin#  
Name  
Description  
1
2
LO  
1
2
3
4
5
6
7
8
9
LO  
Low-Side Gate Drive Output  
Low-Side Return  
Low-Side Gate Drive Output  
Low-Side Return  
COM  
COM  
V
V
3
Low-Side Supply  
Low-Side Supply  
CC  
CC  
4
-
-
-
No Connection  
No Connection  
V
5
No Connection  
High-Side Floating Supply Return  
High-Side Floating Supply  
High-Side Gate Drive Output  
No Connection  
S
V
6
V
High-Side Floating Supply Return  
High-Side Floating Supply  
High-Side Gate Drive Output  
No Connection  
S
B
V
7
HO  
-
B
8
HO  
V
9
-
-
Logic Supply  
DD  
10  
11  
No Connection  
Logic Input for High-Side Gate Driver  
Output (HO), In-Phase  
10  
11  
12  
HIN  
SD  
V
Logic Supply  
DD  
Logic Input for Shutdown  
Logic Input for High-Side Gate Driver  
Output (HO), In-Phase  
12  
13  
14  
HIN  
SD  
Logic Input for Low-Side Gate Driver  
Output (LO), In-Phase  
LIN  
Logic Input for Shutdown  
V
13  
14  
Logic Ground  
SS  
Logic Input for Low-Side Gate Driver  
Output (LO), In-Phase  
LIN  
-
No Connection  
V
15  
16  
Logic Ground  
SS  
-
No Connection  
R03  
www.ixysic.com  
3
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
1.5 Absolute Maximum Ratings  
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage  
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are  
measured under board-mounted and still-air conditions.  
Parameter  
High-Side Floating Supply Voltage  
Symbol  
Min  
Max  
Units  
V
-0.3  
700  
V
V
B
V
High-Side Floating Supply Offset Voltage  
High-Side Floating Output Voltage  
Low-Side Fixed Supply Voltage  
Low-Side Output Voltage  
VB-20  
VB+0.3  
S
V
VS-0.3  
-0.3  
VB+0.3  
20  
HO  
V
V
V
CC  
V
V
CC+0.3  
LO  
-0.3  
V
V
Logic Supply Voltage  
V
SS+20  
VCC+0.3  
VDD+0.3  
DD  
-0.3  
V
V
Logic Supply Offset Voltage  
VCC-20  
SS  
V
V
Logic Input Voltage (HIN, LIN, SD)  
Allowable Offset Supply Voltage Transient  
VSS-0.3  
IN  
V
dV /dt  
S
-
-
50  
1.25  
1.6  
V/ns  
Package Power Dissipation @ T 25°C  
16-Pin SOIC  
14-Pin DIP  
16-Pin SOIC  
14-Pin DIP  
A
PD  
W
Thermal Resistance, Junction to Ambient  
-
100  
75  
R
°C/W  
JA  
T
Junction Temperature  
-
-55  
-
150  
150  
300  
°C  
°C  
J
T
Storage Temperature  
S
T
Lead Temperature (Soldering, 10 Seconds)  
°C  
L
1.6 Recommended Operating Conditions  
For proper operation, the device should be used within the recommended conditions. The V and V offset ratings  
S
SS  
are tested with all supplies biased at a 15V differential.  
Parameter  
Symbol  
Min  
Max  
Units  
V
High-Side Floating Supply Absolute Voltage  
VS+10  
VS+20  
B
V
High-Side Floating Supply Offset Voltage  
High-Side Floating Output Voltage  
Low-Side Fixed Supply Voltage  
Low-Side Output Voltage  
S
-
600  
VB  
V
VS  
HO  
V
10  
20  
CC  
V
V
VCC  
LO  
0
V
Logic Supply Voltage  
VSS+3  
VSS+20  
DD  
V
Logic Supply Offset Voltage  
Logic Input Voltage (HIN, LIN, SD)  
Ambient Temperature  
SS  
-5  
5
V
VSS  
VDD  
IN  
T
-40  
+125  
°C  
A
4
www.ixysic.com  
R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
1.7 Dynamic Electrical Characteristics  
(V , V , V )=15V, CL=1000 pF, T =25°C, and V =COM unless otherwise specified.  
V
BIAS  
CC BS DD  
A
SS  
Parameter  
Conditions  
Symbol  
ton  
Min  
Typ  
Max  
Units  
V =0V  
S
Turn-On propagation Delay  
Turn-Off propagation Delay  
Shutdown propagation Delay  
Turn-On Rise Time  
-
-
-
-
113  
100  
94  
160  
150  
160  
35  
toff  
V =600V  
S
tSD  
tr  
ns  
-
-
-
9.4  
Turn-Off Fall Time  
tf  
-
-
9.7  
-
25  
20  
Delay Matching, HS & LS Turn-On/Off  
MT  
1.8 Static Electrical Characteristics  
V
(V , V , V )=15V, T =25°C and V =COM unless otherwise specified. The V , V , and I parameters  
BIAS  
CC BS DD A SS IN TH IN  
are referenced to V and are applicable to all three logic input leads: HIN, LIN, and SD. The V and I parameters  
SS  
O
O
are referenced to COM and are applicable to the respective output leads: HO or LO.  
Parameter  
Logic “1” Input Voltage  
Conditions  
Symbol  
VIH  
Min  
Typ  
Max  
Units  
9.5  
-
-
-
6
V
=15V  
V
DD  
Logic “0” Input Voltage  
VIL  
-
2.5  
-
Logic “1” Input Voltage  
VIH  
-
-
V
=3V  
V
DD  
Logic “0” Input Voltage  
VIL  
-
0.8  
2.5  
0.15  
60  
310  
420  
1
High-Level Output Voltage, V -V  
BIAS  
I =0A  
O
VOH  
VOL  
O
-
1.6  
-
V
Low-Level Output Voltage, V  
I =20mA  
O
O
-
V =V =600V  
S
Offset Supply Leakage Current  
ILK  
B
-
-
Quiescent V Supply Current  
BS  
V =0V or V  
IN  
IQBS  
IQCC  
IQDD  
IIN+  
DD  
DD  
DD  
-
187  
300  
-
A  
A  
V
Quiescent V Supply Current  
CC  
V =0V or V  
IN  
-
Quiescent V Supply Current  
DD  
V =0V or V  
IN  
-
V =V  
IN DD  
Logic “1” Input Bias Current  
Logic “0” Input Bias Current  
-
22  
-
40  
5
V =0V  
IN  
IIN-  
-
V
V
V
V
Supply Undervoltage Positive Going Threshold  
Supply Undervoltage Negative Going Threshold  
Supply Undervoltage Positive Going Threshold  
Supply Undervoltage Negative Going Threshold  
-
-
-
-
VBSUV+  
VBSUV-  
VCCUV+  
VCCUV-  
IO+  
BB  
BB  
CC  
CC  
7.5  
7
7.4  
7
2
2
8.4  
7.8  
8.4  
7.8  
2.5  
2.5  
9.7  
9.4  
9.6  
9.4  
-
V =0V, V =V , PW10s  
Output High Short Circuit Pulsed Current  
Output Low Short Circuit Pulsed Current  
O
IN DD  
A
V =15V, V =0V, PW10s  
IO-  
O
IN  
-
R03  
www.ixysic.com  
5
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
1.9 Test Waveforms  
1.9.1 Switching Time Test Circuit  
VCC=15V  
VB  
10µF  
0.1µF  
+
11  
3
7
0.1µF  
10µF 15V  
-
6
VS  
12  
13  
14  
CL  
HIN  
SD  
8
(0 to 500V/600V)  
10µF  
HO  
LO  
1
LIN  
CL  
Note: Pin numbers shown  
are for the SOIC package.  
15  
2
1.9.2 Input/Output Timing Diagram  
1.9.4 Shutdown Waveform Definitions  
HIN  
LIN  
50%  
SD  
SD  
tsd  
HO  
LO  
90%  
HO  
LO  
1.9.3 Switching Time Waveform Definition  
1.9.5 Delay Matching Waveform Definitions  
50%  
HO  
50%  
HIN  
LIN  
50%  
tr  
50%  
toff  
HIN  
LIN  
ton  
tf  
LO  
90%  
90%  
10%  
HO  
LO  
MT  
MT  
HO  
10%  
10%  
90%  
LO  
6
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R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
2 Typical Performance Data  
Turn-On Delay Time  
vs.Temperature  
Turn-On Delay Time  
vs. VBIAS Supply Voltage  
Turn-Off Delay Time vs.Temperature  
250  
200  
150  
100  
50  
250  
250  
200  
150  
100  
50  
200  
150  
100  
50  
0
0
0
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
9
11  
13  
15  
17  
19  
21  
Temperature (ºC)  
Temperature (ºC)  
Supply Voltage (V)  
Turn-Off Delay Time  
vs. VBIAS Supply Voltage  
Shutdown Delay Time  
vs. VBIAS Supply Voltage  
Shutdown Delay Time  
vs.Temperature  
250  
200  
150  
100  
50  
250  
200  
150  
100  
50  
250  
200  
150  
100  
50  
0
0
0
-50  
-25  
0
25  
50  
75  
100 125  
10  
12  
14  
16  
18  
20  
9
11  
13  
15  
17  
19  
21  
VBIAS Supply Voltage (V)  
Temperature (ºC)  
Supply Voltage (V)  
Shutdown Delay Time  
vs. VDD Supply Voltage  
Turn-Off Fall Time vs.Temperature  
Turn-On Rise Time vs.Temperature  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
350  
300  
250  
200  
150  
100  
50  
0
-50  
-25  
0
25  
50  
75  
100 125  
0
5
10  
15  
20  
-50  
-25  
0
25  
50  
75  
100 125  
Temperature (ºC)  
VDD Supply Voltage (V)  
Temperature (ºC)  
R03  
www.ixysic.com  
7
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
Logic “0” Input Threshold vs. VDD  
Turn-Off Fall Time vs. Voltage  
Turn-On Rise Time vs. Voltage  
12  
10  
8
35  
30  
25  
20  
15  
10  
5
35  
30  
25  
20  
15  
10  
5
6
4
2
0
0
0
0
3
6
9
12  
15  
18  
21  
10  
-50  
-50  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
VDD (V)  
VBIAS Supply Voltage (V)  
VBIAS Supply Voltage (V)  
Logic "0" Input Threshold  
Logic "1" Input Threshold  
Logic “1” Input Threshold vs. VDD  
vs.Temperature  
vs.Temperature  
12  
10  
8
15  
12  
9
15  
12  
9
6
6
6
4
3
3
2
0
0
0
0
3
6
9
12  
15  
18  
21  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
VDD (V)  
Temperature (ºC)  
Temperature (ºC)  
Logic "0" Input Current  
Logic "1" Input Bias Current  
VDD Supply Current vs.Temperature  
vs.Temperature  
vs.Temperature  
20  
15  
10  
5
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
80  
60  
40  
20  
0
0
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
-25  
0
25  
50  
75  
100 125  
Temperature (ºC)  
Temperature (ºC)  
Temperature (ºC)  
VBS Supply Current vs.Temperature  
VCC Supply Current vs.Temperature  
VDD Supply Current vs. Voltage  
500  
400  
300  
200  
100  
0
600  
500  
400  
300  
200  
100  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
0
5
10  
15  
20  
Temperature (ºC)  
Temperature (ºC)  
VDD Logic Supply Voltage (V)  
8
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R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
Offset Supply Leakage Current  
vs.Temperature  
VCC Supply Current vs. Voltage  
VBS Supply Current vs. Voltage  
50  
40  
30  
20  
10  
0
500  
400  
300  
200  
100  
0
500  
400  
300  
200  
100  
0
-50  
-25  
0
25  
50  
75  
100 125  
10  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
Temperature (ºC)  
VCC Fixed Supply Voltage (V)  
VBS Floating Supply Voltage (V)  
VCC Undervoltage Lockout (+)  
VCC Undervoltage Lockout (-)  
Offset Supply Leakage Current  
vs. VB Boost Voltage  
vs.Temperature  
vs.Temperature  
11  
10  
9
11  
10  
9
500  
400  
300  
200  
100  
0
8
8
7
7
6
6
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
0
100  
200  
300  
400  
500  
600  
Temperature (ºC)  
Temperature (ºC)  
VB Boost Voltage (V)  
High Level Output Voltage  
vs.Temperature  
(IO=0mA)  
VBS Undervoltage Lockout (-)  
VBS Undervoltage Lockout (+)  
vs.Temperature  
vs.Temperature  
5
4
3
2
1
0
11  
10  
9
11  
10  
9
8
8
7
7
6
6
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
Temperature (ºC)  
Temperature (ºC)  
Temperature (ºC)  
Low Level Output Voltage  
vs.Temperature  
(IO=20mA)  
Output Source Current  
vs.Temperature  
Output Sink Current  
vs.Temperature  
1.0  
5
5
0.8  
0.6  
0.4  
0.2  
0.0  
4
3
2
1
0
4
3
2
1
0
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
-50  
-25  
0
25  
50  
75  
100 125  
Temperature (ºC)  
Temperature (ºC)  
Temperature (ºC)  
R03  
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9
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
High Level Output Voltage  
vs. Supply Voltage  
Output Source Current vs. Voltage  
Output Sink Current vs. Voltage  
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
10  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
10  
12  
14  
16  
18  
20  
VBIAS Supply Voltage (V)  
VBIAS Supply Voltage (V)  
VBIAS Supply Voltage (V)  
Low Level Output Voltage  
vs. Supply Voltage  
200  
160  
120  
80  
40  
0
10  
12  
14  
16  
18  
20  
VCC Supply Voltage (V)  
Figure 1. Typical Connection Diagram  
up to 600V  
VDD  
VDD  
HO  
VB  
VS  
HIN  
SD  
HIN  
SD  
LOAD  
VCC  
LIN  
LIN  
COM  
LO  
VSS  
VCC  
VSS  
10  
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R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
3 Manufacturing Information  
3.1 Moisture Sensitivity  
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated  
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the  
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product  
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee  
proper operation of our devices when handled according to the limitations and information in that standard as well as  
to any limitations set forth in the information or standards referenced below.  
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced  
product performance, reduction of operable life, and/or reduction of overall reliability.  
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to  
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.  
Device  
Moisture Sensitivity Level (MSL) Rating  
IX2113B, IX2113G  
MSL 1  
3.2 ESD Sensitivity  
This product is ESD Sensitive, and should be handled according to the industry standard  
JESD-625.  
3.3 Reflow Profile  
This product has a maximum body temperature and time rating as shown below. All other guidelines of  
J-STD-020 must be observed.  
Device  
Maximum Temperature x Time  
IX2113B  
IX2113G  
260°C for 30 seconds  
245°C for 30 seconds  
3.4 Board Wash  
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to  
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or  
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be  
used.  
R03  
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11  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
3.5 Mechanical Dimensions  
3.5.1 IX2113B: 16-Pin SOIC Package  
Recommended PCB Land Pattern  
10.211 0.254  
(0.402 0.010)  
1.27  
(0.050)  
PIN 16  
10.312 0.381  
(0.406 0.015)  
9.40  
(0.370)  
7.493 0.127  
(0.295 0.005)  
2.00  
(0.079)  
PIN 1  
0.406 0.076  
(0.016 0.003)  
0.60  
(0.024)  
1.270 TYP  
(0.050 TYP)  
2.337 0.051  
(0.092 0.002)  
45º  
0.649 0.102  
(0.026 0.004)  
0.203 0.102  
(0.008 0.004)  
0.889 0.178  
(0.035 0.007)  
0.254 / +0.051 / -0.025  
(0.010 / +0.002 / -0.001)  
DIMENSIONS  
mm  
NOTES:  
1. Coplanarity = 0.1016 (0.004) max.  
2. Leadframe thickness does not include solder plating (1000 microinch maximum).  
(inches)  
3.5.2 IX2113BTR: Tape & Reel Packaging for 16-Pin SOIC Package  
330.2 DIA.  
(13.00 DIA.)  
W=16  
(0.630)  
B0=10.70  
Top Cover  
(0.421)  
Tape Thickness  
0.102 MAX.  
(0.004 MAX.)  
A0=10.90  
(0.429)  
P=12.00  
(0.472)  
K0=3.20  
(0.126)  
K1=2.70  
(0.106)  
Embossed Carrier  
NOTES:  
1. All dimensions carry tolerances of EIA Standard 481-2  
2. The tape complies with all “Notes” for constant dimensions  
listed on page 5 of EIA-481-2  
Dimensions  
mm  
Embossment  
(inches)  
12  
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R03  
IX2113  
INTEGRATED  
C
IRCUITS  
D
IVISION  
3.5.3 IX2113G: 14-Pin DIP Through-Hole Package  
18.542 / 19.050  
(0.730 / 0.750)  
See Note 2  
PCB Hole Pattern  
0º / 15º  
8.509 / 9.525  
7.62  
(0.300)  
7.62 BSC  
(0.300 BSC)  
1.35  
(0.053)  
(0.335 / 0.375)  
See Note 3  
Pin 1  
2.542  
(0.100)  
2.54  
(0.100)  
1.524 typ  
(0.06 typ)  
0.85  
(0.0335)  
Hole Size =  
6.223 / 6.477  
(0.245 / 0.255)  
See Note 2  
5.334 max  
NOTES:  
(0.210 max)  
3.175 / 3.429  
1. JEDEC outline: MS-001 AA.  
(0.125 / 0.135)  
2. This dimension does not include mold flash or  
protrusions. Mold flash or protrusions shall not  
exceed 0.254 (0.010).  
3. Measured at the lead tips with the leads  
unconstrained.  
4. Pointed or rounded lead tips are preferred to  
ease insertion.  
5. Distance between leads including dam bar  
protrusions to be 0.127 (0.005).  
6. Datum plane H coincident with the bottom of  
lead where lead exits body.  
H
Seating Plane  
0.457 typ  
(0.018 typ)  
2.921 / 3.810  
(0.115 / 0.150)  
0.381 min  
(0.015 min)  
DIMENSIONS  
(min / max)  
mm  
(inches)  
For additional information please visit our website at: www.ixysic.com  
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make  
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated  
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its  
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.  
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other  
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe  
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.  
Specification: DS-IX2113-R03  
©Copyright 2014, IXYS Integrated Circuits Division  
All rights reserved. Printed in USA.  
6/9/2014  
R03  
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13  
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