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NVTFS5C673NLWFTAG

型号：

NVTFS5C673NLWFTAG

品牌：

ONSEMI[ ONSEMI ]

页数：

6 页

PDF大小：

86 K

下载PDF手册
NVTFS5C673NL  
Power MOSFET  
60 V, 9.8 mW, 50 A, Single N−Channel  
Features  
• Small Footprint (3.3 x 3.3 mm) for Compact Design  
• Low R  
to Minimize Conduction Losses  
DS(on)  
www.onsemi.com  
• Low Capacitance to Minimize Driver Losses  
• NVTFS5C673NLWF − Wettable Flanks Product  
• AEC−Q101 Qualified and PPAP Capable  
V
R
MAX  
I MAX  
D
(BR)DSS  
DS(on)  
• These Devices are Pb−Free and are RoHS Compliant  
9.8 mW @ 10 V  
15 mW @ 4.5 V  
60 V  
50 A  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Parameter  
Drain−to−Source Voltage  
Symbol  
Value  
60  
Unit  
V
N−Channel  
V
DSS  
D (5 − 8)  
Gate−to−Source Voltage  
V
GS  
20  
V
Continuous Drain Cur-  
rent R  
(Notes 1, 2, 3, 4)  
T
= 25°C  
= 100°C  
= 25°C  
I
50  
A
C
D
q
JC  
T
C
35  
Steady  
State  
G (4)  
Power Dissipation  
T
C
P
46  
W
A
D
R
(Notes 1, 2, 3)  
q
JC  
T
C
= 100°C  
23  
S (1, 2, 3)  
Continuous Drain Cur-  
rent R  
T = 25°C  
A
I
D
13  
q
JA  
T = 100°C  
A
9
(Notes 1 & 3, 4)  
Steady  
State  
MARKING DIAGRAM  
Power Dissipation  
T = 25°C  
A
P
3.1  
1.6  
290  
W
1
D
R
(Notes 1, 3)  
1
q
JA  
S
S
S
G
D
D
D
D
T = 100°C  
A
XXXX  
AYWWG  
G
WDFN8  
(m8FL)  
CASE 511AB  
Pulsed Drain Current  
T = 25°C, t = 10 ms  
I
DM  
A
A
p
Operating Junction and Storage Temperature  
T , T  
−55 to  
+175  
°C  
J
stg  
XXXX = Specific Device Code  
Source Current (Body Diode)  
I
52  
88  
A
S
A
Y
= Assembly Location  
= Year  
Single Pulse Drain−to−Source Avalanche  
E
AS  
mJ  
WW  
= Work Week  
Energy (I  
= 2.3 A)  
L(pk)  
G
= Pb−Free Package  
Lead Temperature for Soldering Purposes  
(1/8″ from case for 10 s)  
T
L
260  
°C  
(Note: Microdot may be in either location)  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information in the  
package dimensions section on page 5 of this data sheet.  
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)  
Parameter  
Symbol  
Value  
3.2  
Unit  
Junction−to−Case − Steady State (Note 3)  
Junction−to−Ambient − Steady State (Note 3)  
R
°C/W  
q
JC  
JA  
R
48  
q
1. The entire application environment impacts the thermal resistance values shown,  
they are not constants and are only valid for the particular conditions noted.  
2. Psi (Y) is used as required per JESD51−12 for packages in which  
substantially less than 100% of the heat flows to single case surface.  
2
3. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.  
4. Continuous DC current rating. Maximum current for pulses as long as 1  
second is higher but is dependent on pulse duration and duty cycle.  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
March, 2017 − Rev. 1  
NVTFS5C673NL/D  
 
NVTFS5C673NL  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)  
J
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
Drain−to−Source Breakdown Voltage  
V
V
GS  
= 0 V, I = 250 mA  
60  
V
(BR)DSS  
D
Drain−to−Source Breakdown Voltage  
Temperature Coefficient  
V
/
28  
(BR)DSS  
mV/°C  
T
J
Zero Gate Voltage Drain Current  
I
V
V
= 0 V,  
= 60 V  
T = 25°C  
10  
DSS  
GS  
DS  
J
mA  
T = 125°C  
J
250  
100  
Gate−to−Source Leakage Current  
ON CHARACTERISTICS (Note 5)  
Gate Threshold Voltage  
I
V
= 0 V, V = 20 V  
nA  
GSS  
DS  
GS  
GS  
V
V
= V , I = 250 mA  
1.2  
2.0  
V
GS(TH)  
DS  
D
Threshold Temperature Coefficient  
Drain−to−Source On Resistance  
V
/T  
−4.5  
8.1  
12  
mV/°C  
GS(TH)  
J
R
V
= 10 V  
I
I
= 25 A  
= 25 A  
9.8  
15  
DS(on)  
GS  
D
mW  
V
GS  
= 4.5 V  
D
Forward Transconductance  
CHARGES AND CAPACITANCES  
Input Capacitance  
g
V
=15 V, I = 25 A  
37  
S
FS  
DS  
D
C
880  
450  
11  
ISS  
Output Capacitance  
C
OSS  
C
RSS  
V
= 0 V, f = 1 MHz, V = 25 V  
pF  
GS  
DS  
Reverse Transfer Capacitance  
Total Gate Charge  
Q
V
GS  
= 4.5 V, V = 48 V; I = 25 A  
4.5  
9.5  
1.0  
2.0  
0.8  
2.9  
nC  
nC  
G(TOT)  
G(TOT)  
DS  
D
Total Gate Charge  
Q
V
GS  
= 10 V, V = 48 V; I = 25 A  
DS D  
Threshold Gate Charge  
Gate−to−Source Charge  
Gate−to−Drain Charge  
Plateau Voltage  
Q
G(TH)  
Q
nC  
V
GS  
GD  
GP  
V
GS  
= 10 V, V = 48 V; I = 25 A  
DS  
D
Q
V
SWITCHING CHARACTERISTICS (Note 6)  
Turn−On Delay Time  
t
6.0  
25  
d(ON)  
Rise Time  
t
r
V
GS  
= 10 V, V = 48 V,  
DS  
ns  
V
I
= 25 A, R = 2.5 W  
D
G
Turn−Off Delay Time  
t
16  
d(OFF)  
Fall Time  
t
f
2.0  
DRAIN−SOURCE DIODE CHARACTERISTICS  
Forward Diode Voltage  
V
SD  
T = 25°C  
J
0.9  
0.8  
28  
14  
14  
18  
1.2  
V
I
= 0 V,  
GS  
S
= 25 A  
T = 125°C  
J
Reverse Recovery Time  
Charge Time  
t
RR  
t
a
ns  
V
= 0 V, dIs/dt = 100 A/ms,  
GS  
I
S
= 25 A  
Discharge Time  
t
b
Reverse Recovery Charge  
Q
nC  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.  
6. Switching characteristics are independent of operating junction temperatures.  
www.onsemi.com  
2
 
NVTFS5C673NL  
TYPICAL CHARACTERISTICS  
40  
35  
30  
25  
20  
15  
10  
40  
V
= 3.6 V to 10 V  
V
DS  
= 3 V  
GS  
35  
30  
25  
20  
15  
10  
3.2 V  
3.0 V  
2.8 V  
T = 125°C  
J
2.6 V  
2.4 V  
T = 25°C  
J
5
0
5
0
T = −55°C  
J
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5 4.0  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
Figure 1. On−Region Characteristics  
Figure 2. Transfer Characteristics  
20  
18  
16  
14  
12  
10  
40  
T = 25°C  
J
I
= 25 A  
D
35  
30  
25  
20  
T = 25°C  
J
V
V
= 4.5 V  
GS  
15  
10  
5
= 10 V  
GS  
8
6
3
4
5
6
7
8
9
10  
0
10 20 30 40  
50 60 70  
80 90 100  
V
GS  
, GATE−TO−SOURCE VOLTAGE (V)  
I , DRAIN CURRENT (A)  
D
Figure 3. On−Resistance vs. Gate−to−Source  
Voltage  
Figure 4. On−Resistance vs. Drain Current and  
Gate Voltage  
2.25  
100,000  
I
V
= 25 A  
D
2.00  
1.75  
1.50  
1.25  
1.00  
T = 175°C  
J
= 10 V  
GS  
10,000  
1000  
100  
T = 125°C  
J
T = 85°C  
J
10  
1
0.75  
0.50  
−50 −25  
0
25  
50  
75  
100 125 150 175  
10  
20  
, DRAIN−TO−SOURCE VOLTAGE (V)  
DS  
30  
40  
50  
60  
T , JUNCTION TEMPERATURE (°C)  
V
J
Figure 5. On−Resistance Variation with  
Temperature  
Figure 6. Drain−to−Source Leakage Current  
vs. Voltage  
www.onsemi.com  
3
NVTFS5C673NL  
TYPICAL CHARACTERISTICS  
10  
10,000  
1000  
100  
10  
Q
V
= 0 V  
T
GS  
9
8
7
6
5
4
3
2
T = 25°C  
J
f = 1 MHz  
C
iss  
C
oss  
Q
gd  
Q
gs  
C
rss  
T = 25°C  
J
V
= 48 V  
= 25 A  
DS  
1
0
I
D
1
0
10  
20  
30  
40  
50  
60  
100  
100  
0
1
2
3
4
5
6
7
8
9
10  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Q , TOTAL GATE CHARGE (nC)  
g
Figure 7. Capacitance Variation  
Figure 8. Gate−to−Source vs. Total Charge  
100  
10  
100  
10  
V
= 0 V  
GS  
t
r
t
d(off)  
t
d(on)  
t
1
1
f
V
= 48 V  
= 25 A  
= 10 V  
DS  
I
D
T = 125°C  
T = 25°C  
J
T = −55°C  
J
V
GS  
J
0.1  
0.1  
1
10  
R , GATE RESISTANCE (W)  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
V
SD  
, SOURCE−TO−DRAIN VOLTAGE (V)  
G
Figure 9. Resistive Switching Time Variation  
vs. Gate Resistance  
Figure 10. Diode Forward Voltage vs. Current  
100  
10  
1000  
100  
10  
1 ms  
500 ms  
T
= 25°C  
J(initial)  
V
GS  
≤ 10 V  
1
T
= 100°C  
J(initial)  
Single Pulse  
= 25°C  
1
T
C
10 ms  
R
Limit  
0.1  
DS(on)  
Thermal Limit  
Package Limit  
dc  
0.01  
0.1  
0.1  
1
10  
1E−5  
1E−4  
T , TIME IN AVALANCHE (s)  
AV  
1E−3  
1E−2  
V
DS  
, DRAIN−TO−SOURCE VOLTAGE (V)  
Figure 11. Maximum Rated Forward Biased  
Safe Operating Area  
Figure 12. Maximum Drain Current vs. Time in  
Avalanche  
www.onsemi.com  
4
NVTFS5C673NL  
TYPICAL CHARACTERISTICS  
100  
10  
1
Duty Cycle = 50%  
20%  
10%  
5%  
2%  
1%  
0.1  
Single Pulse  
0.01  
0.000001 0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 13. Thermal Response  
DEVICE ORDERING INFORMATION  
Device  
†
Marking  
Package  
Shipping  
NVTFS5C673NLTAG  
673L  
WDFN8  
(Pb−Free)  
1500 / Tape & Reel  
1500 / Tape & Reel  
NVTFS5C673NLWFTAG  
73LW  
WDFN8  
(Pb−Free, Wettable Flanks)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
www.onsemi.com  
5
NVTFS5C673NL  
PACKAGE DIMENSIONS  
WDFN8 3.3x3.3, 0.65P  
CASE 511AB  
ISSUE D  
2X  
NOTES:  
0.20  
C
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: MILLIMETERS.  
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH  
PROTRUSIONS OR GATE BURRS.  
D
A
B
E
2X  
D1  
MILLIMETERS  
INCHES  
NOM  
0.030  
−−−  
0.012  
0.20  
C
8
1
7
6
5
4
DIM  
A
A1  
b
MIN  
0.70  
0.00  
0.23  
0.15  
NOM  
0.75  
−−−  
0.30  
0.20  
MAX  
MIN  
MAX  
0.031  
0.002  
0.016  
0.010  
0.80  
0.05  
0.40  
0.25  
0.028  
0.000  
0.009  
0.006  
4X  
q
E1  
c
0.008  
D
3.30 BSC  
3.05  
2.11  
3.30 BSC  
3.05  
1.60  
0.30  
0.65 BSC  
0.41  
0.80  
0.43  
0.130 BSC  
0.120  
0.083  
0.130 BSC  
0.120  
0.063  
0.012  
0.026 BSC  
0.016  
0.032  
0.017  
D1  
D2  
E
E1  
E2  
E3  
e
G
K
L
L1  
M
2.95  
1.98  
3.15  
2.24  
0.116  
0.078  
0.124  
0.088  
c
2
3
A1  
TOP VIEW  
0.116  
0.058  
0.009  
0.124  
0.068  
0.016  
2.95  
1.47  
0.23  
3.15  
1.73  
0.40  
0.10  
0.10  
C
C
A
C
6X  
e
0.30  
0.65  
0.30  
0.06  
1.40  
0
0.51  
0.95  
0.56  
0.20  
1.60  
0.012  
0.026  
0.012  
0.002  
0.055  
0
0.020  
0.037  
0.022  
0.008  
0.063  
SEATING  
PLANE  
0.13  
1.50  
−−−  
0.005  
0.059  
−−−  
DETAIL A  
SIDE VIEW  
DETAIL A  
q
12  
12  
_
_
_
_
8X b  
0.10  
0.05  
C
C
A
B
SOLDERING FOOTPRINT*  
8X  
e/2  
0.42  
0.65  
PITCH  
4X  
L
4X  
0.66  
1
8
4
5
PACKAGE  
OUTLINE  
K
E2  
M
E3  
3.60  
L1  
D2  
BOTTOM VIEW  
G
2.30  
0.57  
0.47  
0.75  
2.37  
3.46  
DIMENSION: MILLIMETERS  
*For additional information on our Pb−Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
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PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
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◊
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