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8N3PG10MBKI-161LFT

型号：

8N3PG10MBKI-161LFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

435 K

下载PDF手册
FemtoClock® NG Differential-to-3.3V,  
2.5V LVPECL Synthesizer  
8N3PG10MBKI-161  
Data Sheet  
General Description  
Features  
The 8N3PG10MBKI-161 is a very versatile programmable LVPECL  
synthesizer that can be used for OTN/SONET to Ethernet or 10GB  
Ethernet to OTN/SONET rate conversions. The conversion rate is  
pin-selectable and one of the four rates is supported at a time. In the  
default configuration, an input clock of 156.25MHz is converted to  
161.1328125MHz output (dithering off).  
• Fourth Generation FemtoClock® Next Generation (NG)  
technology  
• Footprint compatible with 5mm x 7mm differential oscillators  
• One differential LVPECL output pair  
• CLK, nCLK input pair can accept the following levels: HCSL,  
LVDS, LVPECL, LVHSTL  
The device uses IDT’s fourth generation FemtoClock® NG  
technology to deliver low phase noise clocks combined with low  
power consumption. The RMS phase jitter at 161.1328125MHz  
output frequency is 0.567ps (12kHz - 20MHz integration range).  
• Output frequency: 161.1328125MHz  
• RMS phase jitter, 12kHz – 20MHz = 0.567ps (typical)  
• Full 3.3V or 2.5V operating supply  
• -40°C to 85°C ambient operating temperature  
• Lead-free (RoHS 6) packaging  
Frequency Select Table  
FSEL[1:0]  
Input (MHz)  
156.25  
Output Frequency (MHz)  
161.1328125  
00  
01  
10  
11  
156.25  
161.1328125  
156.25  
161.1328125  
156.25  
161.1328125 (default)  
Block Diagram  
Pullup  
Pin Assignment  
OE  
FemtoClock® NG  
Pulldown  
CLK  
nCLK  
PFD  
&
Q
OE  
nc  
V
CC  
÷N  
PU/PD  
VCO  
nQ  
Q
V
÷M  
EE  
Pullup  
FSEL0  
FSEL1  
Control  
Logic  
Pullup  
8N3PG10MBKI-161  
10-Lead VFQFN  
5mm x 7mm x 1mm package body  
K Package  
Top View  
©2016 Integrated Device Technology, Inc  
1
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Pin Descriptions and Characteristics  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
Output enable. External pullup required for normal operation.  
LVCMOS/LVTTL interface levels.  
1
OE  
Pullup  
2
3
Reserved  
VEE  
Reserve  
Power  
Reserved pin.  
Negative supply pin.  
Pullup/  
Pulldown  
4
nCLK  
Input  
Inverting differential clock input. VCC/2 default when left floating  
5
6, 7  
8
CLK  
Q, nQ  
VCC  
Input  
Output  
Power  
Pulldown  
Non-inverting differential clock input.  
Differential output pair. LVPECL interface levels.  
Power supply pin.  
Feedback control input. Sets the output divider value to one of four values.  
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.  
9
FSEL0  
FSEL1  
Input  
Input  
Pullup  
Pullup  
Feedback control input. Sets the output divider value to one of four values.  
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.  
10  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
3.5  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
Input Pulldown Resistor  
RPULLUP  
RPULLDOWN  
51  
k  
51  
k  
Function Table  
Table 3. P, M, N Divider Function Table  
Input Frequency  
(MHz)  
Output Frequency  
(MHz)  
FSEL[1:0]  
0 0  
P
M
÷28.87500  
N
÷2  
÷2  
÷2  
÷2  
÷14  
÷14  
÷14  
÷14  
156.25  
156.25  
156.25  
156.25  
161.1328125  
161.1328125  
161.1328125  
161.1328125  
0 1  
÷28.87500  
÷28.87500  
÷28.87500  
1 0  
1 1 (default)  
©2016 Integrated Device Technology, Inc  
2
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
Inputs, VI  
3.63V  
-0.5V to VCC + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, JA  
39.2C/W (0 mps)  
-65C to 150C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 4A. Power Supply DC Characteristics, V = 3.3V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
VCC Power Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
3.3  
Maximum  
3.465  
Units  
V
3.135  
151  
189  
mA  
Table 4B. Power Supply DC Characteristics, V = 2.5V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
VCC Power Supply Voltage  
IEE Power Supply Current  
Test Conditions  
Minimum  
Typical  
2.5  
Maximum  
2.625  
Units  
V
2.375  
146  
182  
mA  
Table 4C. LVCMOS/LVTTL DC Characteristics, V = 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
VCC = 3.465V  
VCC = 2.625V  
VCC = 3.465V  
2
V
V
V
V
VIH Input High Voltage  
1.7  
-0.3  
-0.3  
VIL  
Input Low Voltage  
VCC = 2.625V  
0.7  
OE,  
FSEL[1:0]  
IIH  
Input High Current  
Input Low Current  
VCC = VIN = 3.465V or 2.625V  
5
µA  
µA  
OE,  
FSEL[1:0]  
IIL  
VCC = 3.465V or 2.625V, VIN = 0V  
-150  
©2016 Integrated Device Technology, Inc  
3
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Table 4D. Differential DC Characteristics, V = 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Input  
IIH  
CLK, nCLK  
CLK  
VCC = VIN = 3.465V or 2.625V  
150  
µA  
High Current  
VIN = 0V,  
VCC = 3.465V or 2.625V  
-5  
µA  
µA  
V
Input  
IIL  
Low Current  
VIN = 0V,  
VCC = 3.465V or 2.625V  
nCLK  
-150  
0.15  
VEE  
Peak-to-Peak Voltage;  
NOTE 1  
VPP  
1.3  
Common Mode Input  
Voltage; NOTE 1, 2  
VCMR  
VCC – 0.85  
V
NOTE 1: VIL should not be less than -0.3V.  
NOTE 2: Common mode input voltage is defined as the crossing point.  
Table 4E. LVPECL DC Characteristics, V = 3.3V 5% or 2.5V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Output High Voltage;  
NOTE 1  
VOH  
VCC – 1.4  
VCC – 0.8  
V
Output Low Voltage;  
NOTE 1  
VOL  
VCC – 2.0  
0.6  
VCC – 1.6  
1.0  
V
V
Peak-to-Peak Output  
Voltage Swing  
VSWING  
NOTE 1: Outputs termination with 50to VCC – 2V.  
©2016 Integrated Device Technology, Inc  
4
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
AC Electrical Characteristics  
Table 5A. AC Characteristics, V = 3.3V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
161.1328125  
18  
Maximum  
Units  
MHz  
ps  
fOUT  
Output Frequency  
tjit(cc)  
Cycle-to-Cycle Jitter; NOTE 1  
30  
RMS Phase Jitter (Random);  
NOTE 2, 3  
fOUT = 161.1328125MHz,  
Integration Range: 12kHz – 20MHz  
tjit(Ø)  
0.567  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
150  
49  
450  
51  
ps  
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 2: Refer to the Phase Noise plots.  
NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks.  
Table 5B. AC Characteristics, V = 2.5V 5%, V = 0V, T = -40°C to 85°C  
A
CC  
EE  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fMAX  
Output Frequency  
161.1328125  
MHz  
Cycle-to-Cycle Jitter;  
NOTE 1  
tjit(cc)  
18  
30  
ps  
ps  
RMS Phase Jitter (Random);  
NOTE 2, 3  
fOUT = 161.1328125MHz,  
Integration Range: 12kHz – 20MHz  
tjit(Ø)  
0.567  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
100  
49  
500  
51  
ps  
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 2: Refer to the Phase Noise plots.  
NOTE 3: Characterized using Rhode Schwartz SMA100A for input clocks.  
©2016 Integrated Device Technology, Inc  
5
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Typical Phase Noise at 161.1328125MHz  
Offset Frequency (Hz)  
©2016 Integrated Device Technology, Inc  
6
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Parameter Measurement Information  
2V  
2V  
SCOPE  
SCOPE  
V
Qx  
V
Qx  
CC  
CC  
nQx  
nQx  
VEE  
VEE  
-1.3V 0.165V  
-0.5V 0.125V  
3.3V LVPECL Output Load Test Circuit  
2.5V LVPECL Output Load Test Circuit  
V
CC  
nQ  
Q
nCLK  
CLK  
V
EE  
Differential Input Level  
Output Duty Cycle/Pulse Width/Period  
nQ  
Q
tcycle n  
tcycle n+1  
tjit(cc) = tcycle n – tcycle n+1  
|
|
1000 Cycles  
Cycle-to-Cycle Jitter  
RMS Phase Jitter  
©2016 Integrated Device Technology, Inc  
7
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Parameter Measurement Information, continued  
nQ  
Q
Output Rise/Fall Time  
©2016 Integrated Device Technology, Inc  
8
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VCC/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the V1in the center of the input voltage  
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,  
R1 and R2 value should be adjusted to set V1 at 1.25V. The values  
below are for when both the single ended swing and VCC are at the  
same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of  
two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50applications, R3 and R4 can be  
100. The values of the resistors can be increased to reduce the  
loading for slower and weaker LVCMOS driver. When using  
single-ended signaling, the noise rejection benefits of differential  
signaling are reduced. Even though the differential input can handle  
full rail LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some  
of the recommended components might not be used, the pads  
should be placed in the layout. They can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a differential signal.  
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
Recommendations for Unused Input Pins  
Inputs:  
LVCMOS Control Pins  
For the control pins that have internal pullup resistors; additional  
resistance is not required but can be added for additional protection.  
A 1kresistor can be used.  
©2016 Integrated Device Technology, Inc  
9
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
3.3V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 2A to 2E show interface examples  
for the CLK/nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. Please consult  
with the vendor of the driver component to confirm the driver  
termination requirements. For example, in Figure 2A, the input  
termination applies for IDT open emitter LVHSTL drivers. If you are  
using an LVHSTL driver from another vendor, use their termination  
recommendation.  
3.3V  
1.8V  
Zo = 50Ω  
CLK  
Zo = 50Ω  
nCLK  
Differential  
LVHSTL  
IDT  
LVHSTL Driver  
Input  
R1  
50Ω  
R2  
50Ω  
Figure 2A. CLK/nCLK Input Driven by an  
IDT Open Emitter LVHSTL Driver  
Figure 2B. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
3.3V  
3.3V  
*R3  
*R4  
CLK  
nCLK  
Differential  
Input  
HCSL  
Figure 2C. CLK/nCLK Input Driven by a  
3.3V LVPECL Driver  
Figure 2D. CLK/nCLK Input Driven by a  
3.3V HCSL Driver  
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver  
©2016 Integrated Device Technology, Inc  
10  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
2.5V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 3A to 3E show interface examples  
for the CLK/nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. Please consult  
with the vendor of the driver component to confirm the driver  
termination requirements. For example, in Figure 3A, the input  
termination applies for IDT open emitter LVHSTL drivers. If you are  
using an LVHSTL driver from another vendor, use their termination  
recommendation.  
2.5V  
1.8V  
Zo = 50  
CLK  
Zo = 50  
nCLK  
Differential  
LVHSTL  
Input  
R1  
50  
R2  
50  
IDT Open Emitter  
LVHSTL Driver  
Figure 3A. CLK/nCLK Input Driven by an  
IDT Open Emitter LVHSTL Driver  
Figure 3B. CLK/nCLK Input Driven by a  
2.5V LVPECL Driver  
2.5V  
2.5V  
Zo = 50  
Zo = 50  
*R3  
*R4  
33  
33  
CLK  
nCLK  
Differential  
Input  
HCSL  
R1  
50  
R2  
50  
*Optional R3 and R4 can be 0  
Figure 3C. CLK/nCLK Input Driven by a  
2.5V LVPECL Driver  
Figure 3D. CLK/nCLK Input Driven by a  
2.5V HCSL Driver  
Figure 3E. CLK/nCLK Input Driven by a 2.5V LVDS Driver  
©2016 Integrated Device Technology, Inc  
11  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale  
©2016 Integrated Device Technology, Inc  
12  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
designed to drive 50transmission lines. Matched impedance  
techniques should be used to maximize operating frequency and  
minimize signal distortion. Figures 5A and 5B show two different  
layouts which are recommended only as guidelines. Other suitable  
clock layouts may exist and it would be recommended that the board  
designers simulate to guarantee compatibility across all printed  
circuit and clock component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible signals. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are  
3.3V  
R3  
125  
R4  
125  
3.3V  
3.3V  
Zo = 50  
+
_
Input  
Zo = 50  
R1  
84  
R2  
84  
Figure 5A. 3.3V LVPECL Output Termination  
Figure 5B. 3.3V LVPECL Output Termination  
©2016 Integrated Device Technology, Inc  
13  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Termination for 2.5V LVPECL Outputs  
Figure 6A and Figure 6C show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating  
50to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to  
ground level. The R3 in Figure 6B can be eliminated and the  
termination is shown in Figure 6C.  
2.5V  
VCC = 2.5V  
2.5V  
2.5V  
VCC = 2.5V  
50Ω  
R1  
250Ω  
R3  
250Ω  
+
–
50Ω  
50Ω  
+
–
50Ω  
2.5V LVPECL Driver  
R1  
50Ω  
R2  
50Ω  
2.5V LVPECL Driver  
R2  
62.5Ω  
R4  
62.5Ω  
R3  
18Ω  
Figure 6A. 2.5V LVPECL Driver Termination Example  
Figure 6B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCC = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
50Ω  
R2  
50Ω  
Figure 6C. 2.5V LVPECL Driver Termination Example  
©2016 Integrated Device Technology, Inc  
14  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Schematic Example  
Figure 7 shows an example IDT8N3PG10MBKI-161 application  
schematic in which the device is operated at VCC = +3.3V. The  
schematic example focuses on functional connections and is  
intended as an example only and may not represent the exact user  
configuration. Refer to the pin description and functional tables in  
the datasheet to ensure the logic control inputs are properly set. For  
example OE, FSEL0 and FSEL1 can be configured from an FPGA  
instead of pull up and pull down resistors as shown.  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise, so to achieve optimum jitter  
performance isolation of the VCC pin from power supply is required.  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1µF capacitor on the VCC pin must be placed on the device side  
with direct return to the ground plane though vias. The remaining  
filter components can be on the opposite side of the PCB.  
The input is driven by a DC coupled LVDS driver, though HCSL and  
LVPECL are also compatible with the IDT CLK, nCLK differential  
inputs. There are two LVPECL termination options shown; the  
simple three resistor termination of R5, R6 and R7 and an AC  
termination, used when coupling the IDT8N3PG10MBKI-161  
LVPECL output stage to a different logic family receiver. Note that  
the pull down resistors R8 and R9 that bias the LVPECL output  
stage are to be placed on the IDT8N3PG10MBKI-161 side of the  
PCB directly adjacent to pins 6 and 7 for best signal integrity. Most  
often each output of a 3.3V LVPECL driver will be DC terminated  
with a 130pull up and an 82pull down resistor at the 3.3V  
LVPECL receiver. This is also a valid option with the  
Power supply filter component recommendations are a general  
guideline to be used for reducing external noise from coupling into  
the devices. The filter performance is designed for a wide range of  
noise frequencies. This low-pass filter starts to attenuate noise at  
approximately 10kHz. If a specific frequency noise component is  
known, such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if required,  
additional filtering be added. Additionally, good general design  
practices for power plane voltage stability suggests adding bulk  
capacitance in the local area of all devices.  
IDT8N3PG10MBKI-161, though the three resistor termination is  
simpler in regard to component count and layout as well as lower in  
power dissipation.  
NOTE: This device package has an ePAD that is connected to  
ground internally. The ePAD should be connected to GND on the  
PCB through vias in order to improve heat dissipation.  
©2016 Integrated Device Technology, Inc  
15  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Logic Control Input Examples  
Set Logic Set Logic  
V CC  
V CC  
Input to'1'  
Input to'0'  
3. 3V  
R U1  
1K  
R U2  
N ot I nstal l  
F B 1  
V C C  
2
1
C 4  
10u F  
B LM18B B 221S N1  
To Logic  
Input  
pi ns  
To L og ic  
In pu t  
pi ns  
C5  
0. 1uF  
R D1  
N ot Inst al l  
R D2  
1K  
Place 0.1uF bypass cap directly adjacent to the VCC pin  
and on the component side of the circuit board.  
VC C  
C3  
U 1  
0. 1uF  
F S EL0  
F S EL1  
9
10  
FS E L0  
FS E L1  
1
2
O E  
Z o  
Z o  
=
=
50 Ohm  
OE  
6
7
Q
Q
+
Reserv ed  
Zo  
Zo  
=
=
50 O hm  
50 O hm  
50 Ohm  
5
4
nQ  
CLK  
nQ  
-
R10  
100  
+3. 3V PE CL R eceiv er  
nCLK  
R7  
50  
R5  
50  
LVD S D ri ver  
R 6  
50  
C7  
Z o = 50 Ohm  
Q
0. 1u  
V CC_ Rx  
R8  
150  
R 1  
R3  
R4  
50  
+
-
C6  
0. 01uF  
R 2  
50  
R eceiv er  
C8  
Z o = 50 Ohm  
nQ  
0. 1u  
R9  
150  
Alternate AC coupled LVPECL Termination  
Select R3 and R4 to center the LVPECL swing in the c ommon  
mode center of t he Receiver.  
Place R8 and R9 pull down resistors on the U1 side of the board at  
pins 6 and 7 respectively.  
Figure 7. 8N3PG10MBKI-161 Schematic Layout Example  
©2016 Integrated Device Technology, Inc  
16  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the 8N3PG10MBKI-161.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the 8N3PG10MBKI-161 is the sum of the core power plus the power dissipation due to loading.  
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipation due to loading.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 189mA = 654.885mW  
Power (outputs)MAX = 32mW/Loaded Output pair  
Total Power_MAX (3.465V, with all outputs switching) = 654.885mW + 32mW = 686.885mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 39.2°C/W per Table 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.687W * 39.2°C/W = 111.9°C. This is well below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 6. Thermal Resistance for 10 Lead VFQFN, Forced Convection  
JA  
JA by Velocity  
Meters per Second  
0
Multi-Layer PCB, JEDEC Standard Test Boards  
39.2°C/W  
©2016 Integrated Device Technology, Inc  
17  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.  
The LVPECL output driver circuit and termination are shown in Figure 8.  
VCC  
Q1  
VOUT  
RL  
50Ω  
VCC - 2V  
Figure 8. LVPECL Driver Circuit and Termination  
To calculate power dissipation due to loading, use the following equations which assume a 50load, and a termination voltage of VCC – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V  
(VCC_MAX – VOH_MAX) = 0.8V  
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V  
(VCC_MAX – VOL_MAX) = 1.6V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =  
[(2V – 0.8V)/50] * 0.8V = 19.2mW  
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =  
[(2V – 1.6V)/50] * 1.6V = 12.8mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW  
©2016 Integrated Device Technology, Inc  
18  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Reliability Information  
Table 7. vs. Air Flow Table for a 10 Lead VFQFN  
JA  
JA vs. Air Flow  
Meters per Second  
0
Multi-Layer PCB, JEDEC Standard Test Boards  
39.2°C/W  
Transistor Count  
The transistor count for 8N3PG10MBKI-161 is: 42,520  
Package Dimensions  
Table 8. Package Dimensions for 10-Lead VFQFN  
VNJR-1  
All Dimensions in Millimeters  
Symbol  
N
Minimum  
Nominal  
10  
Maximum  
A
0.80  
0
0.90  
1.00  
0.05  
0.45  
1.45  
A1  
b1  
b2  
D
0.02  
0.35  
1.35  
0.40  
1.40  
5.00 Basic  
1.70  
D2  
E
1.55  
3.55  
1.80  
3.80  
7.00 Basic  
3.70  
E2  
e1  
1.0  
e2  
2.54  
L1  
L2  
N
0.45  
1.0  
10  
0.55  
0.65  
1.20  
1.10  
ND  
NE  
aaa  
bbb  
ccc  
2
3
0.15  
0.10  
0.10  
©2016 Integrated Device Technology, Inc  
19  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Package Outline  
Package Outline - K Suffix for 10-Lead VFQFN  
D
e1  
B
NX L2  
7
NX b1  
bbb  
C A B  
0.1mm  
4
INDEX AREA  
(D/2 xE/2)  
→
0.1mm  
→
7
NX b2  
bbb  
C A B  
4
INDEX AREA  
(D/2 xE/2)  
PIN#1 ID  
9
TOP VIEW  
aaa C 2x  
D2  
BOTTOM VIEW  
ccc C  
C
SEATING  
PLANE  
8
SIDE VIEW  
0.08 C  
Bottom View w/Type A ID  
Bottom View w/Type C ID  
2
1
2
1
CHAMFER  
RADIUS  
N N-1  
4
N N-1  
4
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:  
1. Type A: Chamfer on the paddle (near pin 1)  
2. Type C: Mouse bite on the paddle (near pin 1)  
NOTE: The following package mechanical drawing is a generic  
drawing that applies to any pin count VFQFN package. This drawing  
is not intended to convey the actual pin count or pin layout of this  
device. The pin count and pinout are shown on the front page. The  
package dimensions are in Table 8.  
©2016 Integrated Device Technology, Inc  
20  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Ordering Information  
Table 9. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
-40C to 85C  
-40C to 85C  
8N3PG10MBKI-161LF  
8N3PG10MBKI-161LFT  
ICS10MBI161L  
ICS10MBI161L  
“Lead-Free” 10 Lead VFQFN  
“Lead-Free” 10 Lead VFQFN  
Tray  
Tape & Reel  
©2016 Integrated Device Technology, Inc  
21  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Revision History  
Revision Date  
Description of Change  
▪ Removed ICS in the part number where needed.  
▪ Updated header and footer.  
January 28, 2016  
©2016 Integrated Device Technology, Inc  
22  
Revision A January 28, 2016  
8N3PG10MBKI-161 Data Sheet  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
www.idt.com/go/support  
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications  
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein  
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,  
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners.  
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.  
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.  
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