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LY6251216AML-45SL

型号：

LY6251216AML-45SL

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

12 页

PDF大小：

288 K

下载PDF手册
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Description  
Initial Issue  
Deleted WRITE CYCLE Notes :  
1.WE#,CE#, LB#, UB# must be high during all address  
transitions.  
Issue Date  
Nov.16.2015  
Jun.29.2016  
In page 7  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
FEATURES  
GENERAL DESCRIPTION  
The LY6251216A is a 8,388,608-bit low power CMOS  
static random access memory organized as 524,288  
words by 16 bits. It is fabricated using very high  
performance, high reliability CMOS technology. Its  
standby current is stable within the range of operating  
temperature.  
„ Fast access time : 45ns  
„ Low power consumption:  
Operating current : 35mA (TYP.)  
Standby current : 2μA (TYP.) LL-version  
„ Single 4.5V ~ 5.5V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
„ Tri-state output  
„ Data byte control : LB# (DQ0 ~ DQ7)  
UB# (DQ8 ~ DQ15)  
The LY6251216A is well designed for low power  
application, and particularly well suited for battery  
back-up nonvolatile memory application.  
„ Data retention voltage : 1.5V (MIN.)  
„ Green package available  
„ Package : 44-pin 400 mil TSOP-II  
The LY6251216A operates from a single power  
supply of 4.5V ~ 5.5V and all inputs and outputs are  
fully TTL compatible  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
LY6251216A  
Operating  
Temperature  
0 ~ 70℃  
V
CC Range  
Standby(ISB1,TYP.) Operating(ICC,TYP.)  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
45ns  
45ns  
2µA(SL)  
2µA(SL)  
35mA  
35mA  
-40 ~ 85℃  
LY6251216A(I)  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0 - A18  
Vcc  
Vss  
DQ0 – DQ15 Data Inputs/Outputs  
CE#  
WE#  
OE#  
LB#  
UB#  
VCC  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Power Supply  
512Kx16  
MEMORY ARRAY  
A0-A18  
DECODER  
VSS  
Ground  
DQ0-DQ7  
Lower Byte  
I/O DATA  
CIRCUIT  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
CE#  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
PIN CONFIGURATION  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 6.5  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
1
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is  
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
TRUTH TABLE  
I/O OPERATION  
MODE  
CE# OE# WE# LB# UB#  
SUPPLY CURRENT  
DQ0-DQ7  
DQ8-DQ15  
H
X
X
X
H
H
L
L
L
X
X
X
X
X
X
H
L
X
L
H
L
L
X
H
X
L
H
L
L
H
L
L
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
High – Z  
DOUT  
DIN  
High – Z  
DIN  
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
DOUT  
High – Z  
DIN  
ISB,ISB1  
ICC,ICC1  
ICC,ICC1  
Standby  
L
L
L
L
L
L
L
L
H
H
H
H
H
L
Output Disable  
Read  
Write  
L
L
H
L
ICC,ICC1  
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDIT  
MIN.  
4.5  
2.4  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
VCC  
5.0  
5.5  
VCC+0.3  
0.8  
V
V
V
*1  
VIH  
VIL  
-
-
*2  
- 0.2  
Input Leakage Current  
ILI  
- 1  
-
1
A
≧
≧
VSS  
µ
µ
VCC  
VIN  
Output Leakage  
Current  
Output High Voltage  
Output Low Voltage  
VCC ≧ VOUT ≧ VSS  
Output Disabled  
IOH = -1mA  
ILO  
- 1  
-
1
A
VOH  
VOL  
2.4  
-
-
-
-
V
V
IOL = 2mA  
0.4  
Cycle time = Min.  
CE# = VIL, II/O = 0mA  
Other pins at VIL or VIH  
ICC  
-
35  
50  
mA  
Average Operating  
Power supply Current  
Cycle time = 1 s  
µ
ICC1  
ISB  
≦
-
-
6
12  
2
mA  
mA  
CE# 0.2V, II/O = 0mA  
Other pins at 0.2V or VCC-0.2V  
CE# = VIH  
Other pins at VIL or VIH  
0.2  
Standby Power  
Supply Current  
*5  
℃
-SL/SLI @40  
-
-
-
2
2
2
8
15  
20  
A
µ
A
µ
A
µ
CE# ≧VCC-0.2V  
Other pins at 0.2V -SL  
or VCC-0.2V  
ISB1  
-SLI  
Notes:  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25  
5. This parameter is measured at VCC = 3.0V  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
tRC  
UNIT  
LY6251216A-45  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
45  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
45  
45  
25  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
-
*
*
*
10  
5
-
-
10  
-
-
15  
15  
-
45  
20  
-
tOHZ  
tOH  
tBA  
*
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
tBLZ  
*
*
-
10  
(2) WRITE CYCLE  
PARAMETER  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
LY6251216A-45  
MIN.  
45  
40  
40  
0
MAX.  
Write Cycle Time  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
-
tWP  
tWR  
tDW  
tDH  
tOW  
35  
0
-
-
20  
0
-
-
*
5
-
tWHZ  
*
-
35  
15  
-
tBW  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOLZ  
tBLZ  
tCLZ  
tOHZ  
tBHZ  
tCHZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE#is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.  
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.  
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ  
.
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 1 (WE# Controlled) (1,2,4,5)  
tWC  
Address  
tAW  
CE#  
tCW  
tBW  
LB#,UB#  
WE#  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
Dout  
(4)  
(4)  
tDW  
tDH  
Din  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,4,5)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 3 (LB#,UB# Controlled)  
(1,4 ,5)  
tWC  
Address  
tAW  
tWR  
CE#  
tAS  
tCW  
tBW  
LB#,UB#  
WE#  
tWP  
tWHZ  
High-Z  
Dout  
Din  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.  
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed  
on the bus.  
3.During this period, I/O pins are in the output state, and input signals must not be applied.  
4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data Retention  
SYMBOL  
TEST CONDITION  
CE#≧VCC - 0.2V  
MIN. TYP. MAX. UNIT  
VDR  
1.5  
-
5.5  
8
V
℃
-SL/SLI@40  
-SL  
-
-
-
0.5  
0.5  
0.5  
A
VCC = 1.5V  
CE# ≧VCC-0.2V  
µ
µ
µ
Data Retention Current  
IDR  
15  
20  
A
A
Other pins at 0.2V or VCC-0.2V  
-SLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC*  
tRC*  
= Read Cycle Time  
DATA RETENTION WAVEFORM  
Low VCC Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low VCC Data Retention Waveform (2) (LB#, UB# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
LB#,UB# ≧ Vcc-0.2V  
VIH  
LB#,UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
PACKAGE OUTLINE DIMENSION  
Ⅱ
44-pin 400mil TSOP-  
Package Outline Dimension  
DIMENSIONS IN MILLMETERS  
DIMENSIONS IN MILS  
SYMBOLS  
MIN.  
-
NOM.  
-
MAX.  
1.20  
0.15  
1.05  
0.45  
0.21  
18.618  
12.014  
10.363  
-
MIN.  
NOM.  
-
MAX.  
A
A1  
A2  
b
-
47.2  
5.9  
41.3  
17.7  
8.3  
733  
473  
408  
-
0.05  
0.95  
0.30  
0.12  
18.212  
11.506  
9.957  
-
0.10  
1.00  
-
2.0  
37.4  
11.8  
4.7  
717  
453  
392  
-
3.9  
39.4  
-
c
-
-
D
18.415  
11.760  
10.160  
0.800  
0.50  
0.805  
-
725  
463  
400  
31.5  
19.7  
31.7  
-
E
E1  
e
L
0.40  
-
0.60  
-
15.7  
-
23.6  
-
ZD  
y
-
0o  
0.076  
6o  
-
0o  
3
6o  
3o  
3o  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
ORDERING INFORMATION  
Power  
Type  
Package Type Access Time  
(Speed)(ns)  
Temperature  
Packing  
Type  
Lyontek Item No.  
Range(℃)  
44-Pin 400mil  
45  
Tray  
LY6251216AML-45SL  
LY6251216AML-45SLT  
LY6251216AML-45SLI  
LY6251216AML-45SLIT  
Special Ultra  
Low Power  
℃
℃
~70  
0
TSOP-II  
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY6251216A  
512K X 16 BIT LOW POWER CMOS SRAM  
Rev. 1.1  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
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