请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

5V41234NLG8

型号：

5V41234NLG8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

13 页

PDF大小：

181 K

下载PDF手册
DATASHEET  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
5V41234  
Typical Applications  
Features  
One output synthesizer for PCIe Gen1/2/3  
• 3 x 3 mm 16-QFN package; very small board footprint  
• Spread-spectrum capable; reduces EMI  
Description  
• Outputs can be terminated to LVDS; can drive a wider  
variety of devices  
The 5V41234 is a PCIe Gen2/3 compliant spread spectrum  
capable clock generator. The device has 1 differential  
HCSL output and can be used in communication or  
embedded systems to substantially reduce  
electro-magnetic interference (EMI). Spread spectrum can  
be enabled via a select pin.  
• Spread enable via pin selection; no software required to  
configure device  
• Industrial temperature range available; supports  
demanding embedded applications  
Key Specifications  
Output Features  
• Cycle-to-cycle jitter < 100 ps  
• 1 - 0.7V current mode differential HCSL output pairs  
• PCIe Gen2 phase jitter < 3.0ps RMS  
• PCIe Gen3 phase jitter < 1.0ps RMS  
Block Diagram  
VDD  
Control  
Logic  
SS1  
CLK  
Phase Lock  
Loop  
CLK  
X1  
X2  
Clock  
Buffer/  
Crystal  
Oscillator  
25 MHz  
crystal /clock  
Crystal Tuning Capacitors  
RR (IREF)  
GND  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
1
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Pin Assignment  
Spread Spectrum Select Table  
SS1  
Spread%  
-0.5% down  
No spread  
0
1
13  
GND  
X1  
1
CLK  
CLK  
X2  
GND  
VDDA  
9
NC  
5
16-pin QFN  
Pin Descriptions  
Pin  
Number  
Pin  
Name  
Pin Type  
Power Connect to ground.  
Pin Description  
1
2
3
GND  
X1  
XI  
Crystal or clock input. Connect to 25MHz crystal or single-ended clock.  
X2  
XO  
Crystal connection. Connect to parallel mode crystal. Leave floating if X1 is driven by  
single-ended clock.  
4
5
6
7
NC  
–
No connect.  
GND  
SS1  
IREF  
Power Connect to ground.  
Input  
Spread Select 1. See table above. Internal pull-up resistor.  
Output 475precision resistor must be attached to this pin, which is connected to internal  
current source.  
8
NC  
VDDA  
GND  
CLK  
CLK  
NC  
–
No connect.  
9
Power Connect to 3.3V and filter as analog supply.  
Power Connect to ground.  
10  
11  
12  
13  
14  
15  
16  
Output HCSL complementary output clock.  
Output HCSL true output clock.  
–
–
No connect.  
No connect.  
NC  
VDD  
NC  
Power Connect to 3.3V for OSC and digital circuits.  
No connect.  
–
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
2
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Applications Information  
External Components  
A minimum number of external components are required for  
proper operation.  
Output Structures  
6*IREF  
IREF  
=2.3 mA  
Decoupling Capacitors  
Decoupling capacitors of 0.01F should be connected  
between VDD and the ground plane (pin 4) as close to the  
VDD pin as possible. Do not share ground vias between  
components. Route power from power source through the  
capacitor pad and then into IDT pin.  
Crystal  
A 25 MHz fundamental mode parallel resonant crystal with  
See Layout  
Guidelines  
C = 16pF should be used. This crystal must have less than  
L
RR 475  
300 ppm of error across temperature in order for the  
5V41234 to meet PCI Express specifications.  
General PCB Layout Recommendations  
Crystal Capacitors  
For optimum device performance and lowest output phase  
noise, the following guidelines should be observed.  
Crystal capacitors are connected from pins X1 to ground  
and X2 to ground to optimize the accuracy of the output  
frequency.  
1. Each 0.01µF decoupling capacitor should be mounted on  
the component side of the board as close to the VDD pin as  
possible.  
C = Crystal’s load capacitance in pF  
L
Crystal Capacitors (pF) = (C - 8) * 2  
L
2. No vias should be used between decoupling capacitor  
and VDD pin.  
For example, for a crystal with a 16 pF load cap, each  
external crystal cap would be 16pF. (16-8)*2=16.  
3. The PCB trace to VDD pin should be kept as short as  
possible, as should the PCB trace to the ground via.  
Distance of the ferrite bead and bulk decoupling from the  
device is less critical.  
Current Source (Iref) Reference Resistor - R  
R
If board target trace impedance (Z) is 50, then R = 475  
R
(1%), providing IREF of 2.32mA. The output current (I ) is  
equal to 6*IREF.  
OH  
4. An optimum layout is one with all components on the  
same side of the board, minimizing vias through other signal  
layers (any ferrite beads and bulk decoupling capacitors can  
be mounted on the back). Other signal traces should be  
routed away from the 5V41234.This includes signal traces  
just underneath the device, or on layers adjacent to the  
ground plane layer used by the device.  
Output Termination  
The PCI-Express differential clock outputs of the 5V41234  
are open source drivers and require an external series  
resistor and a resistor to ground. These resistor values and  
their allowable locations are shown in detail in the  
PCI-Express Layout Guidelines section.  
The 5V41234 can also be terminated to LVDS compatible  
voltage levels. See Layout Guidelines section.  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
3
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Layout Guidelines for PCI Express  
PCIe Reference Clock  
Common Recommendations for Differential Routing  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs  
Rt  
49.9  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
0.25 to 14 max  
0.225 min to 12.6 max  
inch  
inch  
2
2
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Down Device  
REF_CLK Input  
L3' L3  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
Rt  
Rt  
HCSL Output Buffer  
PCI Express  
Add-in Board  
REF_CLK Input  
L3' L3  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
4
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Layout Guidelines for LVDS and Other Applications  
Alternative Termination for LVDS and other Common Differential Signals (figure 3)  
Vdiff  
0.45v  
0.58  
0.80  
0.60  
Vp-p  
0.22v  
0.28  
0.40  
0.3  
Vcm  
1.08  
0.6  
0.6  
1.2  
R1  
33  
33  
33  
33  
R2  
R3  
R4  
Note  
150  
78.7  
78.7  
174  
100  
137  
none  
140  
100  
100  
100  
100  
ICS874003i-02 input compatible  
Standard LVDS  
R1a = R1b = R1  
R2a = R2b = R2  
Figure 3  
L2  
L1  
R3  
R4  
R1a  
R1b  
L4  
L4'  
L2'  
L1'  
R2a  
R2b  
HCSL Output Buffer  
Down Device  
REF_CLK Input  
L3'  
L3  
Cable Connected AC Coupled Application (figure 4)  
Component  
Value  
Note  
R5a, R5b  
R6a, R6b  
Cc  
8.2K 5%  
1K 5%  
0.1 µF  
Vcm  
0.350 volts  
Figure 4  
3.3 Volts  
R5a  
R5b  
R6b  
Cc  
Cc  
L4  
L4'  
R6a  
PCIe Device  
REF_CLK Input  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
5
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Typical PCI-Express (HCSL) Waveform  
700 mV  
0
500 ps  
500 ps  
tOR  
tOF  
0.525 V  
0.175 V  
0.525 V  
0.175 V  
Typical LVDS Waveform  
1325 mV  
1000 mV  
500 ps  
500 ps  
tOR  
tOF  
1250 mV  
1150 mV  
1250 mV  
1150 mV  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
6
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 5V41234. These ratings are stress ratings  
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of  
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product  
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.  
Item  
Rating  
Supply Voltage, VDD, VDDA  
5.5V  
All Inputs and Outputs  
-0.5V to VDD+0.5V  
0 to +70C  
Ambient Operating Temperature (commercial)  
Ambient Operating Temperature (industrial)  
Storage Temperature  
-40 to +85C  
-65 to +150C  
125C  
Junction Temperature  
Soldering Temperature  
260C  
ESD Protection (Input)  
2000V min. (HBM)  
DC Electrical Characteristics  
Unless stated otherwise, VDD = 3.3V ±±%, Ambient Temperature -40 to +85C  
Parameter  
Symbol  
Conditions  
Min.  
3.135  
2.2  
Typ.  
Max.  
3.465  
Units  
Supply Voltage  
V
1
Input High Voltage  
V
VDD +0.3  
V
V
IH  
1
Input Low Voltage  
V
VSS-0.3  
-5  
0.8  
5
IL  
2
Input Leakage Current  
I
0 < Vin < VDD  
A  
mA  
pF  
pF  
nH  
k  
k  
IL  
Operating Supply Current  
Input Capacitance  
Output Capacitance  
Pin Inductance  
I
2pF load  
70  
7
DD  
C
Input pin capacitance  
Output pin capacitance  
IN  
C
6
OUT  
L
5
PIN  
Output Resistance  
Pull-up Resistor  
Rout  
CLK outputs  
SS1  
3.0  
R
100  
PUP  
1. Single edge is monotonic when transitioning through region.  
2. Inputs with pull-ups/-downs are not included.  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
7
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
AC Electrical Characteristics - CLK/CLK  
Unless stated otherwise, VDD=3.3V ±±%, Ambient Temperature -40 to +85C  
Parameter  
Input Frequency  
Symbol  
Conditions  
Min.  
Typ.  
25  
Max.  
Units  
MHz  
MHz  
mV  
mV  
mV  
mV  
ps  
Output Frequency  
100  
700  
0
1,2  
Output High Voltage  
V
660  
-150  
250  
850  
27  
OH  
1,2  
Output Low Voltage  
V
OL  
1,2  
Crossing Point Voltage  
Crossing Point Voltage  
Absolute  
350  
40  
550  
140  
100  
700  
700  
125  
55  
1,2,4  
Variation over all edges  
1,3  
Jitter, Cycle-to-Cycle  
25  
1,2  
Rise Time  
t
From 0.175V to 0.525V  
From 0.525V to 0.175V  
175  
175  
332  
344  
75  
ps  
OR  
1,2  
Fall Time  
t
ps  
OF  
1,2  
Rise/Fall Time Variation  
ps  
1,3  
Duty Cycle  
45  
51  
%
Stabilization Time  
t
From power-up VDD = 3.3V  
1.2  
3.0  
3.0  
ms  
STABLE  
Spread Change Time  
t
Settling period after spread change  
ms  
SPREAD  
1
2
3
4
Test setup is R =33 ohms R =50 ohms with 2pF, R = 475(1%).  
S
P
R
Measurement taken from a single-ended waveform.  
Measurement taken from a differential waveform.  
Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.  
Electrical Characteristics - Differential Phase Jitter  
TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%  
SPEC  
PARAMETER  
Symbol  
tjphaseG1  
Conditions  
PCIe Gen 1  
Min  
Typ  
28  
Max  
86  
Units Notes  
ps (p-p) 1,2,3  
PCIe Gen 2  
10kHz < f < 1.5MHz  
PCIe Gen 2  
ps  
tjphaseG2Lo  
tjphaseG2High  
tjphaseG3  
1.1  
1.8  
3
3.1  
1
1,2,3  
(RMS)  
Jitter, Phase  
ps  
(RMS)  
1,2,3  
1.5MHz < f < Nyquist (50MHz)  
ps  
PCIe Gen 3  
0.48  
1,2,3  
(RMS)  
1Guaranteed by design and characterization, not 100% tested in production.  
2See http://www.pcisig.com for complete specs  
3Applies to 100MHz, spread off and 0.5% down spread only.  
Thermal Characteristics  
Parameter  
Symbol  
Conditions  
Min.  
Typ. Max. Units  
Thermal Resistance Junction to  
Ambient  
Still air  
69.4  
60.7  
54.4  
9.7  
C/W  
C/W  
C/W  
C/W  
JA  
JA  
JA  
JC  
1 m/s air flow  
2.5 m/s air flow  
Thermal Resistance Junction to Case  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
8
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Marking Diagrams  
XXX  
XXX  
YWW$  
234G  
YWW$  
234GI  
Notes:  
1. Line 1: “XXX” is the lot traceability (last numeric character of the assembly lot number).  
2. Line 2: “YYW” – date code; “$” – assembly location.  
3. Line 3: truncated IDT part number.  
4. “G” designates RoHS compliant package.  
5. “I” within the part number indicates industrial temperature range.  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
9
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Ordering Information  
Part / Order Number  
5V41234NLG  
Marking  
See Page 9  
Shipping Packaging  
Tubes  
Package  
Temperature  
0 to +70C  
3 x 3 mm 16-QFN  
3 x 3 mm 16-QFN  
3 x 3 mm 16-QFN  
3 x 3 mm 16-QFN  
5V41234NLG8  
Tape and Reel  
Tubes  
0 to +70C  
5V41234NLGI  
-40 to +85C  
-40 to +85C  
5V41234NLGI8  
Tape and Reel  
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Revision History  
Rev.  
A
Date  
Originator Description of Change  
09/26/11  
11/22/11  
RDW  
RDW  
Initial release.  
B
1. Changed title to “1 Output PCIe GEN1/2/3 Synthesizer”  
2. Updated Differential Phase Jitter table.  
B
C
03/20/14  
05/05/17  
S. Lou  
C.P.  
Corrected typo in shipping packaging section of Ordering Information table - changed  
“Trays” to “Tubes”.  
1. Updated package drawing to the latest NLG16 version.  
2. Updated legal disclaimer.  
IDT® 1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
12  
5V41234  
MAY 5, 2017  
5V41234  
1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
For Tech Support  
www.idt.com/go/support  
408-284-8200  
Fax: 408-284-2775  
www.idt.com/go/sales  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications  
described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an  
independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or  
warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or  
non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or  
any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an  
IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an  
express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks  
used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated  
Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		5V40501DCG LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DCG8 LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DCGI LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DCGI8 LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DVG LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DVG8 LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DVGI LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40501DVGI8 LOCO ™ PLL时钟乘法器[ LOCO™ PLL CLOCK MULTIPLIER ] 9 页

IDT

 		5V40512DCGI [ Clock Generator, 133.3MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 ] 9 页

IDT

 		5V40512DCGI8 [ Clock Generator, 133.3MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 ] 9 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.191197s