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LY62L102616ALL-70SLIT

型号：

LY62L102616ALL-70SLIT

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

13 页

PDF大小：

169 K

下载PDF手册
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Description  
Initial Issue  
Issue Date  
Jan. 09. 2012  
July.08. 2013  
Correct typo error on the column “UB#”, “LB#” of truth table  
for row “Byte Read” “Byte Write” and “Output Disable” at  
page 4: “X” revised to be “L”  
Revised ORDERING INFORMATION in page 11  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
FEATURES  
GENERAL DESCRIPTION  
The LY62L102616A is a 16,777,216-bit low power  
CMOS static random access memory organized as  
1,048,576 words by 16 bits or 2,097,152 words by 8  
bits. It is fabricated using very high performance,  
high reliability CMOS technology. Its standby current  
is stable within the range of operating temperature.  
„ Fast access time : 55/70ns  
„ Low power consumption:  
Operating current : 45/30mA (TYP.)  
Standby current : 4μA (TYP.) SL-version  
„ Single 2.7V ~ 3.6V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
The LY62L102616A is well designed for low power  
application, and particularly well suited for battery  
back-up nonvolatile memory application.  
„ Tri-state output  
„ Data byte control :  
(i) BYTE# fixed to VCC  
LB# controlled DQ0 ~ DQ7  
UB# controlled DQ8 ~ DQ15  
(ii) BYTE# fixed to VSS  
The LY62L102616A operates from a single  
power supply of 2.7V ~ 3.6V and all inputs and  
outputs are fully TTL compatible  
DQ15 used as address pin, while  
DQ8~DQ14 pins not used  
„ Data retention voltage : 1.2V (MIN.)  
„ Green package available  
„ Package : 48-pin 12mm x 20mm TSOP-I  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
LY62L102616A  
Operating  
Temperature  
0 ~ 70℃  
Vcc Range  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
55/70ns  
55/70ns  
4µA(SL)  
4µA(SL)  
45/30mA  
45/30mA  
-40 ~ 85℃  
LY62L102616A(I)  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
PIN DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
SYMBOL  
A0 - A19  
A-1 - A19  
DESCRIPTION  
Vcc  
Vss  
Address Inputs(word mode)  
Address Inputs(byte mode)  
A0~A19  
/A-1~A19  
1024Kx16/2048Kx8  
MEMORY ARRAY  
DECODER  
DQ0 – DQ15 Data Inputs/Outputs  
CE#, CE2  
WE#  
OE#  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Byte Enable  
LB#  
UB#  
DQ0-DQ7  
Lower Byte  
BYTE#  
VCC  
I/O DATA  
CIRCUIT  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
Power Supply  
VSS  
Ground  
CE#  
CE2  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
BYTE#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
PIN CONFIGURATION  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A16  
BYTE#  
Vss  
2
3
4
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
Vcc  
5
6
7
A8  
8
A19  
NC  
WE#  
CE2  
NC  
UB#  
LB#  
A18  
A17  
A7  
9
LY62L102616A  
XXXXXXXXX  
XXXX  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
OE#  
A6  
A5  
A4  
A3  
Vss  
A2  
CE#  
A1  
A0  
TSOP-I  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
-0.5 to 4.6  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
1
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
TRUTH TABLE  
I/O OPERATION  
SUPPLY  
CURRENT  
MODE CE# CE2 BYTE# OE# WE# LB#  
UB#  
DQ0-DQ7 DQ8-DQ14 DQ15  
H
X
X
L
L
L
L
L
L
L
L
L
X
X
H
H
H
L
H
H
H
H
H
H
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
H
H
H
H
H
H
L
X
X
H
L
X
L
L
H
L
X
X
H
X
L
L
H
L
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
High – Z  
DOUT  
High – Z  
DOUT  
DIN  
High – Z  
DIN  
High – Z High – Z  
High – Z High – Z  
High – Z High – Z  
High – Z High – Z  
High – Z High – Z  
X
L
Standby  
ISB,ISB1  
X
H
H
H
H
H
H
H
H
H
Output  
Disable  
ICC,ICC1  
High – Z  
A-1  
High – Z High – Z  
Read  
Write  
DOUT  
DOUT  
DOUT  
DOUT  
ICC,ICC1  
L
H
L
L
H
L
High – Z High – Z  
L
L
DIN  
DIN  
DIN  
DIN  
ICC,ICC1  
L
Byte#  
Read  
Byte #  
Write  
L
L
L
H
L
Dout  
Din  
High – Z  
High – Z  
A-1  
A-1  
ICC,ICC1  
H
L
L
L
L
ICC,ICC1  
L
L
X
H
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
2.7  
2.2  
- 0.2  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
3.0  
3.6  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
-
-
-
VCC+0.3  
*2  
VIL  
0.6  
1
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS  
A
µ
ILO  
- 1  
-
1
A
µ
Output Disabled  
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
2.2  
-
2.7  
-
-
V
V
VOL  
IOL = 2mA  
0.4  
Cycle time = Min.  
CE# = VIL and CE2 = VIH  
II/O = 0mA  
45  
30  
60  
45  
- 55  
- 70  
-
-
mA  
ICC  
mA  
mA  
mA  
Other pins at VIL or VIH  
Average Operating  
Power supply Current  
Cycle time = 1 s  
µ
≦
≧
CE# 0.2V and CE2 VCC-0.2V  
ICC1  
-
8
16  
II/O = 0mA  
Other pins at 0.2V or VCC-0.2V  
CE# = VIH or CE2 = VIL  
Other pins at VIL or VIH  
ISB  
-
0.3  
2
SL*5  
℃
℃
-
-
-
-
4
4
4
4
10  
10  
30  
40  
A
µ
A
µ
25  
40  
CE# ≧VCC-0.2V  
Standby Power  
Supply Current  
SLI*5  
≦
or CE2 0.2V  
ISB1  
Other pins at 0.2V  
or VCC-0.2V  
SL  
SLI  
A
µ
A
µ
Notes:  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
5. This parameter is measured at VCC = 3.0V  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
tRC  
UNIT  
LY62L102616A-55  
LY62L102616A-70  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
55  
-
-
-
70  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
-
-
*
*
*
10  
5
-
-
10  
-
10  
5
-
-
10  
-
-
-
20  
20  
-
55  
25  
-
25  
25  
-
70  
30  
-
tOHZ  
tOH  
tBA  
*
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
*
-
10  
-
10  
tBLZ  
*
(2) WRITE CYCLE  
PARAMETER  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
LY62L102616A-55  
LY62L102616A-70  
MIN.  
55  
50  
50  
0
MAX.  
MIN.  
70  
60  
60  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
-
-
tWP  
tWR  
tDW  
tDH  
tOW  
45  
0
-
-
55  
0
-
-
25  
0
-
-
30  
0
-
-
*
5
-
5
-
tWHZ  
*
-
20  
-
60  
25  
-
tBW  
45  
-
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOHZ  
tBHZ  
tCHZ  
tOLZ  
tBLZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE#is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting  
parameter.  
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
CE2  
LB#,UB#  
WE#  
tBW  
tAS  
tWP  
tWR  
tWHZ  
TOW  
High-Z  
Dout  
(4)  
(4)  
tDW  
tDH  
Din  
Data Valid  
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
CE2  
tAS  
tWR  
tCW  
tBW  
tWP  
LB#,UB#  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
WRITE CYCLE 3 (LB#,UB# Controlled)  
(1,2,5,6)  
tWC  
Address  
tAW  
tWR  
CE#  
tAS  
tCW  
CE2  
tBW  
LB#,UB#  
WE#  
tWP  
tWHZ  
High-Z  
Dout  
Din  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions.  
2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain  
in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN.  
TYP. MAX. UNIT  
VCC for Data Retention  
VDR  
1.2  
-
3.6  
10  
10  
30  
40  
V
≧
≦
CE#  
VCC - 0.2V or CE2 0.2V  
℃
℃
-
-
-
-
2.5  
2.5  
2.5  
2.5  
A
25  
40  
SL  
SLI  
µ
µ
µ
µ
VCC = 1.2V  
≧ ≦  
VCC-0.2V or CE2 0.2V  
Other pins at 0.2V or VCC-0.2V  
A
A
A
Data Retention Current  
IDR  
CE#  
SL  
SLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
Low Vcc Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low Vcc Data Retention Waveform (2) (CE2 controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
CE2 ≦ 0.2V  
CE2  
VIL  
VIL  
Low Vcc Data Retention Waveform (3) (LB#, UB# controlled)  
VDR ≧ 1.2V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
LB#,UB# ≧ Vcc-0.2V  
VIH  
LB#,UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
PACKAGE OUTLINE DIMENSION  
48-pin 12mm x 20mm TSOP-I Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
ORDERING INFORMATION  
Package Type  
Access Time  
(Speed)(ns)  
Temperature  
Packing  
Type  
Lyontek Item No.  
Range(℃)  
48Pin 12mmX20mm  
TSOP-I  
55  
70  
Tray  
LY62L102616ALL-55SL  
LY62L102616ALL-55SLT  
LY62L102616ALL-55SLI  
LY62L102616ALL-55SLIT  
LY62L102616ALL-70SL  
LY62L102616ALL-70SLT  
LY62L102616ALL-70SLI  
LY62L102616ALL-70SLIT  
℃
℃
~70  
0
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
Tray  
℃
0
℃
~70  
Tape Reel  
Tape Reel  
Tape Reel  
℃
℃
-40 ~85  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
®
LY62L102616A  
16M Bits ( 2Mx8 / 1Mx16 Switchable) LOW POWER CMOS SRAM  
Rev. 1.1  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
厂商 型号 描述 页数 下载

SEOUL

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SEOUL

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SEOUL

 		LY611 红外灯LED[ INFRARED LAMP LED ] 14 页

LYONTEK

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LYONTEK

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LYONTEK

 		LY611024I 128K ×8位高速CMOS SRAM[ 128K X 8 BIT HIGH SPEED CMOS SRAM ] 13 页

LYONTEK

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LYONTEK

 		LY611024JL-12I [ 暂无描述 ] 13 页

LYONTEK

 		LY611024JL-12LL 128K ×8位高速CMOS SRAM[ 128K X 8 BIT HIGH SPEED CMOS SRAM ] 13 页

LYONTEK

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