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LY61L2568_13

型号：

LY61L2568_13

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

11 页

PDF大小：

215 K

下载PDF手册
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
REVISION HISTORY  
Revision  
Rev. 0.1  
Rev. 0.2  
Rev. 0.3  
Rev. 0.4  
Description  
Preliminary  
Deleted ISB Spec.  
Deleted -10/-12/-15 Spec.  
Revised Test Condition of ICC/ISB1/IDR  
Revised VTERM to VT1 and VT2  
Issue Date  
Apr.19.2006  
May.24.2006  
May.13.2007  
Apr.17.2009  
FEATURES ORDERING INFORMATION  
Revised  
&
Lead free and green package available to Green package  
available  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
ORDERING INFORMATION  
Added packing type in  
Added I grade  
Rev. 0.5  
Rev. 0.6  
Rev. 1.0  
Apr.27.2010  
Aug.30.2010  
Aug.29.2013  
ORDERING INFORMATION  
Revised  
in page 9  
Revised Notes item 1 and 2 in page 3  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
ORDERING INFORMATION  
Added packing type in  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
FEATURES  
GENERAL DESCRIPTION  
The LY61L2568 is a 2,097,152-bit low power CMOS  
static random access memory organized as 262,144  
words by 8 bits. It is fabricated using very high  
performance, high reliability CMOS technology. Its  
standby current is stable within the range of  
operating temperature.  
„ Fast access time : 20/25ns  
„ Very low power consumption:  
Operating current(Normal version):  
110/90mA(TYP.)  
Operating current(20/25ns LL version):  
40/35mA(TYP.)  
Standby current(Normal version):  
0.5mA(TYP.)  
Standby current(20/25ns LL version):  
The LY61L2568 is well designed for very low power  
system applications, and particularly well suited for  
battery back-up nonvolatile memory application.  
10 A(TYP.)  
µ
„ Single 3.3V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
The LY61L2568 operates from a single power  
supply of 3.3V and all inputs and outputs are fully  
TTL compatible  
„ Tri-state output  
„ Data retention voltage : 2.0V (MIN.)  
„ Green package available  
„ Package : 44-pin 400 mil TSOP-II  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
LY61L2568  
LY61L2568(I)  
LY61L2568(LL)  
LY61L2568(LLI)  
Operating  
Temperature  
0 ~ 70℃  
Vcc Range  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
3.0 ~ 3.6V  
3.0 ~ 3.6V  
3.0 ~ 3.6V  
3.0 ~ 3.6V  
20/25ns  
20/25ns  
20/25ns  
20/25ns  
0.5mA  
0.5mA  
110/90mA  
110/90mA  
-40 ~ 85℃  
0 ~ 70℃  
10µA(LL)  
10µA(LL)  
40/35mA(LL)  
40/35mA(LL)  
-40 ~ 85℃  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
A0 - A17  
Address Inputs  
Vcc  
Vss  
DQ0 – DQ7 Data Inputs/Outputs  
CE#  
WE#  
OE#  
VCC  
VSS  
Chip Enable Inputs  
Write Enable Input  
Output Enable Input  
Power Supply  
256Kx8  
MEMORY ARRAY  
A0-A17  
DECODER  
Ground  
NC  
No Connection  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
WE#  
OE#  
CONTROL  
CIRCUIT  
PIN CONFIGURATION  
NC  
NC  
1
2
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
NC  
NC  
A4  
3
NC  
A3  
4
A5  
A2  
5
A6  
A1  
6
A7  
A0  
7
A8  
CE#  
DQ0  
DQ1  
Vcc  
Vss  
DQ2  
DQ3  
WE#  
A17  
A16  
A15  
A14  
A13  
NC  
8
OE#  
DQ7  
DQ6  
Vss  
Vcc  
DQ5  
DQ4  
A9  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A10  
A11  
A12  
NC  
NC  
NC  
NC  
NC  
TSOP-II  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
-0.5 to 4.6  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
H
OE#  
X
WE#  
X
SUPPLY CURRENT  
MODE  
I/O OPERATION  
High-Z  
Standby  
ISB1  
ICC  
ICC  
ICC  
Output Disable  
Read  
L
H
H
High-Z  
L
L
H
DOUT  
Write  
L
X
L
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
3.0  
2.2  
- 0.3  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
3.3  
3.6  
VCC+0.3  
0.6  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -1mA  
2.4  
-
-
-
V
V
VOL  
IOL = 2mA  
-
-
-
-
-
-
-
0.4  
150  
115  
50  
20  
25  
20LL  
25LL  
Normal  
110  
90  
40  
35  
0.5  
10  
mA  
mA  
mA  
mA  
mA  
Cycle time = Min.  
Average Operating  
Power supply Current  
ICC  
CE# = VIL , II/O = 0mA  
Others at VIL or VIH  
45  
5*5  
Standby Power  
Supply Current  
Notes:  
CE# ≧VCC - 0.2V  
Others at 0.2V or VCC - 0.2V20/25LL  
ISB1  
50*6  
A
µ
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
5. 1mA for special request  
6. 20 A for special request  
µ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX  
8
10  
UNIT  
pF  
pF  
CIN  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
LY61L2568-20  
LY61L2568-25  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
MIN.  
MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
tRC  
tAA  
20  
-
-
-
20  
20  
8
-
-
8
8
-
25  
-
-
-
25  
25  
9
-
-
9
9
-
ns  
ns  
ns  
ns  
N`s  
ns  
ns  
ns  
ns  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
-
-
*
*
*
*
4
0
-
-
3
4
0
-
-
3
(2) WRITE CYCLE  
PARAMETER  
LY61L2568-20  
LY61L2568-25  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
MIN.  
20  
16  
16  
0
MAX.  
MIN.  
25  
20  
20  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
-
-
tWP  
tWR  
tDW  
tDH  
tOW  
11  
0
-
-
12  
0
-
-
9
-
10  
0
-
-
0
-
*
5
-
6
-
tWHZ  
*
-
9
-
10  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tAS  
tWP  
tWR  
WE#  
Dout  
Din  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL TEST CONDITION  
MIN.  
TYP. MAX. UNIT  
VCC for Data Retention  
VDR  
CE# ≧ VCC - 0.2V  
VCC = 2.0V  
CE# ≧ VCC - 0.2V  
Others at 0.2V or VCC - 0.2V  
2.0  
-
3.6  
V
Normal  
-
-
0.5  
1
mA  
Data Retention Current  
IDR  
20/25LL  
5
40  
A
µ
Chip Disable to Data  
Retention Time  
Recovery Time  
See Data Retention  
Waveforms (below)  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
VDR ≧ 2.0V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
PACKAGE OUTLINE DIMENSION  
Ⅱ
44-pin 400mil TSOP-  
Package Outline Dimension  
DIMENSIONS IN MILLMETERS  
DIMENSIONS IN MILS  
SYMBOLS  
MIN.  
-
NOM.  
-
MAX.  
1.20  
0.15  
1.05  
0.45  
0.21  
18.618  
12.014  
10.363  
-
MIN.  
NOM.  
-
MAX.  
A
A1  
A2  
b
-
47.2  
5.9  
41.3  
17.7  
8.3  
733  
473  
408  
-
0.05  
0.95  
0.30  
0.12  
18.212  
11.506  
9.957  
-
0.10  
1.00  
-
2.0  
37.4  
11.8  
4.7  
717  
453  
392  
-
3.9  
39.4  
-
c
-
-
D
18.415  
11.760  
10.160  
0.800  
0.50  
0.805  
-
725  
463  
400  
31.5  
19.7  
31.7  
-
E
E1  
e
L
0.40  
-
0.60  
-
15.7  
-
23.6  
-
ZD  
y
-
0.076  
6o  
-
3
0o  
3o  
0o  
3o  
6o  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
ORDERING INFORMATION  
Package Type  
Access Time  
(Speed)(ns)  
Temperature  
Packing  
Type  
Lyontek Item No.  
Range(℃)  
44-pin 400mil  
TSOP-II  
20  
Tray  
LY61L2568ML-20  
℃
℃
~70  
0
Tape Reel  
Tray  
LY61L2568ML-20T  
LY61L2568ML-20E  
LY61L2568ML-20ET  
LY61L2568ML-20I  
LY61L2568ML-20IT  
LY61L2568ML-25  
LY61L2568ML-25T  
LY61L2568ML-25E  
LY61L2568ML-25ET  
LY61L2568ML-25I  
℃
℃
-20 ~80  
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
Tray  
25  
℃
℃
~70  
0
Tape Reel  
Tray  
℃
℃
-20 ~80  
Tape Reel  
Tray  
℃
℃
-40 ~85  
Tape Reel  
LY61L2568ML-25IT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY61L2568  
256K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.0  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
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