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RX-8803LC

型号：

RX-8803LC

品牌：

SEIKO[ SEIKO EPSON CORPORATION ]

页数：

36 页

PDF大小：

759 K

下载PDF手册
ETM34E-04  
Application Manua  
l
Real Time Clock Module  
RX-8803SA/LC  
Preliminary  
NOTICE  
•
•
This material is subject to change without notice.  
Any part of this material may not be reproduced or duplicated in any form or any means without the  
written permission of Seiko Epson.  
•
The information about applied circuitry, software, usage, etc. written in this material is intended for  
reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any  
patent or copyright of a third party. This material does not authorize the licensing for any patent or  
intellectual copyrights.  
•
•
When exporting the products or technology described in this material, you should comply with the  
applicable export control laws and regulations and follow the procedures required by such laws and  
regulations.  
You are requested not to use the products (and any technical information furnished, if any) for the  
development and/or manufacture of weapon of mass destruction or for other military purposes. You  
are also requested that you would not make the products available to any third party who may use the  
products for such prohibited purposes.  
•
These products are intended for general use in electronic equipment. When using them in specific  
applications that require extremely high reliability, such as the applications stated below, you must  
obtain permission from Seiko Epson in advance.  
/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related  
(automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life /  
Submarine transmitters / Power stations and related / Fire work equipment and security  
equipment / traffic control equipment / and others requiring equivalent reliability.  
•
All brands or product names mentioned herein are trademarks and/or registered trademarks of their  
respective.  
RX - 8803 SA / LC  
Contents  
1. Overview........................................................................................................................1  
2. Block Diagram ...............................................................................................................1  
3. Terminal description ......................................................................................................2  
3.1. Terminal connections .......................................................................................................................2  
3.2. Pin Functions....................................................................................................................................2  
4. Absolute Maximum Ratings ...........................................................................................3  
5. Recommended Operating Conditions............................................................................3  
6. Frequency Characteristics .............................................................................................3  
7. Electrical Characteristics................................................................................................4  
7.1. DC Characteristics............................................................................................................................4  
7.2. AC Characteristics............................................................................................................................5  
8. Use Methods..................................................................................................................6  
8.1. Description of Registers ...................................................................................................................6  
8.1.1. Write / Read and Bank Select............................................................................................6  
8.1.2. Register table (Basic time and calendar register) ..............................................................6  
8.1.3. Register table (Extension register  
8.1.4. Register table (Extension register  
ꢀ
ꢁ
) .................................................................................7  
) .................................................................................7  
8.2. Details of Registers ..........................................................................................................................8  
8.2.1. Clock counter ( 1/100S, SEC - HOUR ) .............................................................................8  
8.2.2. Calendar counter ( WEEK - YEAR )...................................................................................9  
8.2.3. Alarm registers.................................................................................................................10  
8.2.4. Fixed-cycle timer control registers....................................................................................10  
8.2.5. Extension register.............................................................................................................10  
8.2.6. Flag register .....................................................................................................................11  
8.2.7. Control register.................................................................................................................12  
8.2.8. OSC Offset Contorol ........................................................................................................14  
8.2.9. Capture Buffer / Event control..........................................................................................15  
8.3. Fixed-cycle Timer Interrupt Function..............................................................................................16  
8.3.1. Diagram of fixed-cycle timer interrupt function.................................................................16  
8.3.2. Related registers for function of time update interrupts. ..................................................17  
8.3.3. Fixed-cycle timer interrupt interval (example) ..................................................................18  
8.3.4. Fixed-cycle timer start timing............................................................................................18  
8.4. Time Update Interrupt Function......................................................................................................19  
8.4.1. Time update interrupt function diagram ...........................................................................19  
8.4.2. Related registers for time update interrupt functions. ......................................................20  
8.5. Alarm Interrupt Function.................................................................................................................21  
8.4.1. Diagram of alarm interrupt function..................................................................................21  
8.5.2. Related registers..............................................................................................................22  
8.5.2. Examples of alarm settings ..............................................................................................23  
2
8.6. Reading/Writing Data via the I C Bus Interface.............................................................................24  
2
8.6.1. Overview of I C-BUS .......................................................................................................24  
8.6.2. System configuration........................................................................................................24  
8.6.3. Starting and stopping I2C bus communications ...............................................................25  
2
8.6.4. Data transfers and acknowledge responses during I C-BUS communications...............26  
8.6.5. Slave address ..................................................................................................................26  
8.6.6. I2C bus protocol................................................................................................................27  
8.7. Backup and Recovery ....................................................................................................................28  
8.8. Connection with Typical Microcontroller.........................................................................................29  
8.9. When used as a clock source (32 kHz-TCXO)...............................................................................29  
9. External Dimensions / Marking Layout.........................................................................30  
10. Application notes .......................................................................................................32  
RX − 8803 SA / LC  
I2C-Bus Interface Real-time Clock Module  
RX − 8803 SA / LC  
• Features built-in 32.768 kHz DTCXO, High Stability.  
• Supports I2C-Bus's high speed mode (400 kHz)  
• Alarm interrupt function for day, date, hour, and minute settings  
• Fixed-cycle timer interrupt function  
(Seconds, minutes)  
• Time update interrupt function  
(FOE and FOUT pins)  
(from 2000 to 2099)  
• 32.768 kHz output with OE function  
• Auto correction of leap years  
• Wide interface voltage range: 2.2 V to 5.5 V  
• Wide time-keeping voltage range:1.6 V to 5.5 V  
• Low current consumption: 0.75µA / 3 V (Typ.)  
• Time synchronization function by 1PPS(*) signal input  
(*)Signal on pulse per second that synchronizes with Coordinated Universal Time output from GPS module  
The I2C-BUS is a trademark of NXP Semiconductors.  
1. Overview  
This module is an I2C bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO.  
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter  
function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer  
function, time update interrupt function, and 32.768 kHz output function.  
The devices in this module are fabricated via a C-MOS process for low current consumption, which enables  
long-term battery back-up.  
All of these many functions are implemented in SOP-14 pin and VSOJ-20 pin package.  
2. Block Diagram  
32.768 kHz  
32kHz  
DTCXO  
CLOCK  
DIVIDER  
and  
CALENDAR  
FOE  
TIMER  
FOUT  
CONTROLLER  
REGISTER  
FOUT  
EVI  
ALARM  
INTERRUPT  
CONTROLLER  
/ INT  
SCL  
SDA  
SYSTE  
CONTROLLER  
and  
INTERFACE  
CIRCUIT  
CONTROL  
REGISTER  
Page - 1  
ETM34E - 04  
RX − 8803 SA / LC  
3. Terminal description  
3.1. Terminal connections  
RX − 8803 SA  
RX − 8803 LC  
1. T1 (CE)  
2. SCL  
14. N.C.  
13. SDA  
1. N.C.  
12. EVIN  
11. / INT  
10. GND  
2. FOE  
3. VDD  
3. FOUT  
4. N.C.  
12. T2 (VPP  
11. GND  
10. / INT  
9. EVIN  
)
4. FOUT  
5. SCL  
6. T1(CE)  
9. T2(VPP  
)
5. TEST  
6. VDD  
8. SDA  
7. N.C.  
7. FOE  
8. N.C.  
VSOJ − 12pin  
SOP − 14pin  
3.2. Pin Functions  
Signal  
name  
I/O  
Function  
This pin's signal is used for input and output of address, data, and ACK bits, synchronized  
with the serial clock used for I2C communications.  
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable  
pull-up resistance relative to the signal line capacity.  
SDA  
I/O  
SCL  
Input  
This is the serial clock input pin for I2C Bus communications.  
This is the C-MOS output pin with output control provided via the FOE pin.  
When FOE = "H" (high level), this pin outputs a 32.768 kHz signal.  
When output is stopped, the FOUT pin = "Hi-Z"( high impedance ).  
FOUT  
Output  
This is an input pin used to control the output mode of the FOUT pin.  
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the  
FOUT pin is stopped.  
FOE  
Input  
This pins is used to output alarm signals, timer signals, time update signals, and other  
signals. This pin is an open drain pin.  
/ INT  
EVIN  
Output  
Input  
−
External event input pin.  
V
DD  
This pin is connected to a positive power supply.  
This pin is connected to a ground.  
GND  
TEST  
−
Input  
Input  
−
Use by the manufacture for testing. ( Do not connect externally.)  
Use by the manufacture for testing. ( Do not connect externally.)  
Use by the manufacture for testing. ( Do not connect externally.)  
This pin is not connected to the internal IC.  
T1 (CE)  
T2 (VPP  
N.C.  
)
−
Leave N.C. pins open or connect them to GND or VDD  
.
Note: Be sure to connect a bypass capacitor rated at least 0.1 µF between VDD and GND.  
Page - 2  
ETM34E - 04  
RX − 8803 SA / LC  
4. Absolute Maximum Ratings  
GND = 0 V  
Unit  
Item  
Symbol  
Condition  
Rating  
to +6.5  
Supply voltage  
VDD  
VIN1  
VIN2  
Between VDD and GND  
V
V
−0.3  
GND−0.3  
GND−0.3  
GND−0.3  
GND−0.3  
−55  
Input voltage (1)  
Input voltage (2)  
FOE pin  
to VDD+0.3  
to +6.5  
SCL and SDA pins  
FOUT pin  
V
Output voltage (1)  
Output voltage (2)  
Storage temperature  
V
V
OUT1  
OUT2  
to VDD+0.3  
to +6.5  
V
SDA and /INT pins  
V
When stored separately,  
without packaging  
T
STG  
to +125  
°C  
5. Recommended Operating Conditions  
GND = 0 V  
Unit  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Operating supply voltage  
V
DD  
Interface voltage  
1.6  
2.2  
1.6  
−40  
3.0  
3.0  
3.0  
+25  
5.5  
5.5  
5.5  
+85  
V
V
Temp. compensation  
voltage  
Temperature compensation  
voltage  
V
TEM  
CLK  
Clock supply voltage  
Operating temperature  
V
V
−
TOPR  
No condensation  
°C  
6. Frequency Characteristics  
GND = 0 V  
Unit  
Item  
Symbol  
Condition  
Rating  
Ta= 0 to +50 °C, VDD=3.0 V  
Ta=−40 to +85 °C, VDD=3.0 V  
± 1.9 ( 1)  
± 3.4 ( 2)  
U A  
U B  
Ta= 0 to +50 °C, VDD=3.0 V  
Ta=−40 to +85 °C, VDD=3.0 V  
± 3.8 ( 3)  
± 5.0 ( 4)  
± 3.8 ( 3)  
± 5.0 ( 4)  
× 10−ꢀ  
Frequency stability  
∆ f / f  
Ta= 0 to +50 °C, VDD=3.0 V  
Ta=−30 to +70 °C, VDD=3.0 V  
U C  
A A  
+5± 5.0 ( 5)  
± 1.0 Max.  
Ta= +25 °C, VDD=3.0 V  
Frequency/voltage  
characteristics  
× 10−ꢀ/ V  
f / V  
Ta= +25 °C, VDD=2.2 V to 5.5 V  
1.0 Max.  
3.0 Max.  
Ta= +25 °C, VDD=1.6 V  
Ta=−40 to +85 °C, VDD=1.6 V to 5.5 V  
Oscillation start time  
t
STA  
s
× 10−ꢀ  
year  
/
Aging  
fa  
Ta= +25 °C, VDD=3.0 V, first year  
± 3 Max.  
*
*
1 ) Equivalent to 5 seconds of month deviation.  
3 ) Equivalent to 10 seconds of month deviation.  
*
*
2 ) Equivalent to 9 seconds of month deviation.  
*
4 )  
5 ) Equivalent to 13 seconds of month deviation. ( excluding offset )  
Page - 3  
ETM34E - 04  
RX − 8803 SA / LC  
7. Electrical Characteristics  
7.1. DC Characteristics  
*Unless otherwise specified, GND = 0 V, VDD = 1.6 V to 5.5 V, Ta = −40 °C to +85 °C  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
Current  
consumption (1)  
Current  
f
SCL = 0 Hz, / INT = VDD  
I
I
DD1  
0.75  
3.4  
V
V
DD = 5 V  
DD = 3 V  
FOE = GND  
FOUT : output OFF ( High Z )  
Compensation interval 2.0 s  
µA  
DD2  
0.75  
2.0  
2.1  
7.5  
consumption (2)  
Current  
consumption (3)  
f
SCL = 0 Hz, / INT = VDD  
I
I
I
I
I
I
I
DD3  
DD4  
DD5  
DD6  
DD7  
DD8  
DD9  
V
V
V
V
V
V
V
V
DD = 5 V  
DD = 3 V  
DD = 5 V  
DD = 3 V  
DD = 5 V  
DD = 3 V  
DD = 5 V  
DD = 3 V  
FOE = VDD  
FOUT :32.768 kHz, CL =0pF  
Compensation interval 2.0 s  
µA  
µA  
µA  
µA  
Current  
consumption (4)  
1.5  
7.0  
4.5  
0.7  
0.7  
120  
115  
5.0  
20.0  
12.0  
2.95  
1.85  
900  
Current  
consumption (5)  
f
SCL = 0 Hz, / INT = VDD  
FOE = VDD  
FOUT :32.768 kHz, CL =30pF  
Compensation interval 2.0 s  
Current  
consumption (6)  
Current  
consumption (7)  
f
SCL = 0 Hz, / INT = VDD  
FOE = GND  
FOUT : output OFF ( High Z )  
Compensation OFF  
Current  
consumption (8)  
Current  
consumption (9)  
f
SCL = 0 Hz, / INT = VDD  
FOE = GND  
FOUT : output OFF ( High Z )  
Compensation ON ( peak )  
Current  
consumption (10)  
I
DD10  
350  
High-level input  
voltage  
Low-level input  
voltage  
V
IH  
CE, DI, CLK, FOE, EVIN pins  
CE, DI, CLK, FOE, EVIN pins  
5.5  
V
V
0.8 × VDD  
GND − 0.3  
V
IL  
0.2 × VDD  
V
V
V
V
V
V
V
V
V
OH1  
OH2  
OH3  
4.5  
2.2  
2.9  
GND  
GND  
GND  
GND  
GND  
GND  
5.0  
3.0  
3.0  
V
V
V
V
V
V
V
V
V
DD=5 V, IOH=−1 mA  
DD=3 V, IOH=−1 mA  
DD=3 V, IOH=−100 µA  
DD=5 V, IOL=1 mA  
DD=3 V, IOL=1 mA  
DD=3 V, IOL=100 µA  
DD=5 V, IOL=1 mA  
DD=3 V, IOL=1 mA  
DD ≥2 V, IOL=3 mA  
High-level output  
voltage  
FOUT pin  
FOUT pin  
V
V
OL1  
OL2  
OL3  
OL4  
OL5  
OL6  
GND+0.5  
GND+0.8  
GND+0.1  
GND+0.25  
GND+0.4  
GND+0.4  
Low-level output  
voltage  
/ INT pin  
SDA pin  
V
V
Input leakage  
current  
Output leakage  
current  
I
LK  
FOE, SCL, SDA pins ,  
V
IN = VDD or GND  
0.5  
0.5  
−0.5  
−0.5  
µA  
I
OZ  
/ INT, SDA, FOUT pins, VOUT = VDD or GND  
µA  
• Temperature compensation and consumption current  
Compensation ON  
1 ms  
I
DD9,10  
Average  
I
DD1,2  
Compensation OFF  
I
DD7,8  
Compensation interval ( 2.0 s )  
Page - 4  
ETM34E - 04  
RX − 8803 SA / LC  
* Unless otherwise specified,  
GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C  
7.2. AC Characteristics  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
SCL clock frequency  
f
SCL  
400  
kHz  
Start condition setup time  
Start condition hold time  
Data setup time  
t
t
t
SU;STA  
HD;STA  
SU;DAT  
0.6  
0.6  
100  
0
µs  
µs  
ns  
ns  
Data hold time  
t
t
HD;DAT  
SU;STO  
900  
Stop condition setup time  
Bus idle time between  
start condition and stop condition  
0.6  
µs  
t
BUF  
1.3  
µs  
t
LOW  
1.3  
0.6  
µs  
µs  
Time when SCL  
Time when SCL  
=
=
"L"  
t
HIGH  
"H"  
Rise time for SCL and SDA  
Fall time for SCL and SDA  
Allowable spike time on bus  
FOUT duty  
t
t
r
0.3  
0.3  
50  
µs  
µs  
ns  
%
f
t
SP  
t
W
/t  
50% of VDD level  
40  
50  
60  
Timing chart  
START  
CONDITION  
BIT 7  
MSB  
(A7)  
BIT 6  
(A6)  
BIT 0  
LSB  
(R/W)  
ACK  
(A)  
STOP  
CONDITION  
START  
CONDITION  
Protocol  
(S)  
(P)  
(S)  
t
SU ; STA  
t
LOW  
t
HIGH  
1 / fSCL  
t
SU ; STA  
SCL  
SDA  
(S)  
(P)  
(S)  
t
BUF  
tr  
tf  
(A)  
t
HD ; STA  
t
SU ; DAT  
t
HD ; DAT  
t
SP  
t
SU ; STO  
t
HD ; STA  
Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop  
condition after access should be completed within 0.95 seconds.  
If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus  
timeout function.  
Page - 5  
ETM34E - 04  
RX − 8803 SA / LC  
8. Use Methods  
8.1. Description of Registers  
8.1.1. Write / Read and Bank Select  
Address 00h to 0Fh : Basic time and calendar register … Compatible with RX-8801.  
Address 10h to 1Fh : Extension registerꢀ … Adds 1/100s Counter.  
Address 20h to 2Fh : Extension registerꢁ … Capture buffer and Event control registers.  
8.1.2. Register table (Basic time and calendar register)  
Address  
Function  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read  
Write  
ꢂ
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
SEC  
MIN  
40  
40  
ꢂ
20  
20  
20  
5
10  
10  
10  
4
8
8
8
3
8
8
8
•
4
4
4
2
4
4
4
•
2
2
1
1
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
HOUR  
2
1
WEEK  
6
ꢂ
ꢂ
1
0
DAY  
20  
ꢂ
10  
10  
10  
•
2
1
MONTH  
2
1
YEAR  
80  
•
40  
•
20  
•
2
1
RAM  
•
•
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
Timer Counter 0  
Timer Counter 1  
Extension Register  
Flag Register  
Control Register  
AE  
AE  
40  
•
20  
20  
5
10  
10  
4
8
8
3
8
8
4
4
2
4
4
2
1
2
1
6
1
0
P
P
0A  
AE  
20  
32  
•
10  
16  
•
2
1
•
P
P
P
P
P
P
P
P
P
P
0B  
0C  
0D  
0E  
0F  
128  
64  
•
2
1
2048 1024  
512  
256  
•
TEST WADA USEL  
TE FSEL1 FSEL0 TSEL1 TSEL0  
ꢂ
ꢂ
UF  
TF  
AF  
EVF  
EIE  
VLF VDET  
ꢂ
CSEL1 CSEL0 UIE  
TIE  
AIE  
RESET  
P : Possible , I : Impossible  
Note  
When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before  
using the module.  
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data  
or time data is incorrect.  
1)  
During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".  
At this point, all other register values are undefined, so be sure to perform a reset before using the module.  
Only a "0" can be written to the UF, TF, AF, VLF, or VDET bit.  
2)  
3)  
4)  
5)  
Any bit marked with " " should be used with a value of "0" after initialization.  
ꢂ
Any bit marked with "•" is a RAM bit that can be used to read or write any data.  
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.  
Page - 6  
ETM34E - 04  
RX − 8803 SA / LC  
8.1.3. Register table (Extension registerꢀ)  
Address  
Function  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read  
Write  
P
P
P
P
P
P
P
P
P
P
I
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1/100 S  
SEC  
80  
40  
40  
40  
ꢂ
20  
20  
20  
20  
5
10  
10  
10  
10  
4
8
8
8
8
3
8
8
8
8
8
3
8
8
4
4
4
4
2
4
4
4
4
4
2
4
4
2
2
1
1
ꢂ
P
P
P
P
P
P
P
P
P
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
MIN  
2
1
HOUR  
2
1
WEEK  
6
ꢂ
ꢂ
1
0
DAY  
20  
ꢂ
10  
10  
10  
10  
10  
4
2
1
MONTH  
2
1
YEAR  
80  
AE  
AE  
40  
40  
•
20  
20  
20  
5
2
1
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
Timer Counter 0  
Timer Counter 1  
Extension Register  
Flag Register  
Control Register  
2
1
2
1
6
1
0
P
P
1A  
AE  
20  
32  
•
10  
16  
•
2
1
•
P
P
P
P
P
P
P
P
P
P
1B  
1C  
1D  
1E  
1F  
128  
64  
•
2
1
2048 1024  
512  
256  
•
TEST WADA USEL  
TE FSEL1 FSEL0 TSEL1 TSEL0  
ꢂ
ꢂ
UF  
TF  
AF  
EVF  
EIE  
VLF VDET  
ꢂ
CSEL1 CSEL0 UIE  
TIE  
AIE  
RESET  
1/100S Reg. is cleared to "00" by writing in the SEC Reg. or RESET bit and the ERST bit operation.  
8.1.4. Register table (Extension registerꢁ)  
Address  
Function  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read  
Write  
P
P
I
I
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
1/100 S CP  
80  
40  
40  
−
20  
20  
−
10  
10  
−
8
8
−
−
−
−
−
−
−
−
−
−
4
4
−
−
−
−
−
−
−
−
−
−
2
2
−
−
−
−
−
−
−
−
−
−
1
1
−
−
−
−
−
−
−
−
−
−
ꢂ
SEC CP  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
P
−
−
−
−
−
−
−
−
−
−
P
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ꢂ
ꢂ
ꢂ
ꢂ
OSC Offset  
OFS3 OFS2 OFS1 OFS0  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
P
−
−
P
−
−
−
−
ꢂ
ꢂ
ꢂ
Event Control  
ECP  
EHL  
ET1  
ET0  
ERST  
When an initial power on, frequency offset is ±0 selected by "0000".  
Page - 7  
ETM34E - 04  
RX − 8803 SA / LC  
8.2. Details of Registers  
8.2.1. Clock counter ( 1/100S, SEC - HOUR )  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
10  
1/100 S  
SEC  
MIN  
80  
ꢂ
40  
40  
40  
ꢂ
20  
20  
20  
20  
10  
10  
10  
10  
8
8
8
8
4
4
4
4
2
2
2
2
1
1
1
1
00, 11  
01, 12  
02, 13  
ꢂ
ꢂ
HOUR  
)
"o" indicates write-protected bits. A zero is always read from these bits.  
• The clock counter counts 1/100s, seconds, minutes, and hours.  
• The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59  
seconds.  
Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.  
1) 1/100 Second counter  
Address  
10  
Function  
1/100 S  
bit 7  
80  
bit 6  
40  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
• This second counter counts from "00" to "01," "02," and up to 99/100 seconds, after which it starts again  
from 00 seconds.  
2) Second counter  
Address  
00, 11  
Function  
SEC  
bit 7  
bit 6  
40  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
ꢂ
• This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from  
00 seconds.  
3) Minute counter  
Address  
01, 12  
Function  
MIN  
bit 7  
bit 6  
40  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
ꢂ
• This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from  
00 minutes.  
4) Hour counter  
Address  
02, 13  
Function  
HOUR  
bit 7  
bit 6  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
ꢂ
ꢂ
• This hour counter counts from "00" hours to "01," "02," and up to 23 hours, after which it starts again from  
00 hours.  
Page - 8  
ETM34E - 04  
RX − 8803 SA / LC  
8.2.2. Calendar counter ( WEEK - YEAR )  
Address  
03, 14  
Function  
WEEK  
bit 7  
bit 6  
6
bit 5  
5
bit 4  
4
bit 3  
3
bit 2  
2
bit 1  
1
bit 0  
0
ꢂ
)
"o" indicates write-protected bits. A zero is always read from these bits.  
1) Day of the WEEK counter  
• The day (of the week) is indicated by 7 bits, bit 0 to bit 6.  
The day data values are counted as: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day  
20h → Day 40h → Day 01h → Day 02h, etc.  
• The correspondence between days and count values is shown below.  
WEEK  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Day  
Data [h]  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
Sunday  
Monday  
Tuesday  
Wednesday  
Thursday  
Friday  
01 h  
02 h  
04 h  
08 h  
10 h  
20 h  
40 h  
Write/Read  
Saturday  
Do not set "1" to more than one day at the same time.  
Also, note with caution that any setting other than the  
seven shown above should not be made as it may  
interfere with normal operation.  
Write prohibit  
−
−
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢂ
ꢂ
ꢂ
ꢂ
04, 15  
05, 16  
06, 17  
DAY  
MONTH  
YEAR  
20  
10  
10  
10  
8
8
8
4
4
4
2
2
2
1
1
1
ꢂ
80  
40  
20  
)
"o" indicates write-protected bits. A zero is always read from these bits.  
• The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.  
• The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.  
Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.  
2) Date counter  
Address  
04, 15  
Function  
DAY  
bit 7  
bit 6  
bit 5  
20  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
ꢂ
ꢂ
• The updating of dates by the date counter varies according to the month setting.  
A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In  
February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc.  
DAY  
Month  
Date update pattern  
1, 3, 5, 7, 8, 10, or 12  
4, 6, 9, or 11  
February in normal year  
February in leap year  
01, 02, 03 30, 31, 01  
01, 02, 03 30, 01, 02  
01, 02, 03 28, 01, 02  
01, 02, 03 28, 29, 01  
Write/Read  
3) Month counter  
Address  
05, 16  
Function  
MONTH  
bit 7  
bit 6  
bit 5  
bit 4  
10  
bit 3  
8
bit 2  
4
bit 1  
2
bit 0  
1
ꢂ
ꢂ
ꢂ
• The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again  
at 01 (January).  
4) Year counter  
Address  
06, 17  
Function  
YEAR  
bit 7  
Y80  
bit 6  
Y40  
bit 5  
Y20  
bit 4  
Y10  
bit 3  
Y8  
bit 2  
Y4  
bit 1  
Y2  
bit 0  
Y1  
• The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.  
• Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.  
Page - 9  
ETM34E - 04  
RX − 8803 SA / LC  
8.2.3. Alarm registers  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
08, 18  
09, 19  
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
AE  
AE  
40  
•
6
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
0A, 1A  
AE  
20  
10  
•
• The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day,  
hour, and minute values.  
• When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to low  
level and "1" is set to the AF bit to report that and alarm interrupt event has occurred.  
8.2.4. Fixed-cycle timer control registers  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
0B, 1B  
0C, 1C  
Timer Counter 0  
Timer Counter 1  
128  
•
64  
•
32  
•
16  
•
8
4
2
512  
1
256  
2048  
1024  
• These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function.  
The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function.  
• When the value in the above fixed-cycle timer control register changes from 001h to 000h, the /INT pin goes to low  
level and "1" is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred.  
8.2.5. Extension register  
Address  
0D, 1D  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Extension Register  
TEST  
(0)  
WADA  
(−)  
USEL  
(−)  
TE  
(−)  
FSEL1 FSEL0 TSEL1 TSEL0  
(0)  
(Default)  
(0)  
(−)  
(−)  
1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
2) "o" indicates write-protected bits. A zero is always read from these bits.  
3) "−" indicates a default value is undefined.  
• This register is used to specify the target for the alarm function or time update interrupt function and to select or  
set operations such as fixed-cycle timer operations.  
1) TEST bit  
This is the manufacturer's test bit. Its value should always be "0".  
Be careful to avoid writing a "1" to this bit when writing to other bits.  
TEST  
Data  
Description  
Default  
0
Normal operation mode  
Setting prohibited (manufacturer's test bit)  
Write/Read  
1
2) WADA ( Week Alarm/Day Alarm ) bit  
This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function.  
Writing a "1" to this bit specifies DAY as the comparison obLCct for the alarm interrupt function.  
Writing a "0" to this bit specifies WEEK as the comparison obLCct for the alarm interrupt function.  
3) USEL ( Update Interrupt Select ) bit  
This bit is used to specify either "second update" or "minute update" as the update generation timing of the time  
update interrupt function.  
Auto reset time  
USEL  
Data  
update interrupts  
t
RTN  
0
1
second update  
minute update  
Default  
500 ms  
Write/Read  
7.813 ms  
4) TE ( Timer Enable ) bit  
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.  
Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a  
preset value).  
Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function.  
Page - 10  
ETM34E - 04  
RX − 8803 SA / LC  
5) FSEL0,1 ( FOUT frequency Select 0, 1 ) bits  
The combination of these two bits is used to set the FOUT frequency.  
FSEL1  
(bit 3)  
FSEL0  
(bit 2)  
FSEL0,1  
FOUT frequency  
32768 Hz Output  
0
0
1
1
0
1
0
1
Default  
1024 Hz Output  
1 Hz Output  
Write/Read  
32768 Hz Output  
6) TSEL0,1 ( Timer Select 0, 1 ) bits  
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer  
interrupt function (four settings can be made).  
TSEL1  
(bit 1)  
TSEL0  
(bit 0)  
TSEL0,1  
Source clock  
4096 Hz  
0
0
1
1
0
1
0
1
/ Once per 244.14 µs  
64 Hz / Once per 15.625 ms  
"Second" update / Once per second  
"Minute" update / Once per minute  
Write/Read  
8.2.6. Flag register  
Address  
0E, 1E  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢂ
ꢂ
Flag register  
UF  
(−)  
TF  
(−)  
AF  
(−)  
EVF  
(−)  
VLF  
(1)  
VDET  
(1)  
(Default)  
(0)  
(0)  
1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
2) "o" indicates write-protected bits. A zero is always read from these bits.  
3) "−" indicates a default value is undefined.  
• This register is used to detect the occurrence of various interrupt events and reliability problems in internal data.  
1) UF ( Update Flag ) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
For details, see "8.4. Time Update Interrupt Function".  
2) TF ( Timer Flag ) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
For details, see "8.3. Fixed-cycle Timer Interrupt Function".  
3) AF ( Alarm Flag ) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred.  
Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
For details, see "8.5. Alarm Interrupt Function".  
4) EVF ( Event Flag ) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a event input interrupt has occurred.  
Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
5) VLF ( Voltage Low Flag ) bit  
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"  
when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained  
until a "0" is written to it.  
When after powering up from 0 V this bit's value is "1" .  
Page - 11  
ETM34E - 04  
RX − 8803 SA / LC  
VLF  
Data  
0
Description  
The VLF bit is cleared to zero to prepare for the next status detection.  
Write  
Read  
1
This bit is invalid after a "1" has been written to it.  
Data loss is not detected.  
0
1
Data loss is detected. All registers must be initialized.  
( This setting is retained until a "zero" is written to this bit. )  
5) VDET ( Voltage Detection Flag ) bit  
This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the  
temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is  
retained until a "0" is written to it.  
When after powering up from 0 V this bit's value is "1".  
VDET  
Data  
0
Description  
The VDET bit is cleared to zero to prepare for the next low voltage detection.  
Write  
1
0
1
The write access of "1" to this bit is invalid.  
Temperature compensation is normal.  
Read  
Temperature compensation is stop detected.  
8.2.7. Control register  
Address  
0F, 1F  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢂ
Control Register  
CSEL1 CSEL0  
UIE  
(−)  
TIE  
(−)  
AIE  
(−)  
EIE  
(−)  
RESET  
(Default)  
(0)  
(1)  
(0)  
(−)  
1) The default value is the value that is read (or is set internally) after powering up from 0 V.  
2) "o" indicates write-protected bits. A zero is always read from these bits.  
3) "−" indicates no default value has been defined.  
• This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and  
calendar operations.  
1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits  
The combination of these two bits is used to set the temperature compensation interval.  
CSEL1  
(bit 7)  
CSEL0  
(bit 6)  
CSEL0,1  
Compensation interval  
0.5 s  
0
0
1
1
0
1
0
1
Default  
2.0 s  
Write/Read  
10 s  
30 s  
2) UIE ( Update Interrupt Enable ) bit  
When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
Page - 12  
ETM34E - 04  
RX − 8803 SA / LC  
UIE  
Data  
0
Function  
When a time update interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status changes from low to Hi-Z).  
When a time update interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
Write/Read  
1
When a time update interrupt event occurs, low-level output from the /INT pin occurs only when  
the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT  
status changes from low to Hi-Z) 7.8 ms after the interrupt occurs.  
2) TIE ( Timer Interrupt Enable ) bit  
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
TIE  
Data  
Function  
When a fixed-cycle timer interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status changes from low to Hi-Z).  
0
When a fixed-cycle timer interrupt event occurs, an interrupt signal is  
generated (/INT status changes from Hi-Z to low).  
Write/Read  
1
*
When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin  
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z)  
.
3) AIE ( Alarm Interrupt Enable ) bit  
When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value  
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT  
status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
AIE  
Data  
Function  
When an alarm interrupt event occurs, an interrupt signal is not generated  
or is canceled (/INT status changes from low to Hi-Z).  
0
When an alarm interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
Write/Read  
1
When an alarm interrupt event has been generated low-level output from the /INT pin occurs  
only when the value of the control register's AIE bit is "1". This setting is retained until the AF bit  
value is cleared to zero. (No automatic cancellation)  
For details, see "8.5. Alarm Interrupt Function".  
[Caution]  
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.  
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1"  
(this indicates which type of interrupt event has occurred).  
(2) To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without  
outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags.  
4) EIE ( Event Interrupt Enable ) bit  
When a Event input is generated (when the EVF bit value changes from "0" to "1"), this bit's value specifies if an  
interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z).  
When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an  
interrupt event is generated.  
When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.  
5) RESET bit  
When this bit is set to "1", values (less than seconds) of the counter in the Clock & Calendar circuitry is reset,  
and the clock also stops.  
After "1" is written to this bit, this can be released by setting CE to "L".  
Page - 13  
ETM34E - 04  
RX − 8803 SA / LC  
8.2.8. OSC Offset Contorol  
Address  
2C  
Function  
OSC Offset  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢂ
ꢂ
ꢂ
ꢂ
OFS3  
OFS2  
OFS1  
OFS0  
1) OFS bits (OFS3-OFS0)  
The offset adjustment is done to the oscillation frequency.  
Adjust value ( x 10-6 )  
RX-8803SA RX-8803LC  
± 0.0 ± 0.0  
OFS3  
OFS2  
OFS1  
OFS0  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
−0.6  
−1.2  
−1.8  
−2.4  
−3.0  
−3.6  
−4.2  
+4.8  
+4.2  
+3.6  
+3.0  
+2.4  
+1.8  
+1.2  
+0.6  
−0.7  
−1.4  
−2.1  
−2.8  
−3.5  
−4.2  
−4.9  
+5.6  
+4.9  
+4.2  
+3.5  
+2.8  
+2.1  
+1.4  
+0.7  
*The OFS register affects the frequency stability. Please refer to a lower graph.  
Please be careful if you offset and adjust it.  
The offset function is effective for frequency adjustment at the normal temperature.  
Frequency Stability vs. Temperature vs. OSC Offset Value  
(Typ_data)  
20  
OSC_Offset:08h  
15  
10  
5
OSC_Offset:00h  
0
-5  
-10  
-15  
OSC_Offset:07h  
60 85  
-20  
-40  
-15  
10  
35  
Temperature [℃]  
Page - 14  
ETM34E - 04  
RX − 8803 SA / LC  
8.2.9. Capture Buffer / Event control  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
20  
21  
2F  
1/100 S CP  
SEC CP  
Event Control  
80  
40  
40  
EHL  
20  
20  
ET1  
10  
10  
ET0  
8
8
ꢂ
4
4
ꢂ
2
2
ꢂ
1
1
ꢂ
ECP  
ERST  
It is a register that sets it concerning the event detection.  
1) ECP bit ( Event Capture enable )  
It is specified whether to do the second and 1/100S data to the capture buffer in capture  
when the event is detected.  
ECP  
Operation  
0
1
Capture doesn't operate  
Capture operation  
2) EHL bit ( High/Low detection select )  
The disregard level of the event input is specified.  
The event is detected by maintaining the level specified by the EHL bit longer than the chattering removal  
cycle.  
EHL  
0
1
Operation  
"L" level detect  
"H" level detect  
3) ET1, ET0 bits ( Event chattering Time Set )  
The removal cycle of the chattering removal function is set.  
ꢁChattering removal cycle  
ET1  
0
0
ET0  
0
1
Cycle  
not provided  
3.9 ms  
1
1
0
1
15.6 ms  
125 ms  
4) ERST bit  
When this bit is made "1", the counter of the Clock & Calendar circuit (counter for 16kHz to 2Hz  
and 1/100 seconds) at less than second is reset synchronizing with the external event detection.  
ALL "0" is cleared to CP and the CP register of the second at the same time for 1/100 seconds.  
Timing continues until the event is generated after "1" is written in the ERST bit.  
The counter at less than second when an external event is detected is reset, and the ERST bit is  
cleared.  
Moreover, it is also possible to assume this reset action to be invalid by doing "0" writing  
directly to the ERST bit before the event is generated.  
When the highly accurate time suiting is done, this bit is used.  
The time for the counter at less than second to be reset influences the operation of the alarm, the  
fixed cycle timer, and the update interrupt of time, etc.  
Page - 15  
ETM34E - 04  
RX − 8803 SA / LC  
8.3. Fixed-cycle Timer Interrupt Function  
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set  
between 244.14 µs and 4095 minutes.  
When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an  
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from  
the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z).  
Example of  
/INT operation  
7.8ms  
(Max.)  
period  
TIE = " 1 "  
TIE = " 1 " → " 0 "  
TE = " 0 " → " 1 "  
8.3.1. Diagram of fixed-cycle timer interrupt function  
Fixed-cycle timer starts  
Fixed-cycle timer stops  
" 1 "  
" 0 "  
(1)  
(7)  
TE bit  
Operation of fixed-cycle timer  
(9)  
" 1 "  
" 1 "  
" 0 "  
(5)  
TIE bit  
Hi - z  
" L "  
/INT output  
(6)  
(7)  
Even when the TE bit is  
tRTN  
tRTN cleared to zero, /INT  
remains low during the  
tRTN time.  
tRTN  
tRTN  
Even when the TF bit is  
(8)  
cleared to zero, /INT  
remains low during the  
tRTN time.  
" 1 "  
" 0 "  
(4)  
(3)  
TF bit  
period  
period  
period  
period  
(2)  
• • • 001 h → 000 h  
(1)  
Event occurs  
(7)  
When the TE bit value changes from "0" to "1" the fixed-cycle timer function starts.  
The counter always starts counting down from the preset value when the TE value changes from "0" to "1".  
RTC internal operation  
Write operation  
(1) When a "1" is written to the TE bit, the fixed-cycle timer countdown starts from the preset value.  
(2) A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When  
the count value changes from 001h to 000h, an interrupt event occurs.  
After the interrupt event that occurs when the count value changes from 001h to 000h, the counter  
automatically reloads the preset value and again starts to count down. (Repeated operation)  
(3) When a fixed-cycle timer interrupt event occurs, "1" is written to the TF bit.  
(4) When the TF bit = "1" its value is retained until it is cleared to zero.  
(5) If the TIE bit = "1" when a fixed-cycle timer interrupt occurs, /INT pin output goes low.  
If the TIE bit = "0" when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z.  
(6) Output from the /INT pin remains low during the tRTN period following each event, after which it is  
automatically cleared to Hi-Z status.  
/INT is again set low when the next interrupt event occurs.  
(7) When a "0" is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z  
status.  
When /INT = low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time  
before the /INT pin status changes from low to Hi-Z.  
(8) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TF bit value changes from "1" to  
"0".  
(9) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from "1" to  
"0".  
Page - 16  
ETM34E - 04  
RX − 8803 SA / LC  
8.3.2. Related registers for function of time update interrupts.  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
0B, 1B  
0C, 1C  
0D, 1D  
0E, 1E  
0F, 1F  
Timer Counter 0  
Timer Counter 1  
Extension Register  
Flag Register  
128  
•
64  
•
32  
•
16  
•
8
4
2
512  
1
256  
2048  
FSEL1  
AF  
1024  
FSEL0  
EVF  
TEST  
WADA  
USEL  
TE  
TF  
TIE  
TSEL1 TSEL0  
VLF  
ꢂ
ꢂ
UF  
VDET  
ꢂ
CSEL1  
CSEL0  
UIE  
AIE  
EIE  
RESET  
Control Register  
1) "o" indicates write-protected bits. A zero is always read from these bits.  
2) Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.  
Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent hardware  
interrupts from occurring inadvertently while entering settings.  
When the STOP bit or RESET bit value is "1" the time update interrupt function operates only partially.  
(Operation continues if the source clock setting is 4096 Hz. Otherwise, operation is stopped.)  
When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register (Reg – B to  
C) can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and  
TIE bits.  
1) TSEL0,1 bits (Timer Select 0, 1)  
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer  
interrupt function (four settings can be made).  
TSEL1 TSEL0  
(bit 1) (bit 0)  
Auto reset time  
tRTN  
Effects of  
RESET bits  
TSEL0,1  
Source clock  
0
0
1
1
0
1
0
1
4096 Hz /Once per 244.14 µs  
122 µs  
7.8125 ms  
7.8125 ms  
7.8125 ms  
−
64 Hz  
/ Once per 15.625 ms  
Does not operate  
when the RESET  
bit value is "1".  
Write/Read  
"Second" update /Once per second  
"Minute" update /Once per minute  
1) The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting.  
2) When the source clock has been set to "second update" or "minute update", the timing of both  
countdown and interrupts is coordinated with the clock update timing.  
2) Fixed-cycle Timer Control register (Reg - B to C)  
This register is used to set the default (preset) value for the counter. Any count value from 1 (001 h) to  
4095 (FFFh) can be set. The counter counts down based on the source clock's period, and when the count value  
changes from 001h to 000h, the TF bit value becomes "1".  
The countdown that starts when the TE bit value changes from "0" to "1" always begins from the preset value.  
Be sure to write "0" to the TE bit before writing the preset value. If a value is written while TE = "1" the first  
subsequent event will not be generated correctly.  
Address C  
Address B  
Timer Counter 1  
Timer Counter 0  
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  
2048 1024 512 256 128 64 32 16  
8
4
2
1
•
•
•
•
3) TE (Timer Enable) bit  
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.  
TE  
Data  
Description  
Stops fixed-cycle timer interrupt function.  
Starts fixed-cycle timer interrupt function.  
0
Write/Read  
1
The countdown that starts when the TE bit value changes from "0" to "1" always begins from the  
preset value.  
4) TF (Timer Flag) bit  
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has  
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.  
TF  
Data  
Description  
The TF bit is cleared to zero to prepare for the next status detection  
Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).  
0
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Fixed-cycle timer interrupt events are not detected.  
Read  
Fixed-cycle timer interrupt events are detected.  
(Result is retained until this bit is cleared to zero.)  
1
Page - 17  
ETM34E - 04  
RX − 8803 SA / LC  
5) TIE (Timer Interrupt Enable) bit  
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value  
specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated  
(/INT status remains Hi-Z).  
TIE  
Data  
Description  
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status remains Hi-Z).  
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is  
canceled (/INT status changes from low to Hi-Z).  
0
Even when the TIE bit value is "0" another interrupt event may change the /INT status to low (or  
may hold /INT = "L").  
Write/Read  
When a fixed-cycle timer interrupt event occurs, an interrupt signal is  
generated (/INT status changes from Hi-Z to low).  
1
When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin  
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt  
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).  
8.3.3. Fixed-cycle timer interrupt interval (example)  
Timer  
Source clock  
"Second"  
update  
"Minute"  
update  
Counter  
setting  
4096 Hz  
64 Hz  
TSEL1,0 = 0,0  
TSEL1,0 = 0,1  
TSEL1,0 = 1,0  
TSEL1,0 = 1,1  
0
1
2
−
−
−
1 s  
2 s  
−
15.625 ms  
31.25 ms  
1 min  
2 min  
244.14 µs  
488.28 µs  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
41  
205  
410  
10.010 ms  
50.049 ms  
100.10 ms  
500.00 ms  
640.63 ms  
3.203 s  
6.406 s  
41 s  
205 s  
410 s  
41 min  
205 min  
410 min  
2048 min  
2048  
32.000 s  
2048 s  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4095  
0.9998 s  
63.984 s  
4095 s  
4095 min  
• Time error in fixed-cycle timer  
A time error in the fixed-cycle timer will produce a positive or negative time period error in the selected  
source clock. The fixed-cycle timer's time is within the following range relative to the time setting.  
(Fixed-cycle timer's time setting ( ) − source clock period) to (timer's time setting)  
) The timer's time setting = source clock period × timer counter's division value.  
The time actually set to the timer is adjusted by adding the time described above to the  
communication time for the serial data transfer clock used for the setting.  
8.3.4. Fixed-cycle timer start timing  
Counting down of the fixed-cycle timer value starts at the rising edge of the SCL signal that occurs when the TE  
value is changed from "0" to "1" (after bit 0 is transferred).  
Address D  
SCL pin  
FSEL1 FSEL0 TSEL1 TSEL0 ACK  
TE  
SDA pin  
Internal timer  
/INT pin  
Operation of timer  
Page - 18  
ETM34E - 04  
RX − 8803 SA / LC  
8.4. Time Update Interrupt Function  
The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to  
the timing of the internal clock.  
When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that  
an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output  
from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is  
automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (fixed value) after the interrupt occurs.  
/INT operation  
example  
7.8ms  
period  
UIE = " 1 "  
UIE = " 1 " → " 0 "  
8.4.1. Time update interrupt function diagram  
" 1 "  
(7)  
" 1 "  
" 0 "  
(4)  
UIE bit  
Hi - z  
" L "  
/INT output  
(5)  
tRTN  
tRTN  
tRTN  
tRTN  
(6)  
/INT status change  
when UF bit is cleared  
to zero.  
" 1 "  
" 0 "  
(3)  
(2)  
UF bit  
period  
period  
period  
period  
(1)  
Events  
Operation in RTC  
Write operation  
(1) A time update interrupt event occurs when the internal clock's value matches either the second update time or  
the minute update time. The USEL bit's specification determines whether it is the second update time or the  
minute update time that must be matched.  
(2) When a time update interrupt event occurs, the UF bit value becomes "1".  
(3) When the UF bit value is "1" its value is retained until it is cleared to zero.  
(4) When a time update interrupt occurs, /INT pin output is low if UIE = "1".  
If UIE = "0" when a timer update interrupt occurs, the /INT pin status remains Hi-Z.  
(5) Each time an event occurs, /INT pin output is low only up to the tRTN time (which is fixed as 7.1825 ms for  
time update interrupts) after which it is automatically cleared to Hi-Z.  
/INT pin output goes low again when the next interrupt event occurs.  
(6) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UF bit value changes from "1"  
to "0".  
(7) When /INT = low, the /INT pin status changes from low to Hi-Z as soon as the UIE bit value changes from "1"  
to "0".  
Page - 19  
ETM34E - 04  
RX − 8803 SA / LC  
8.4.2. Related registers for time update interrupt functions.  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
TEST  
WADA  
TE  
TF  
FSEL1  
AF  
FSEL0  
EVF  
TSEL1  
TSEL0  
VDET  
0D, 1D  
0E, 1E  
0F, 1F  
Extension Register  
Flag Register  
Control Register  
USEL  
UF  
UIE  
ꢂ
ꢂ
VLF  
ꢂ
CSEL1  
CSEL0  
TIE  
AIE  
EIE  
RESET  
)
"o" indicates write-protected bits. A zero is always read from these bits.  
Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts  
from occurring inadvertently while entering settings.  
When the RESET bit value is "1" time update interrupt events do not occur.  
Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update  
interrupt function can be prevented from changing the /INT pin status to low.  
1) USEL (Update Interrupt Select) bit  
This bit is used to select "second" update or "minute" update as the timing for generation of time update interrupt  
events.  
USEL  
Data  
Description  
Selects "second update" (once per second) as the timing for generation of  
interrupt events  
0
Write/Read  
Selects "minute update" (once per minute) as the timing for generation of  
interrupt events  
1
2) UF (Update Flag) bit  
Once it has been set to "0", this flag bit value changes from "0" to "1" when a time update interrupt event occurs.  
When this flag bit = "1" its value is retained until a "0" is written to it.  
UF  
Data  
Description  
The UF bit is cleared to zero to prepare for the next status detection  
Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).  
0
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Time update interrupt events are not detected.  
Read  
Time update interrupt events are detected.  
(The result is retained until this bit is cleared to zero.)  
1
3) UIE (Update Interrupt Enable) bit  
When a time update interrupt event occurs (UF bit value changes from "0" to "1"), this bit selects whether to  
generate an interrupt signal (/INT status changes from Hi-Z to low) or to not generate it (/INT status remains  
Hi-Z).  
UIE  
Data  
Description  
1) Does not generate an interrupt signal when a time update interrupt event  
occurs (/INT remains Hi-Z)  
2) Cancels interrupt signal triggered by time update interrupt event (/INT  
changes from low to Hi-Z).  
0
Even when the UIE bit value is "0" another interrupt event may change the /INT status to low (or  
may hold /INT = "L").  
Write/Read  
When a time update interrupt event occurs, an interrupt signal is generated  
(/INT status changes from Hi-Z to low).  
1
When a time update interrupt event occurs, low-level output from the /INT pin occurs only when  
the UIE bit value is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically  
cleared (/INT status changes from low to Hi-Z).  
Page - 20  
ETM34E - 04  
RX − 8803 SA / LC  
8.5. Alarm Interrupt Function  
The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and  
minute settings.  
When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an  
event has occurred.  
Example of  
/INT operation  
AIE = " 1 "  
( AF = " 0 " → " 1 " )  
AF = " 1 " → " 0 " or  
AIE = " 1 " → " 0 "  
8.4.1. Diagram of alarm interrupt function  
" 1 "  
" 1 "  
" 0 "  
(4)  
AIE bit  
(5)  
Hi - z  
" L "  
(7)  
/INT output  
AF bit  
(6)  
" 1 "  
" 0 "  
(3)  
(2)  
(1)  
Event  
occurs  
RTC internal operation  
Write operation  
(1) The hour, minute, date or day when an alarm interrupt event is to occur is set in advance along with the  
WADA bit, and when the setting matches the current time an interrupt event occurs.  
(Note) Even if the current date/time is used as the setting, the alarm will not occur until the counter counts up  
to the current date/time (i.e., an alarm will occur next time, not immediately).  
(2) When a time update interrupt event occurs, the AF bit values becomes "1".  
(3) When the AF bit = "1", its value is retained until it is cleared to zero.  
(4) If AIE = "1" when an alarm interrupt occurs, the /INT pin output goes low.  
When an alarm interrupt event occurs, /INT pin output goes low, and this status is then held until it is  
cleared via the AF bit or AIE bit.  
(5) If the AIE value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low to  
Hi-Z. After the alarm interrupt occurs and before the AF bit value is cleared to zero, the /INT status can be  
controlled via the AIE bit.  
(6) If the AF bit value is changed from "1" to "0" while /INT is low, the /INT status immediately changes from low  
to Hi-Z.  
(7) If the AIE bit value is "0" when an alarm interrupt occurs, the /INT pin status remains Hi-Z.  
Page - 21  
ETM34E - 04  
RX − 8803 SA / LC  
8.5.2. Related registers  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
ꢂ
ꢂ
ꢂ
ꢂ
01, 12  
02, 13  
03, 14  
04, 15  
MIN  
HOUR  
WEEK  
DAY  
40  
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
ꢂ
6
ꢂ
20  
10  
08, 18  
09, 19  
MIN Alarm  
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
AE  
AE  
40  
•
6
•
WADA  
ꢂ
20  
20  
5
20  
USEL  
10  
10  
4
10  
TE  
TF  
TIE  
8
8
3
4
4
2
2
2
1
2
1
1
0
0A, 1A  
AE  
8
4
1
TEST  
FSEL1  
AF  
AIE  
FSEL0  
EVF  
EIE  
TSEL1  
VLF  
ꢂ
TSEL0  
VDET  
RESET  
0D, 1D  
0E, 1E  
0F, 1F  
Extension Register  
Flag Register  
Control Register  
ꢂ
UF  
CSEL1  
CSEL0  
UIE  
1) "o" indicates write-protected bits. A zero is always read from these bits.  
2) Bits marked with "•" are RAM bits that can contain any value and are read/write-accessible.  
Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts  
from occurring inadvertently while entering settings.  
When the RESET bit value is "1" alarm interrupt events do not occur.  
When the alarm interrupt function is not being used, the Alarm registers (Reg - 8 to A) can be used as a RAM  
register. In such cases, be sure to write "0" to the AIE bit.  
When the AIE bit value is "1" and the Alarm registers (Reg - 8 to A) is being used as a RAM register, /INT may be  
changed to low level unintentionally.  
1) WADA (Week Alarm /Day Alarm) bit  
The alarm interrupt function uses either "Day" or "Week" as its target. The WADA bit is used to specify either  
WEEK or DAY as the target for alarm interrupt events.  
WADA  
Data  
Description  
Sets WEEK as target of alarm function  
(DAY setting is ignored)  
0
Write/Read  
Sets DAY as target of alarm function  
(WEEK setting is ignored)  
1
2) Alarm registers  
Address  
Function  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
08, 18  
09, 19  
MIN Alarm  
AE  
AE  
40  
•
6
20  
20  
5
10  
10  
4
8
8
3
8
4
4
2
4
2
2
1
2
1
1
0
1
HOUR Alarm  
WEEK Alarm  
DAY Alarm  
0A,1A  
AE  
20  
10  
•
The hour, minute, date or day when an alarm interrupt event will occur is set using this register and the  
WADA bit.  
In the WEEK alarm /Day alarm register (Reg - A), the setting selected via the WADA bit determines whether  
WEEK alarm data or DAY alarm data will be set. If WEEK has been selected via the WADA bit, multiple  
days can be set (such as Monday, Wednesday, Friday, Saturday).  
When the settings made in the alarm registers and the WADA bit match the current time, the AF bit value is  
changed to "1". At that time, if the AIE bit value has already been set to "1", the /INT pin goes low.  
1) The register that "1" was set to "AE" bit, doesn't compare alarm.  
(Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A):  
Only the hour and minute settings are used as alarm comparison targets. The week and date settings  
are not used as alarm comparison targets.  
As a result, alarm occurs if only an hour and minute accords with alarm data.  
2) If all three AE bit values are "1" the week/date settings are ignored and an alarm interrupt event will  
occur once per minute.  
Page - 22  
ETM34E - 04  
RX − 8803 SA / LC  
3) AF (Alarm Flag) bit  
When this flag bit value is already set to "0", occurrence of an alarm interrupt event changes it to "1". When this  
flag bit value is "1", its value is retained until a "0" is written to it.  
AF  
Data  
Description  
The AF bit is cleared to zero to prepare for the next status detection  
Clearing this bit to zero enables /INT low output to be canceled (/INT remains Hi-Z) when an alarm  
interrupt event has occurred.  
0
Write  
1
0
This bit is invalid after a "1" has been written to it.  
Alarm interrupt events are not detected.  
Read  
Alarm interrupt events are detected.  
(Result is retained until this bit is cleared to zero.)  
1
4) AIE (Alarm Interrupt Enable) bit  
When an alarm interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies  
whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status  
remains Hi-Z).  
AIE  
Data  
Description  
1) When an alarm interrupt event occurs, an interrupt signal is not  
generated or is canceled (/INT status remains Hi-Z).  
2) When an alarm interrupt event occurs, the interrupt signal is canceled  
(/INT status changes from low to Hi-Z).  
0
Even when the AIE bit value is "0" another interrupt event may change the /INT status to low  
(or may hold /INT = "L").  
Write/Read  
When an alarm interrupt event occurs, an interrupt signal is generated (/INT  
status changes from Hi-Z to low).  
1
When an alarm interrupt event occurs, low-level output from the /INT pin occurs only when the  
AIE bit value is "1". This value is retained (not automatically cleared) until the AF bit is cleared  
to zero.  
8.5.2. Examples of alarm settings  
1) Example of alarm settings when "Day" has been specified (and WADA bit = "0")  
Reg – A  
Reg - 9  
Reg - 8  
Day is specified  
bit bit bit bit bit bit bit bit  
HOUR  
Alarm  
MIN  
Alarm  
7
6
5
4
3
2
1
0
WADA bit = "0"  
AE S  
F
T
W
T
M
S
Monday through Friday, at 7:00 AM  
Minute value is ignored  
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
07 h  
80 h FF h  
30 h  
Every Saturday and Sunday, for 30 minutes  
each hour Hour value is ignored  
80 h FF h  
18 h  
0
1
1
1
1
1
1
1
1
Every day, at 6:59 AM  
59 h  
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ: Don't care  
2) Example of alarm settings when "Day" has been specified (and WADA bit = "1")  
Reg - A  
Reg - 9  
Reg - 8  
Day is specified  
bit  
6
bit  
7
bit bit bit bit bit bit  
HOUR  
Alarm  
MIN  
Alarm  
5
4
3
2
1
0
WADA bit = "1"  
AE  
20 10 08 04 02 01  
•
First of each month, at 7:00 AM  
Minute value is ignored  
0
0
0
0
0
1
0
0
0
1
0
0
1
1
07 h  
80 h FF h  
30 h  
15th of each month, for 30 minutes each  
0
1
0
80 h FF h  
18 h  
hour  
Hour value is ignored  
Every day, at 6:59 PM  
59 h  
Χ
Χ
Χ
Χ
Χ
Χ
Χ
Χ: Don't care  
Page - 23  
ETM34E - 04  
RX − 8803 SA / LC  
2
8.6. Reading/Writing Data via the I C Bus Interface  
8.6.1. Overview of I2C-BUS  
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A  
combination of these two signals is used to transmit and receive communication start/stop signals, data transfer  
signals, acknowledge signals, and so on.  
Both the SCL and SDA signals are held at high level whenever communications are not being performed.  
The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at  
high level.  
During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and  
on the receiving side the data is output while the SCL line is at high level.  
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a  
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications  
only when its slave address matches the slave address in the received data. In either case, the data is transferred  
via the SCL line at a rate of one bit per clock pulse.  
8.6.2. System configuration  
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND  
connections to multiple devices.  
SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both  
held at high level when the bus is released (when communication is not being performed).  
V
DD  
SDA  
SCL  
Master  
Slave  
Master  
Slave  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Transmitter/  
Receiver  
Other I2C bus device  
CPU, etc.  
RX - 8803  
Any device that controls the data transmission and data reception is defined as a "Master".  
and any device that is controlled by a master device is defined as a “Slave”.  
The device transmitting data is defined as a “Transmitter” and the device receiving data is defined as a receiver”  
In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is  
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a  
transmitter or receiver depending on these conditions.  
Page - 24  
ETM34E - 04  
RX − 8803 SA / LC  
8.6.3. Starting and stopping I2C bus communications  
START  
condition  
Repeated START(RESTART)  
condition  
STOP  
condition  
SCL  
SDA  
[ S ]  
[ Sr ]  
[ P ]  
0.95 s ( Max. )  
1) START condition, repeated START condition, and STOP condition  
(1) START condition  
•
The SDA level changes from high to low while SCL is at high level.  
(2) STOP condition  
2
• This condition regulates how communications on the I C-BUS are terminated.  
The SDA level changes from low to high while SCL is at high level.  
(3) Repeated START condition (RESTART condition)  
• In some cases, the START condition occurs between a previous START condition and the next  
STOP condition, in which case the second START condition is distinguished as a RESTART  
condition. Since the required status is the same as for the START condition, the SDA level changes  
from high to low while SCL is at high level.  
2) Caution points  
1) The master device always controls the START, RESTART, and STOP conditions for communications.  
2) The master device does not impose any restrictions on the timing by which STOP conditions affect  
transmissions, so communications can be forcibly stopped at any time while in progress. (However,  
this is only when this RTC module is in receiver mode (data reception mode = SDA released).  
3) When communicating with this RTC module, the series of operations from transmitting the START  
condition to transmitting the STOP condition should occur within 0.95 seconds. (A RESTART  
condition may be sent between a START condition and STOP condition, but even in such cases the  
series of operations from transmitting the START condition to transmitting the STOP condition should  
still occur within 0.95 seconds.)  
If this series of operations requires 0.95 seconds or longer, the I2C bus interface will be automatically  
cleared and set to standby mode by this RTC module's bus timeout function. Note with caution that  
both write and read operations are invalid for communications that occur during or after this auto  
clearing operation. (When the read operation is invalid, all data that is read has a value of "1").  
Restarting of communications begins with transfer of the START condition again  
4) When communicating with this RTC module, wait at least 1.3 µs (see the tBUF rule) between  
transferring a STOP condition (to stop communications) and transferring the next START condition (to  
start the next round of communications).  
STOP  
condition  
START  
condition  
SCL  
SDA  
[ P ]  
[ S ]  
µ
61 s (Min.)  
Page - 25  
ETM34E - 04  
RX − 8803 SA / LC  
8.6.4. Data transfers and acknowledge responses during I2C-BUS communications  
1) Data transfers  
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit  
on the amount (bytes) of data that are transferred between the START condition and STOP condition.  
(However, the transfer time must be no longer than 0.95 seconds.)  
The address auto increment function operates during both write and read operations.  
After address Fh, incrementation goes to address 0h.  
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low  
level. The receiver (receiving side) receives data while the SCL line is at high level.  
SCL  
SDA  
Data is valid  
Data can be  
when data line is  
changed  
stable  
Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a  
START, RESTART, or STOP condition.  
2) Data acknowledge response (ACK signal)  
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an  
8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal  
communication has not been established. (This does not include instances where the master device intentionally  
does not generate an ACK signal.)  
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the  
transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.  
SCL from Master  
1
2
8
9
SDA from transmitter  
(sending side)  
Release SDA  
SDA from receiver  
(receiving side)  
Low active  
ACK signal  
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is  
released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer  
resumes when the Master becomes the transmitter.  
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent  
from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter  
continues to release the SDA and awaits a STOP condition from the Master.  
8.6.5. Slave address  
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a  
chip select pin, slave addresses are allocated to each device.  
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The  
receiving device responds to this communication only when the specified slave address it has received matches its  
own slave address.  
Slave addresses have a fixed length of 7 bits. This RTC's slave address is [0110 010 ].  
An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers.  
Slave address  
R/W bit  
Transfer data  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
Read  
Write  
65 h  
64 h  
1 (= Read)  
0 (= Write)  
0
1
1
0
0
1
0
Page - 26  
ETM34E - 04  
RX − 8803 SA / LC  
8.6.6. I2C bus protocol  
In the following sequence descriptions, it is assumed that the CPU is the master and the RX-8803 is the slave.  
a. Address specification write sequence  
Since the RX-8803 includes an address auto increment function, once the initial address has been specified,  
the RX-8803 increments (by one byte) the receive address each time data is transferred.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8803's slave address with the R/W bit set to write mode.  
(3) Check for ACK signal from RX-8803.  
(4) CPU transmits write address to RX-8803.  
(5) Check for ACK signal from RX-8803.  
(6) CPU transfers write data to the address specified at (4) above.  
(7) Check for ACK signal from RX-8803.  
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.  
(9) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5)  
0
(6)  
(7)  
0
(8)  
(9)  
P
Slave address  
0
Address  
Data  
Data  
0
R/W  
ACK signal from RX-8801  
b. Address specification read sequence  
After using write mode to write the address to be read, set read mode to read the actual data.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8803's slave address with the R/W bit set to write mode.  
(3) Check for ACK signal from RX-8803.  
(4) CPU transfers address for reading from 8803.  
(5) Check for ACK signal from RX-8803.  
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]).  
(7) CPU transfers RX-8803's slave address with the R/W bit set to read mode.  
(8) Check for ACK signal from RX-8803 (from this point on, the CPU is the receiver and the RX-8803 is  
the transmitter).  
(9) Data from address specified at (4) above is output by the RX-8803.  
(10) CPU transfers ACK signal to RX-8803.  
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.  
(12) CPU transfers ACK signal for "1".  
(13) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5) (6)  
Sr  
(7)  
(8)  
0
(9)  
(10)  
0
(11)  
(12) (13)  
Slave address  
0
Address  
0
Slave address  
1
Data  
Data  
1
P
R/W  
R/W  
ACK from RX-8801  
ACK from CPU  
c. Read sequence when address is not specified  
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read  
operation is the previously accessed address + 1.  
(1) CPU transfers start condition [S].  
(2) CPU transmits the RX-8803's slave address with the R/W bit set to read mode.  
(3) Check for ACK signal from RX-8803 (from this point on, the CPU is the receiver and the RX-8803 is the  
transmitter).  
(4) Data is output from the RX-8803 to the address following the end of the previously accessed address.  
(5) CPU transfers ACK signal to RX-8803.  
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX-8803.  
(7) CPU transfers ACK signal for "1".  
(8) CPU transfers stop condition [P].  
(1)  
S
(2)  
(3)  
0
(4)  
(5)  
0
(6)  
(7) (8)  
Slave address  
1
Data  
Data  
1
P
R/W  
ACK from RX-8801  
ACK from CPU  
Page - 27  
ETM34E - 04  
RX − 8803 SA / LC  
8.7. Backup and Recovery  
V
V
DD  
V
DET  
CLK  
0 V  
t
R1  
t
F
tR2  
Back up  
Item  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit.  
Power supply  
detection voltage ( 1 )  
Power supply  
detection voltage ( 2 )  
Power supply  
V
DET  
2.2  
1.6  
V
−
−
−
−
V
LOW  
V
t
F
2
µs /V  
ms /V  
drop time  
Initial power-up time  
t
R1  
10  
5
1.6V → VDD ≤ 3.6V  
1.6V → VDD > 3.6V  
µs /V  
µs /V  
Clock maintenance  
power-up time  
t
R2  
15  
Page - 28  
ETM34E - 04  
RX − 8803 SA / LC  
8.8. Connection with Typical Microcontroller  
VDD  
D1: Schottky Barrier  
Diode  
Note  
SCL  
SDA  
I2C-BUS  
Master  
V
DD  
SCL  
RX-8803  
SLAVE ADRS = 0110 010*  
VDD  
SDA  
GND  
Pull up Registor  
t
r
R =  
C
BUS  
SCL  
SDA  
( I2C Bus )  
Note : It uses the secondary battery or a lithium battery. When using the seconding battery, the diode is not required.  
When using the lithium battery, the diode is required.  
For detailed value on the resistance, please consult a battery maker.  
8.9. When used as a clock source (32 kHz-TCXO)  
RX-8803  
VDD  
VDD  
VDD  
T1  
SCL  
SDA  
TEST  
T2  
0.1 µF  
FOUT  
/INT  
32.768kHz  
O E  
FOE  
EVIN  
GND  
Page - 29  
ETM34E - 04  
RX − 8803 SA / LC  
9. External Dimensions / Marking Layout  
9.1. RX − 8803 SA  
9.1.1. External dimensions  
RX − 8803 SA ( SOP − 14pin )  
• External dimensions  
• Recommended soldering pattern  
10.1 ± 0.2  
0° - 10°  
#14  
#8  
1.4  
5.4  
1.4  
5.0 7.4  
±
0.2  
0.1  
0.6  
#1  
#7  
0.15  
1.27  
0.7  
0.05  
Min.  
1.27 × 6 = 7.62  
3.2  
±
0.35  
1.27 1.2  
Unit : mm  
The cylinder of the crystal oscillator can be seen in this area ( front ),  
but it has no affect on the performance of the device.  
9.1.2. Marking layout  
RX − 8803 SA ( SOP − 14pin )  
UA : A  
UB : Blank  
UC : C  
Frequency  
Stability  
Type  
Logo  
R 8803 A  
E A123B  
AA : W  
Production lot  
Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning.  
Page - 30  
ETM34E - 04  
RX − 8803 SA / LC  
9.2. RX − 8803 LC  
9.2.1. External dimensions  
RX − 8803 LC ( VSOJ − 20pin )  
• External dimensions  
• Recommended soldering pattern  
3.7 ± 0.2  
0.1  
2.5  
# 12  
# 7  
0.5  
0.27  
# 1  
# 6  
0.08  
M
2.77  
0.5  
0.22  
Unit : mm  
0.08  
The cylinder of the liquid crystal oscillator can be seen in this area ( back and front ),  
but it has no affect on the performance of the device.  
9.2.2. Marking layout  
RX − 8803 LC ( VSOJ − 20pin )  
UA : A  
UB : Blank  
UC : C  
Type  
Logo  
Frequency  
Stability  
AA : W  
E8803A  
A123B  
Production lot  
#1 Pin Mark  
Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning.  
Page - 31  
ETM34E - 04  
RX − 8803 SA / LC  
10. Application notes  
1) Notes on handling  
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.  
(1) Static electricity  
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by  
a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.  
In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used  
with this module, which should also be grounded when such devices are being used.  
(2) Noise  
If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up."  
In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1 µF as close as possible  
to the power supply pins (between VDD and GNDs). Also, avoid placing any device that generates high level of electronic  
noise near this module.  
* Do not connect signal lines to the shaded area in the figure shown in Fig. 1 and, if possible, embed this area in a GND land.  
(3) Voltage levels of input pins  
When the input pins are at the mid-level, this will cause increased current consumption and a reduced noise margin, and can  
impair the functioning of the device. Therefore, try as much as possible to apply the voltage level close to VDD or GND.  
(4) Handling of unused pins  
Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can  
lead to unstable voltage level and malfunctions due to noise. Therefore, pull-up or pull-down resistors should be provided for  
all unused input pins.  
2) Notes on packaging  
(1) Soldering heat resistance.  
If the temperature within the package exceeds +260 °C, the characteristics of the crystal oscillator will be degraded and it may  
be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting  
temperature and time before mounting this device. Also, check again if the mounting conditions are later changed.  
* See Fig. 2 profile for our evaluation of Soldering heat resistance for reference.  
(2) Mounting equipment  
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in  
some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the  
mounting conditions are later changed, the same check should be performed again.  
(3) Ultrasonic cleaning  
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during  
ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time,  
state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic  
cleaning.  
(4) Mounting orientation  
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before  
mounting.  
(5) Leakage between pins  
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the  
device is dry and clean before supplying power to it.  
Fig. 1 : Example GND Pattern  
RX - 8803 SA  
Fig. 2 : Reference profile for our evaluation of Soldering heat resistance.  
Temperature [ °C ]  
300  
OVER  
TP  
; +260 °C  
+255 °C  
tp ; at least 30 s  
250  
200  
150  
100  
50  
Ramp-up rate  
+3 °C/s Max.  
Ramp-down rate  
-6 °C/s Max.  
tL  
TL  
; +217 °C  
; +200 °C  
60 s to 150 s  
( +217 °C over )  
Ts max  
RX - 8803 LC  
ts  
Ts min ; +150 °C  
60 s to 120 s  
( +150 °C to +200 °C)  
The shaded part (  
where a GND pattern should be set  
without getting too close to a signal line  
) indicates  
Time +25 °C to Peak  
0
60  
120 180 240 300 360 420 480 540 600 660 720 780  
Time [ s ]  
Page - 32  
ETM34E - 04  
Application Manual  
AMERICA  
EPSON ELECTRONICS AMERICA, INC.  
HEADQUARTER  
214 Devcon Drive, San Jose, CA 95112, U.S.A.  
Phone: (1)800-228-3964  
FAX :(1)408-922-0238  
http://www.eea.epson.com  
Chicago Office  
1827 Walden Office Square. Suite 450 Schaumburg, IL 60173  
Phone: (1)847-925-8350  
Fax: (1)847 925-8965  
El Segundo Office  
1960 E. Grand Ave., 2nd Floor, El Segundo, CA 90245, U.S.A.  
Phone: (1)800-249-7730 (Toll free) : (1)310-955-5300 (Main)  
Fax: (1)310-955-5400  
EUROPE  
EPSON EUROPE ELECTRONICS GmbH  
HEADQUARTER Riesstrasse 15, 80992 Munich, Germany  
Phone: (49)-(0)89-14005-0 Fax: (49)-(0)89-14005-110  
http://www.epson-electronics.de  
ASIA  
EPSON (China) CO., LTD.  
7F, Jinbao Building No.89 Jinbao Street Dongcheng District, Beijing, China, 100005  
Phone: (86) 10-8522-1199 Fax: (86) 10-8522-1120  
http://www.epson.com.cn  
Shanghai Branch  
Shenzhen Branch  
High-Tech Building,900 Yishan Road Shanghai 200233,China  
Phone: (86) 21-5423-5577 Fax: (86) 21-5423-4677  
12/F, Dawning Mansion,#12 Keji South Road, Hi-Tech Park,Shenzhen, China  
Phone: (86) 755-26993828 Fax: (86) 755-26993838  
EPSON HONG KONG LTD.  
Unit 715-723 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong  
Phone: (852) 2585-4600 Fax: (852) 2827-2152  
http://www.epson.com.hk  
EPSON TAIWAN TECHNOLOGY & TRADING LTD.  
14F, No.7, Song Ren Road, Taipei 110  
Phone: (886) 2-8786-6688 Fax: (886)2-8786-6660  
http://www.epson.com.tw  
EPSON SINGAPORE PTE. LTD.  
No 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633.  
Phone: (65)- 6586-5500 Fax: (65) 6271-3182  
http://www.epson.com.sg  
SEIKO EPSON CORPORATION KOREA Office  
5F, KLI 63 Building,60 Yoido-dong, Youngdeungpo-Ku, Seoul, 150-763, Korea  
Phone: (82) 2-784-6027 Fax: (82) 2-767-3677  
http://www.epson-device.co.kr  
Distributor  
Electronic devices information on WWW server  
http://www5.epsondevice.com/en/quartz/index.html  
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