Philips Semiconductors
Product specification
SDH/SONET, Fibre Channel and Gigabit
Ethernet multi-rate fibre optic receiver
TZA3052AHW
Demultiplexer
HIGH. Boundaries are recognized on receipt of the second
A2 byte and FP goes HIGH for one POCLK cycle.
The demultiplexer converts the serial input bit stream to
parallel formats of 1 : 16, 1 : 10, 1 : 8 or 1 : 4. The output
data is available on a scalable bus with LVPECL outputs
(see Fig.10). In addition to the deserializing function, the
demultiplexer comprises a parity calculator and a frame
header detection circuit. The calculated parity (EVEN) is
output at pins PARITY and PARITYQ. A detected frame
header pattern in the data stream results in a 1 clock cycle
wide pulse on output pins FP and FPQ.
The first two A2 bytes in the frame header are the first data
word to be reported with the correct alignment on the
outgoing data bus (D00 to D15).
When interfacing with a section terminating device, ENBA
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct
(see Fig.8). Byte boundary detection is disabled on the first
FP pulse after ENBA has gone LOW.
The number of parallel data bus outputs that are used
depends on the multiplexing ratio selected by pins DMXR0
and DMXR1. Any unused parallel data bus outputs are
disabled. The configuration settings and active outputs for
each demultiplexing ratio are shown in Table 3.
Figure 9 shows frame and byte boundary detection
activated on the rising edge of ENBA, and deactivated by
the first FP pulse after ENBA has gone LOW.
If ENBA is LOW, no active alignment takes place.
However, if the framing pattern happens to occur in the
formatted data, a frame pulse will still be output on pins FP
and FPQ.
Table 3 Setting the demultiplexing ratio
ACTIVE
OUTPUTS
LSB TO MSB
PIN
PIN
DEMULTIPLEXER
RATIO
DMXR1 DMXR0
Frame detection for Gigabit Ethernet
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
1 : 4
1 : 8
D6 to D9
D4 to D11
D3 to D12
D0 to D15
For Gigabit Ethernet the frame header detection operates
on a 10-bit pattern. The frame header pattern is
00 1111 1010 which equals the K28.5 character plus
alternating 010. The occurrence of this pattern generates
a frame pulse on pins FP and FPQ.
1 : 10
1 : 16
The highest supported speed for the parallel data bus is
400 Mbit/s. Therefore, a demultiplexing ratio of 1 : 4 will
support bit rates up to 1.6 Gbit/s. For OC3/STM1,
OC12/STM4, GE and FC all bus widths are supported. For
OC48/STM16, OC48+FEC/STM16+FEC, 2FC and 10GE
the 4-bit bus width option is not supported.
Parity generation
Output pins PARITY and PARITYQ provide the EVEN
parity of the byte or word that is currently available on the
parallel bus.
Loop mode I/Os
Frame detection for SDH/SONET
The IC can be used in a ‘diagnostic loop back’ mode by
setting pin ENLINQ to LOW. In this case, the demultiplexer
will select inputs DLOOP and DLOOPQ, CLOOP and
CLOOPQ instead of taking the input from the DCR. The
‘line loop back’ mode is activated by setting pin ENLOUTQ
to LOW. Now, the recovered clock and serial data will be
available at output pins DOUT and DOUTQ and COUT
and COUTQ.
Byte alignment is enabled if the Enable Byte Alignment
(ENBA) input is HIGH. Whenever a 32-bit sequence
matches the frame header pattern, the incoming data is
formatted into logical bytes or words and a frame pulse is
generated on differential outputs FP and FPQ.
The frame header pattern is F6F62828H, corresponding to
the middle section of the standard SDH/SONET frame
header (the last two A1 bytes plus the first two A2 bytes).
RF I/Os
Figure 7 shows a typical SDH/SONET reframe sequence
involving byte alignment.
The RF CML outputs have an amplitude of 80 mV (p-p)
single-ended. The termination scheme is AC coupled (see
Fig.11).
Frame and byte boundary detection is enabled on the
rising edge of ENBA and remains enabled while ENBA is
2003 Nov 19
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