W173
4. PCB power supply traces should be at least 20 mils wide to
assure adequate trade impedance recommend Power
Supply Schematic–Single Voltage Supply Operation.
Power Supply Connections
The recommended single voltage power supply configuration
for the W173 is shown schematically in Figure 1. These recom-
mendations should be followed to both ensure adequate
device performance and to control EMI. The major consider-
ations can be summarized as follows:
Ground Connections
All ground connections should be made to the main system
ground plane. These connections should be as short as
possible. No cuts should be made in the ground plane around
the clock device since this can increase system EMI and
reduce clock performance.
µF decoupling capacitor
1. Decoupling Capacitor—A 0.1-
should be used for each VDD pin to minimize crosstalk be-
tween output frequencies. The trace to the VDD pin and to
the ground via should be as short as possible.
Clock Output Lines
2. Ferrite Bead (FB)—A common supply connection should
be used for all W173 VDD pins. A ferrite bead should be
used on this common supply as shown to remove high
frequency system noise.
1. The clock line width should be set to provide a 60 trace
impedance. This width will vary depending on the PCB ma-
terial; the PCB supplier can suggest what width to use for
a 60 clock line. In general, an 8-mil trace will provide a
60impedance on a multi-level board.
µF capacitor filters
µF Supply Filter Capacitor—The 22-
3. 22-
low frequency supply noise that may produce clock output
jitter. Depending on the particular application, this capacitor
may not be required; its use should be considered optional.
Mounting pads should be implemented in PCB layout. Use
of this capacitor in production should be determined upon
prototype evaluation.
2. Theseriesterminationresistor (sometimescalled“damping
resistor”) must be placed in series with the clock line as
close to the clock output as possible (within one inch).
3. Assume an output resistance from the W173 of 40,
choose series resistors appropriate to the number of driven
traces.
System VDD
FB
µF
22
C1
VDD
VDD
X1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
µF
µF
0.1
µF
µF
0.1
0.1
6.6MHz
GND
X2
GND
OE
13.2MHz
VDD
0.1
0.1
VDD
GND
50MHz
GND
10MHz
VDD
µF
Figure 1. Test Circuit
......... Document #: 38-07313 Rev. *B Page Page 3 of 5 of 5
