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TXS0102YZTR

型号：

TXS0102YZTR

品牌：

TI[ TEXAS INSTRUMENTS ]

页数：

27 页

PDF大小：

1557 K

下载PDF手册
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR  
FOR OPEN-DRAIN AND PUSH-PULL APPLICATIONS  
Check for Samples: TXS0102  
1
FEATURES  
TYPICAL LEVEL-SHIFTER  
APPLICATIONS  
2
•
No Direction-Control Signal Needed  
Max Data Rates  
•
•
•
I2C/SMBus  
UART  
•
–
–
24 Mbps (Push Pull)  
2 Mbps (Open Drain)  
GPIO  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
DCT OR DCU PACKAGE  
(TOP VIEW)  
1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on  
B1  
1
2
3
4
8
7
6
5
B2  
B port (VCCA ≤ VCCB  
)
VCC Isolation Feature – If Either VCC Input Is at  
GND, Both Ports Are in the High-Impedance  
State  
GND  
VCCA  
A2  
VCCB  
OE  
A1  
•
•
•
•
No Power-Supply Sequencing Required –  
Either VCCA or VCCB Can Be Ramped First  
DQE OR DQM PACKAGE  
(TOP VIEW)  
Ioff Supports Partial-Power-Down Mode  
Operation  
1
2
3
4
8
7
6
5
VCCA  
A1  
VCCB  
B1  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A2  
B2  
ESD Protection Exceeds JESD 22  
GND  
OE  
–
A Port  
YZP PACKAGE  
(BOTTOM VIEW)  
–
–
–
2500-V Human-Body Model (A114-B)  
250-V Machine Model (A115-A)  
D1  
C1  
B1  
A1  
D2  
C2  
B2  
A2  
4 5  
3 6  
2 7  
1 8  
A2  
A1  
1500-V Charged-Device Model (C101)  
VCCA  
OE  
–
B Port  
VCCB  
GND  
B2  
–
–
–
8-kV Human-Body Model (A114-B)  
B1  
250-V Machine Model (A115-A)  
1500-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital  
switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails,  
with the A ports supporting operating voltages from 1.65 V to 3.6 V while it tracks the VCCA supply, and the B  
ports supporting operating voltages from 2.3 V to 5.5 V while it tracks the VCCB supply. This allows the support of  
both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the  
1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.  
When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly  
reduces the power-supply quiescent current consumption.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoStar is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2011, Texas Instruments Incorporated  
TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(3)  
2H_  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP  
Reel of 3000  
TXS0102YZPR  
SON – DQE  
SON – DQM  
Reel of 5000  
Reel of 3000  
Reel of 3000  
Tube of 250  
Reel of 3000  
TXS0102DQER  
TXS0102DQMR  
TXS0102DCTR  
TXS0102DCTT  
TXS0102DCUR  
2H  
2HR  
–40°C to 85°C  
NFE_ _ _  
NFE _ _ _  
NFE_  
SSOP – DCT  
VSSOP – DCU  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and wafer fab/assembly site.  
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
PIN DESCRIPTION  
NO.  
NAME  
TYPE  
FUNCTION  
DCT, DQE,  
YZP  
DCU  
DQM  
1
2
3
4
5
6
4
1
3
2
A1  
B1  
C1  
D1  
D2  
B2  
GND  
VCCA  
A2  
I/O  
GND  
Power  
I/O  
Input/output B. Referenced to VCCB  
Ground  
.
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB  
Input/output A. Referenced to VCCA  
Input/output A. Referenced to VCCA  
.
.
A1  
I/O  
Output enable (active High). Pull OE low to place all outputs in 3-state mode.  
Referenced to VCCA  
6
5
C2  
OE  
Input  
.
7
8
8
7
B2  
A2  
VCCB  
B1  
Power  
I/O  
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V  
Input/output B. Referenced to VCCB  
.
TYPICAL OPERATING CIRCUIT  
1.8 V  
3.3 V  
0.1 mF  
0.1 mF  
1 mF  
V
CCA  
V
CCB  
1.8 V  
3.3 V  
System  
Controller  
System  
OE  
A1  
A2  
B1  
B2  
Data  
Data  
2
Submit Documentation Feedback  
Copyright © 2007–2011, Texas Instruments Incorporated  
Product Folder Link(s): TXS0102  
 
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
ABSOLUTE MAXIMUM RATINGS(1)  
over recommended operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
MAX  
4.6  
6.5  
4.6  
6.5  
4.6  
6.5  
UNIT  
V
VCCA  
VCCB  
Supply voltage range  
Supply voltage range  
V
A port  
B port  
A port  
B port  
A port  
B port  
VI < 0  
VI  
Input voltage range(2)  
V
V
V
Voltage range applied to any output  
VO  
VO  
in the high-impedance or power-off state(2)  
–0.5 VCCA + 0.5  
Voltage range applied to any output in the high or low state(2) (3)  
–0.5 VCCB + 0.5  
IIK  
IOK  
IO  
Input clamp current  
–50  
–50  
±50  
mA  
mA  
mA  
mA  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCCA, VCCB, or GND  
±100  
220  
227  
261  
TBD  
102  
DCT package  
DCU package  
DQE package  
DQM package  
YZP package  
θJA  
Package thermal impedance(4)  
°C/W  
Tstg  
Storage temperature range  
–65  
150  
°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The value of VCCA and VCCB are provided in the recommended operating conditions table.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
RECOMMENDED OPERATING CONDITIONS(1) (2)  
VCCA  
VCCB  
MIN  
1.65  
MAX  
UNIT  
V
VCCA  
VCCB  
Supply voltage(3)  
Supply voltage  
3.6  
2.3  
5.5  
V
1.65 V to 1.95 V  
2.3 V to 3.6 V  
VCCI – 0.2  
VCCI – 0.4  
VCCI – 0.4  
VCCI  
A-port I/Os  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
VCCI  
High-level  
input voltage  
VIH  
V
V
B-port I/Os  
VCCI  
1.65 V to 3.6 V  
OE input  
VCCA × 0.65  
5.5  
A-port I/Os  
0
0
0
0.15  
Low-level  
input voltage  
(4)  
VIL  
B-port I/Os  
1.65 V to 3.6 V  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
0.15  
OE input  
VCCA × 0.35  
A-port I/Os, push-pull driving  
B-port I/Os, push-pull driving  
Control input  
10  
10  
10  
85  
Input transition  
rise or fall rate  
Δt/Δv  
1.65 V to 3.6 V  
ns/V  
TA  
Operating free-air temperature  
–40  
°C  
(1) VCCI is the supply voltage associated with the input port.  
(2) VCCO is the supply voltage associated with the output port.  
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.  
(4) The maximum VIL value is provided to ensure that a valid VOL is maintained. The VOL value is VIL plus the voltage drop across the  
pass-gate transistor.  
Copyright © 2007–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TXS0102  
TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
ELECTRICAL CHARACTERISTICS(1) (2) (3)  
over recommended operating free-air temperature range (unless otherwise noted)  
TA = 25°C  
–40°C to 85°C  
MIN MAX  
TEST  
CONDITIONS  
PARAMETER  
VOHA  
VOLA  
VOHB  
VOLB  
II  
VCCA  
VCCB  
UNIT  
MIN TYP MAX  
IOH = –20 μA,  
VIB ≥ VCCB – 0.4 V  
1.65 V to 3.6 V  
1.65 V to 3.6 V  
1.65 V to 3.6 V  
1.65 V to 3.6 V  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
VCCA × 0.67  
V
V
V
V
IOL = 1 mA,  
VIB ≤ 0.15 V  
0.4  
IOH = –20 μA,  
VIA ≥ VCCA – 0.2 V  
VCCB × 0.67  
IOL = 1 mA,  
VIA ≤ 0.15 V  
0.4  
OE  
1.65 V to 3.6 V  
0 V  
2.3 V to 5.5 V  
0 to 5.5 V  
0 V  
±1  
±1  
±1  
±1  
±2  
±2  
±2  
±2  
2.4  
2.2  
–1  
12  
–1  
1
μA  
μA  
μA  
μA  
A port  
B port  
A or B port  
Ioff  
0 to 3.6 V  
1.65 V to 3.6 V  
1.65 V to VCCB  
3.6 V  
IOZ  
2.3 V to 5.5 V  
2.3 V to 5.5 V  
0 V  
VI = VO = open,  
IO = 0  
ICCA  
μA  
μA  
0 V  
5.5 V  
1.65 V to VCCB  
3.6 V  
2.3 V to 5.5 V  
0 V  
VI = VO = open,  
IO = 0  
ICCB  
0 V  
5.5 V  
VI = VCCI or GND,  
IO = 0  
ICCA + ICCB  
1.65 V to VCCB  
2.3 V to 5.5 V  
14.4  
3.5  
μA  
CI  
OE  
3.3 V  
3.3 V  
3.3 V  
3.3 V  
2.5  
10  
5
pF  
A or B port  
A port  
B port  
Cio  
6
pF  
6
7.5  
(1) VCCI is the VCC associated with the input port.  
(2) VCCO is the VCC associated with the output port.  
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.  
4
Submit Documentation Feedback  
Copyright © 2007–2011, Texas Instruments Incorporated  
Product Folder Link(s): TXS0102  
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)  
VCCB = 2.5 V  
VCC = 3.3 V  
VCC = 5 V  
± 0.2 V  
± 0.3 V  
± 0.5 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
21  
2
22  
2
24  
2
Data rate  
Mbps  
ns  
47  
45  
41  
Pulse  
duration  
tw  
Data inputs  
500  
500  
500  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)  
VCCB = 2.5 V  
VCC = 3.3 V  
VCC = 5 V  
± 0.2 V  
± 0.3 V  
± 0.5 V  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
24  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
20  
2
22  
2
Data rate  
Mbps  
ns  
2
50  
45  
41  
Pulse  
duration  
tw  
Data inputs  
500  
500  
500  
TIMING REQUIREMENTS  
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)  
VCC = 3.3 V  
VCC = 5 V  
± 0.3 V  
± 0.5 V  
UNIT  
MIN  
MAX  
23  
MIN  
MAX  
24  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Data rate  
Mbps  
ns  
2
2
43  
41  
tw  
Pulse duration  
Data inputs  
500  
500  
Copyright © 2007–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TXS0102  
TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)  
VCCB = 2.5 V  
VCCB = 3.3 V  
VCCB = 5 V  
± 0.5 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
± 0.2 V  
± 0.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
2.3  
45  
MAX  
5.3  
MIN  
2.4  
36  
MAX  
5.4  
9.6  
7.1  
208  
4.5  
4.4  
4.5  
140  
200  
40  
MIN  
2.6  
27  
MAX  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
6.8  
tPHL  
tPLH  
tPHL  
tPLH  
8.8  
10  
ns  
A
B
B
A
6.8  
7.5  
260  
4.4  
198  
4.7  
1.9  
45  
5.3  
1.1  
36  
1.2  
27  
4
ns  
5.3  
0.5  
175  
200  
50  
102  
ten  
OE  
OE  
A or B  
A or B  
200  
35  
ns  
ns  
tdis  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
3.2  
38  
4
9.5  
2.3  
30  
9.3  
132  
9.1  
106  
6
2
22  
2.7  
10  
1.7  
4.2  
2.8  
7
7.6  
95  
trA  
trB  
tfA  
A-port rise time  
ns  
ns  
165  
10.8  
145  
5.9  
2.7  
23  
7.6  
58  
B-port rise time  
A-port fall time  
34  
2
1.9  
4.3  
2.8  
7.5  
13.3  
6.1  
16.2  
16.2  
0.7  
4.4  
2.9  
6.9  
6.9  
6.4  
16.2  
16.2  
0.7  
ns  
13.8  
13.8  
0.7  
tfB  
B-port fall time  
tSK(O)  
Channel-to-channel skew  
ns  
Push-pull driving  
21  
2
22  
2
24  
2
Max data rate  
Mbps  
Open-drain driving  
6
Submit Documentation Feedback  
Copyright © 2007–2011, Texas Instruments Incorporated  
Product Folder Link(s): TXS0102  
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)  
VCCB = 2.5 V  
VCCB = 3.3 V  
VCCB = 5 V  
± 0.5 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
± 0.2 V  
± 0.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
1.7  
43  
MAX  
3.2  
6.3  
3.5  
250  
3
MIN  
2
MAX  
3.7  
6
MIN  
2.1  
27  
MAX  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
3.8  
5.8  
4.4  
190  
4.3  
4
tPHL  
tPLH  
tPHL  
tPLH  
A
B
B
A
ns  
4.1  
206  
3.6  
4.2  
1.6  
140  
200  
40  
36  
2.6  
37  
1.8  
44  
4.7  
2.5  
170  
200  
50  
1.2  
27  
ns  
1
103  
200  
35  
ten  
OE  
OE  
A or B  
A or B  
ns  
ns  
tdis  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
2.8  
34  
7.4  
149  
8.3  
151  
5.7  
6.9  
7.8  
8.8  
0.7  
2.6  
28  
6.6  
121  
7.2  
112  
5.5  
6.2  
6.7  
9.4  
0.7  
1.8  
24  
5.6  
89  
trA  
trB  
tfA  
A-port rise time  
ns  
ns  
ns  
3.2  
35  
2.9  
24  
2.4  
12  
6.1  
64  
B-port rise time  
A-port fall time  
1.9  
4.4  
2.2  
5.1  
1.9  
4.3  
2.4  
5.4  
1.8  
4.2  
2.6  
5.4  
5.3  
5.8  
6.6  
10.4  
0.7  
tfB  
B-port fall time  
ns  
ns  
tSK(O)  
Channel-to-channel skew  
Push-pull driving  
20  
2
22  
2
24  
2
Max data rate  
Mbps  
Open-drain driving  
Copyright © 2007–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): TXS0102  
TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)  
VCCB = 3.3 V  
VCCB = 5 V  
± 0.5 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
± 0.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
1.3  
36  
1
MAX  
MIN  
1.4  
28  
1
MAX  
Push-pull driving  
2.4  
4.2  
4.2  
204  
2.5  
124  
2.5  
139  
200  
40  
3.1  
tPHL  
tPLH  
tPHL  
tPLH  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
4.6  
ns  
A
B
B
A
4.4  
165  
3.3  
97  
ns  
2.6  
3
3
105  
ten  
OE  
OE  
A or B  
A or B  
200  
35  
ns  
ns  
tdis  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
Push-pull driving  
Open-drain driving  
2.3  
25  
2.5  
26  
2
5.6  
116  
6.4  
116  
5.4  
6.1  
7.4  
7.6  
0.7  
1.9  
19  
4.8  
85  
trA  
trB  
tfA  
A-port rise time  
ns  
ns  
ns  
2.1  
14  
7.4  
72  
B-port rise time  
A-port fall time  
1.9  
4.2  
2.4  
4.8  
5
4.3  
2.3  
5
5.7  
7.6  
8.3  
0.7  
tfB  
B-port fall time  
ns  
ns  
tSK(O)  
Channel-to-channel skew  
Push-pull driving  
23  
2
24  
2
Max data rate  
Mbps  
Open-drain driving  
8
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Copyright © 2007–2011, Texas Instruments Incorporated  
Product Folder Link(s): TXS0102  
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
PRINCIPLES OF OPERATION  
Applications  
The TXS0102 can be used to bridge the digital-switching compatibility gap between two voltage nodes to  
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point  
topology for interfacing devices or systems operating at different interface voltages with one another. Its primary  
target application use is for interfacing with open-drain drivers on the data I/Os such as I2C or 1-wire, where the  
data is bidirectional and no control signal is available. The TXS0102 can also be used in applications where a  
push-pull driver is connected to the data I/Os, but the TXB0102 might be a better option for such push-pull  
applications.  
Architecture  
The TXS0102 architecture (see Figure 1) is an auto-direction-sensing based translator that does not require a  
direction-control signal to control the direction of data flow from A to B or from B to A.  
VCCA  
VCCB  
One-  
shot  
One-  
shot  
T1  
T2  
R1  
10k  
R2  
10k  
Gate Bias  
A
B
N2  
Figure 1. Architecture of a TXS01xx Cell  
These two bidirectional channels independently determine the direction of data flow without a direction-control  
signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is how this  
auto-direction feature is realized.  
The TXS0102 is part of TI's "Switch" type voltage translator family and employs two key circuits to enable this  
voltage translation:  
1) An N-channel pass-gate transistor topology that ties the A-port to the B-port  
and  
2) Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B  
ports  
For bidirectional voltage translation, pull-up resistors are included on the device for dc current sourcing capability.  
The VGATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above  
the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal.  
The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for  
transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S.  
circuits turn on the PMOS transistors (T1, T2) to increase the current drive capability of the driver for  
approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high  
ac drive by bypassing the internal 10-kΩ pull-up resistors during the low-to-high transition to speed up the signal.  
The output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase. To  
minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn-off  
before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width  
number provided in the Timing Requirements section of this data sheet.  
Copyright © 2007–2011, Texas Instruments Incorporated  
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9
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TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
Input Driver Requirements  
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or  
push-pull) drivers that are interfaced to the TXS0102 I/O pins. Since the high bandwidth of these bidirectional I/O  
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a  
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup  
resistors.  
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving  
TXS0102 data I/Os, as well as the capacitive loading on the data lines.  
Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for  
tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is  
less than 50 Ω.  
Output Load Considerations  
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading  
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough  
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity  
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay  
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends  
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is  
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC  
,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the  
capacitance that the TXS0102 output sees, so it is recommended that this lumped-load capacitance be  
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level  
affects.  
Power Up  
During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power supply will not damage  
the device during the power up operation, so either power supply can be ramped up first.  
Enable and Disable  
The TXS0102 has an OE input that is used to disable the device by setting OE low, which places all I/Os in the  
Hi-Z state. The disable time (tdis) indicates the delay between the time when OE goes low and when the outputs  
are disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the one-shot  
circuitry to become operational after OE is taken high.  
Pullup or Pulldown Resistors on I/O Lines  
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup  
resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O  
to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). Adding lower value pull-up resistors will effect VOL  
levels, however. The internal pull-ups of the TXS0102 are disabled when the OE pin is low.  
10  
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Product Folder Link(s): TXS0102  
TXS0102  
www.ti.com  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
PARAMETER MEASUREMENT INFORMATION  
V
CCI  
V
CCO  
V
CCI  
V
CCO  
DUT  
DUT  
IN  
IN  
OUT  
OUT  
1 MW  
1 MW  
15 pF  
15 pF  
DATA RATE, PULSE DURATION, PROPAGATION DELAY,  
OUTPUT RISE AND FALL TIME MEASUREMENT USING  
AN OPEN-DRAIN DRIVER  
DATA RATE, PULSE DURATION, PROPAGATION DELAY,  
OUTPUT RISE AND FALL TIME MEASUREMENT USING  
A PUSH-PULL DRIVER  
2 × V  
CCO  
S1  
50 kW  
Open  
From Output  
Under Test  
15 pF  
50 kW  
TEST  
/t  
S1  
2 × V  
t
PZL PLZ  
CCO  
LOAD CIRCUIT FOR ENABLE/DISABLE  
TIME MEASUREMENT  
t
/t  
Open  
PHZ PZH  
t
w
V
CCI  
V
CCA  
V
/2  
V
/2  
Output  
Control  
(low-level  
enabling)  
Input  
CCI  
CCI  
V /2  
CCA  
V /2  
CCA  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
0 V  
t
PLZ  
t
PZL  
V
V
CCO  
Output  
Waveform 1  
V
CCI  
V
V
/2  
CCO  
Input  
V
/2  
/2  
V
/2  
CCI  
CCI  
0.1 y V  
CCO  
S1 at 2 × V  
CCO  
OL  
0 V  
(see Note B)  
t
PHZ  
t
t
t
PLH  
PHL  
PZH  
Output  
Waveform 2  
S1 at GND  
V
OH  
0.9 y V  
V
OH  
CCO  
0.9 y V  
CCO  
/2  
Output  
V
CCO  
V
CCO  
/2  
CCO  
(see Note B)  
0.1 y V  
CCO  
0 V  
V
OL  
t
f
t
r
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
A.  
C
L
includes probe and jig capacitance.  
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
H.  
I.  
t
t
t
V
V
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
pd  
PHL  
is the V associated with the input port.  
CC  
CCI  
is the V associated with the output port.  
CCO  
CC  
J. All parameters and waveforms are not applicable to all devices.  
Figure 2. Load Circuit and Voltage Waveforms  
Copyright © 2007–2011, Texas Instruments Incorporated  
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TXS0102  
SCES640D –JANUARY 2007–REVISED MARCH 2011  
www.ti.com  
REVISION HISTORY  
Changes from Revision C (May 2009) to Revision D  
Page  
•
Added TOP-SIDE MARKING for SON - DQE and SON - DQM Packages in the ORDERING INFORMATION table. ....... 2  
12  
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Copyright © 2007–2011, Texas Instruments Incorporated  
Product Folder Link(s): TXS0102  
D: Max = 1.918 mm, Min = 1.858 mm  
E: Max = 0.918 mm, Min = 0.858 mm  
PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Feb-2014  
PACKAGING INFORMATION  
Orderable Device  
TXS0102DCTR  
TXS0102DCTRE4  
TXS0102DCTT  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
ACTIVE  
SM8  
SM8  
DCT  
8
8
8
8
8
8
8
8
8
8
8
8
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
NFE  
Z
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DCT  
DCT  
DCT  
DCT  
DCU  
DCU  
DCU  
DCU  
DQE  
DQM  
YZP  
3000  
250  
Green (RoHS  
& no Sb/Br)  
NFE  
Z
SM8  
Green (RoHS  
& no Sb/Br)  
NFE  
Z
TXS0102DCTTE4  
TXS0102DCTTG4  
TXS0102DCUR  
TXS0102DCURG4  
TXS0102DCUT  
TXS0102DCUTG4  
TXS0102DQER  
TXS0102DQMR  
TXS0102YZPR  
SM8  
250  
Green (RoHS  
& no Sb/Br)  
NFE  
Z
SM8  
250  
Green (RoHS  
& no Sb/Br)  
NFE  
Z
US8  
3000  
3000  
250  
Green (RoHS CU NIPDAU | CU SN  
& no Sb/Br)  
(FE ~ NFEQ ~ NFER)  
NZ  
US8  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
NFER  
US8  
Green (RoHS CU NIPDAU | CU SN  
& no Sb/Br)  
(FE ~ NFEQ ~ NFER)  
NZ  
US8  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAUAG  
CU NIPDAU  
SNAGCU  
NFER  
X2SON  
X2SON  
DSBGA  
5000  
3000  
3000  
Green (RoHS  
& no Sb/Br)  
2H  
Green (RoHS  
& no Sb/Br)  
(2H7 ~ 2HR)  
(2H ~ 2H7 ~ 2HN)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Feb-2014  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Jun-2014  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TXS0102DCUR  
TXS0102DCUR  
TXS0102DCURG4  
TXS0102DCUTG4  
TXS0102DQER  
TXS0102DQMR  
TXS0102DQMR  
TXS0102YZPR  
TXS0102YZPR  
US8  
US8  
DCU  
DCU  
DCU  
DCU  
DQE  
DQM  
DQM  
YZP  
8
8
8
8
8
8
8
8
8
3000  
3000  
3000  
250  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
178.0  
180.0  
8.4  
9.0  
8.4  
8.4  
8.4  
8.4  
9.5  
9.2  
8.4  
2.25  
2.05  
2.25  
2.25  
1.2  
3.35  
3.3  
1.05  
1.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q3  
Q1  
Q1  
Q1  
Q1  
Q1  
US8  
3.35  
3.35  
1.6  
1.05  
1.05  
0.55  
0.59  
0.5  
US8  
X2SON  
X2SON  
X2SON  
DSBGA  
DSBGA  
5000  
3000  
3000  
3000  
3000  
1.57  
1.4  
2.21  
2.0  
1.02  
1.02  
2.02  
2.02  
0.63  
0.63  
YZP  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Jun-2014  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TXS0102DCUR  
TXS0102DCUR  
TXS0102DCURG4  
TXS0102DCUTG4  
TXS0102DQER  
TXS0102DQMR  
TXS0102DQMR  
TXS0102YZPR  
TXS0102YZPR  
US8  
US8  
DCU  
DCU  
DCU  
DCU  
DQE  
DQM  
DQM  
YZP  
8
8
8
8
8
8
8
8
8
3000  
3000  
3000  
250  
202.0  
182.0  
202.0  
202.0  
202.0  
202.0  
184.0  
220.0  
182.0  
201.0  
182.0  
201.0  
201.0  
201.0  
201.0  
184.0  
220.0  
182.0  
28.0  
20.0  
28.0  
28.0  
28.0  
28.0  
19.0  
35.0  
17.0  
US8  
US8  
X2SON  
X2SON  
X2SON  
DSBGA  
DSBGA  
5000  
3000  
3000  
3000  
3000  
YZP  
Pack Materials-Page 2  
MECHANICAL DATA  
MPDS049B – MAY 1999 – REVISED OCTOBER 2002  
DCT (R-PDSO-G8)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,30  
0,15  
M
0,13  
0,65  
8
5
0,15 NOM  
2,90  
2,70  
4,25  
3,75  
Gage Plane  
PIN 1  
INDEX AREA  
0,25  
1
4
0° – 8°  
0,60  
0,20  
3,15  
2,75  
1,30 MAX  
Seating Plane  
0,10  
0,10  
0,00  
4188781/C 09/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion  
D. Falls within JEDEC MO-187 variation DA.  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
D: Max = 1.918 mm, Min =1.858 mm  
E: Max = 0.918 mm, Min =0.858 mm  
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