IXI848A
IXYS
Pin Description and Configuration
SOIC Name Description
Ground
Connecting R10 to GND, (R50=N/C) selects a VOUT voltage that is 10X the voltage across
RSENSE
Output voltage proportional to the voltage across RSENSE
1
2
GND
R10
.
.
3
4
5
6
7
VOUT
IN
Positive supply terminal and power connection for the external Sense Resistor.
Load-side connection to the external Sense Resistor.
LOAD
N/C
No Connect
No Connect
N/C
Connecting R50 to GND, (R10=N/C) selects a VOUT voltage that is 50X the voltage across
8
R50
RSENSE
.
Detailed Circuit Description
The IXI848A is a precision high side current sense
monitor featuring an input voltage range of 2.7V to
60V, and a selectable ground referenced fixed
gain output of either 10 or 50.
the error component associated with the input
offset voltage of the internal op amp.
The IXI848A can be configured to measure a wide
selection of currents by using different RSENSE
values. Some common values for typical operation
of the IXI848A are listed in the following table.
A small voltage developed across an external
sense resistor (RS), is converted to an amplified
ground referenced voltage output at VOUT,
(Figure 1). The amplifier’s non-inverting input is
high impedance making the voltage at that
terminal equal to VIN – (IL) (RS). The amplifier
forces the high impedance inverting terminal to
equal the non-inverting input voltage by turning on
the P-Channel MOS FET.
Full-Scale RSENSE
Gain
(V/V)
10
10
50
VOUT (V)
VSENSE = 150mV
IL (A)
0.15
1.5
RS (Ω)
1.0
0.1
1.5
1.5
2.5
5
5
100
0.01
0.001
50
As the P-Channel MOS FET is biased on by the
amplifier output, current is sourced through RG
(10R or 10R+40R), to produce a voltage equal to
VIN – (IL) (RS) at the inverting input of the amplifier.
This develops a voltage across the inverting input
resistor, R that matches the sense voltage across
RS, plus any associated input offset voltage, (VIO).
Consequently, the voltage at VOUT corresponds
to RG / R.
Output Impedance
The VOUT output is a current source driving a
33kꢀ resistance to ground for a gain of 10, or a
165kꢀ resistance to ground for a gain of 50.
Output gain is reduced by resistive loading of the
VOUT terminal. The impedance of the external
monitor load (ZM) should be chosen high enough
to maintain the desired accuracy. Buffering of the
VOUT terminal with a high-impedance input stage
may be required to minimize output errors.
Output: VOUT = G [ (IL) (RS) + VIO ]
Gain: G = (RG) (ZM) / R (RG (RG + ZM))
RG = 10R or 50R selectable
The following formulas quantify the percent error
introduced by output loading:
For a Gain of 10
Temperature coefficient:
%ERROR = 100 [RLOAD / (33kꢀ + RLOAD) – 1]
(all on-chip resistors) R = 700ppm / °C typical
For a Gain of 50
RSENSE Component Selection
%ERROR = 100 [RLOAD / (165kꢀ + RLOAD) – 1]
The RSENSE value should be selected such that the
voltage across RSENSE is at full-scale for the load
current to be monitored. Operating the IXI848A at
or near the full-scale sense voltage will minimize
RLOAD = the external load applied to VOUT
www.ixys.com
3
08/01/05
