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PX3515BDDGR4XTMA1

型号：

PX3515BDDGR4XTMA1

品牌：

INFINEON[ Infineon ]

页数：

7 页

PDF大小：

184 K

下载PDF手册
An Infineon Technologies Company  
PX3515  
Sychronous Rectified Buck MOSFET Driver IC  
Datasheet  
Applications  
Description  
®
®
The PX3515 is a dual high speed driver designed to drive a  
wide range of high-side and low-side power N-channel  
MOSFETs in synchronous rectified buck converters. When  
combined with the Primarion PX35XX family of Digital Multi-  
phase Controllers or PX75XX Digital Point of Load (Di-  
POLTM) Controllers and N-channel MOSFETs, the PX3515  
•
Core power regulation for Intel and AMD  
μprocessors  
•
•
High current DC-DC converters  
POL power converters for memory, DSP, FPGA, ASIC  
forms  
a complete core-voltage regulator solution for  
advanced micro and graphics processors as well as point-  
of-load applications.  
Features  
The PX3515 provides the capability of driving the high-side  
gate and low-side gate with independent drive voltages  
over a range from 7V to 12V (high-side VCC) and 5V to  
12V (low-side PVCC). This provides the flexibility necessary  
to optimize applications involving trade-offs between gate  
charge and conduction losses.  
•
Dual MOSFET driver for synchronous rectified bridge  
converters  
•
Adjustable high-side and low-side MOSFET gate drive  
voltages for optimal efficiency  
-
-
High-side VCC (7V to 12V)  
Low-side PVCC (5V to 12V)  
Adaptive zero shoot-through protection is integrated into the  
IC which prevents both upper and lower MOSFETs from  
conducting simultaneously and to minimize dead time. The  
PX3515 has small propagation delay from input to output  
with fast rise and fall times.  
•
•
•
Integrated bootstrap diode for reduced part count  
Adaptive gate drive control prevents cross-conduction  
Fast rise and fall times supports switching rates of up  
to 2MHz  
The PX3515 drivers also feature a three-state PWM input  
which, when used together with Primarion’s Digital  
Controllers, eliminates the need for Schottky diodes that are  
often used in systems to protect the load from reversed  
output voltage events.  
•
Capable of sinking more than 4A peak current for low  
switching losses  
•
•
•
Three-state PWM input for output stage shutdown  
VCC under-voltage protection  
Lead-free (RoHS compliant) SOIC and DFN packages  
PX3515 DFN Package  
10-pin DFN (TOP VIEW)  
1
10  
UGATE  
BOOT  
N/C  
PHASE  
PVCC  
N/C  
Ordering Information  
2
3
4
5
9
8
7
6
Part Number  
Ambient  
Package  
GND  
PWM  
GND  
VCC  
PX3515BDDG  
10-lead DFN  
0 to 85°C  
LGATE  
.
PD-3515-001A  
Copyright © 2008, Primarion, Inc.  
Contents subject to change without notice  
26-Aug-08  
PX3515  
Functional Block Diagram  
Figure 1. Block Diagram  
Typical Application  
+12V  
VDRIVE  
+5V  
1
63.4K  
SDA  
VINSEN  
VCC  
1000pF  
SCL  
SMBus I/F  
1
F
5K  
10K  
SMBALERT_N  
GND  
PX7510  
1
F
F
VD25  
0.1  
0.1  
F
PWRGD  
OUTEN  
Power  
Management I/F  
VCC  
UGATE  
1
F
5K  
VD33  
PWM  
F
PVCC  
PHASE  
BOOT  
VOUT  
L
FAULT1  
FAULT2  
Fault  
1
F
PX3515  
1
Outputs  
Cb  
Rc  
PWM  
GND  
Rb  
LGATE  
SADDR_L  
SADDR_M  
BAV99  
5K  
422  
COUT  
TEMPSEN  
Rn  
ISENN  
ISENP  
VSENP  
VSET  
REXT  
FSET  
Rp  
VTRIM  
IMAXSET  
CEXT  
R0  
VSENN  
RTN  
optional  
Figure 2. Single-Phase Application with PX7510 DiPOL Controller  
PD-3515-001A  
2
PX3515  
Absolute Maximum Ratings  
Stresses above those listed in Table 1 “Absolute Maximum Ratings” may cause permanent damage to the device. These are  
absolute stress ratings only and operation of the device is not implied at these or any other conditions in excess of those given  
in the operational sections of this specification.  
Table 1. Absolute Maximum Ratings1  
Symbol  
VVCC  
Description  
VCC supply voltage (DC)  
PVCC supply voltage (DC)  
BOOT voltage  
Min  
-0.3  
-0.3  
-0.3  
-0.3  
-1  
Max  
25  
Units  
Conditions  
V
V
V
V
V
VPVCC  
VBOOT  
25  
45  
Referenced to GND  
VBOOT - VPHASE BOOT to PHASE voltage  
25  
Referenced to PHASE  
VPHASE  
PHASE voltage, DC  
25  
DC  
VPHASE  
VPWM  
PHASE voltage, pulsed  
Input voltage  
-20  
-0.3  
30  
V
V
Pulsed (500ns, 2% max duty cycle)  
6.3  
UGATE  
VPHASE – 0.3  
-0.3  
VBOOT + 0.3  
VPVCC + 0.3  
V
LGATE  
V
ESD, Human Body Model  
ESD, Charged Device Model  
ESD, Machine Model  
Junction temperature  
Storage temperature  
4000  
1000  
300  
V
JEDEC JESD22-A114-E  
JEDEC JESD22-C101-C  
JEDEC JESD22-A115-A  
V
V
TJ  
-25  
150  
150  
°C  
°C  
TSTG  
-55  
Notes:  
1. At TJ = 25°C, unless otherwise specified  
Recommended Operating Conditions  
Table 2. Recommended Operating Conditions  
Symbol  
VVCC  
VPVCC  
fPWM  
Description  
Min  
+7.0  
+4.5  
0.1  
0
Nom  
Max  
+13.2  
+13.2  
2
Units  
V
VCC supply voltage  
+12.0  
+12.0  
PVCC supply voltage  
V
PWM signal transition frequency  
Junction temperature  
MHz  
°C  
TJ  
125  
85  
TAMBIENT  
θJA(0)  
θJC  
Operating ambient temperature  
Thermal resistance, junction-to-air, note 2  
Thermal resistance, junction-to-case, note 3  
0
°C  
48  
7
°C/W  
°C/W  
Notes:  
2.  
θJA is measured with the component mounted on a high effective thermal conductivity test board in free air  
For θJC, the case temperature location is the center of the exposed metal pad on the underside of the package  
3.  
PD-3515-001A  
3
PX3515  
Electrical Characteristics  
Operating conditions: VCC = +12.0V, PVCC = +12.0V, TA = 25°C, unless otherwise specified.  
Table 3. Electrical Characteristics  
Parameter  
Conditions  
Symbol  
Min  
Typ  
Max  
Units  
Supply Characteristics  
VCC supply current  
PVCC supply current  
Quiescent current  
VCC rising threshold  
VCC falling threshold  
VCC hysteresis  
fPWM = 1MHz, no load  
fPWM = 1MHz, no load  
IVCC  
IPVCC  
6
mA  
mA  
mA  
V
5.5  
1.9  
6.2  
5.6  
650  
IPVCCQ+IVCCQ  
1.4
≤
V
PWM
≤
2.2  
dv/dt < 2.5 kV/s  
6.7  
4.8  
V
400  
950  
mV  
PWM Input  
Input current  
VPWM = +3.3V  
VPWM = 0V  
IPWM_H  
IPWM_L  
450  
-530  
3.5  
μA  
μA  
kΩ  
V
Sink/source impedance  
Shutdown window (3-state)  
PWM open threshold  
RPWM  
minimum pulse of 25ns  
VPWM_SD  
VPWM_O  
VPWM_H  
VPWM_L  
SRPWM  
tmin_PWM  
1.4  
1.6  
2.6  
2.2  
2.0  
1.8  
V
PWM rising threshold  
V
PWM falling threshold  
PWM input slew rate  
1.0  
V
5
V/µs  
ns  
Minimum pulse width high side  
pulse width on PWM  
40  
Upper Gate (UGATE) Output  
Shutdown hold off time  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
tPDTS_UG  
tr_UG  
25  
20  
15  
25  
25  
25  
40  
45  
ns  
ns  
ns  
ns  
ns  
ns  
UGATE rise time  
UGATE fall time  
tf_UG  
3-state rising propagation delay  
UGATE turn-on propagation delay  
UGATE turn-off propagation delay  
tTSSHD_UG  
tD(ON)_UG  
tD(OFF)_UG  
Lower Gate (LGATE) Output  
Shutdown hold-off time  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
Note 4, 3nF load  
tPDTS_LG  
tr_LG  
20  
20  
15  
20  
20  
20  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
LGATE rise time  
LGATE fall time  
tf_LG  
3-state rising propagation delay  
LGATE turn-on propagation delay  
LGATE turn-off propagation delay  
tTSSHD_LG  
tD(ON)_LG  
tD(OFF)_LG  
Output Characteristics (note 3)  
Upper drive source current  
Upper drive source impedance  
Upper drive sink current  
current pulse < 20ns  
Note 5, ISRC_UG = 2A  
current pulse < 20ns  
ISRC_UG  
RSRC_UG  
ISNK_UG  
RSNK_UG  
ISRC_LG  
RSRC_LG  
ISNK_LG  
4
4
4
A
Ω
A
Ω
A
Ω
A
Ω
1
Upper drive sink impedance  
Lower drive source current  
Lower drive source impedance  
Lower drive sink current  
0.9  
1.4  
0.9  
1.3  
1.3  
current pulse < 40ns  
Note 6, ISRC_UG = 2A  
current pulse < 40ns  
4
-
Lower drive sink impedance  
RSNK_LG  
PD-3515-001A  
4
PX3515  
Notes:  
4. Guaranteed by design, verified during characterization  
5. Incremental resistance VBOOT – VUG = 4.3V @ ISRC = 2A  
6. Incremental resistance VVCC – VBG = 4.4V @ ISRC = 2A  
Table 4. Pin Function Description  
Description  
UGATE Upper gate drive output. Connect to the gate of high-side power N-channel MOSFET  
Pin # Name  
1
2
3
4
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin  
and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the  
Internal Bootstrap Device section herein for guidance in choosing the capacitor value.  
BOOT  
N/C  
No connection  
The PWM signal is the control input for the driver and is to be connected to the PWM output of the  
controller. The PWM signal can enter three distinct states during operation. See the 3-state PWM input  
section herein for further details.  
PWM  
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of  
the driver.  
5
6
7
8
9
GND  
LGATE Lower gate drive output. Connect to the gate of the low-side power N-channel MOSFET  
This pin supplies power to the upper gate , Its operating range is +6V to +12V. Place a high quality low  
ESR ceramic capacitor from this pin to GND.  
VCC  
N/C  
No connection  
This pin supplies power to the lower gate , Its operating range is +6.7V to +12V. Place a high quality low  
ESR ceramic capacitor from this pin to GND.  
PVCC  
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides  
a return path for the upper gate drive.  
10 PHASE  
Die paddle  
Connect pad to the power circuit board power ground plane (GND), use thermal vias  
Timing Diagram  
1.4V< PWM <2.2V  
PWM  
tD(OFF)_LG  
tD(OFF)_UG  
tPDTS_UG  
tSSHD_UG  
UGATE  
tr_UG  
tD(ON)_UG  
tf_LG  
tf_HS  
tSSHD_LG  
tPDTS_LG  
tD(ON)_LS  
LGATE  
PHASE  
tr_LG  
PD-3515-001A  
5
PX3515  
MOSFET should be as close as thermally allowable.  
Layout Considerations  
•
Minimize the current loop of the output and input power  
trains. Short the source connection of the lower  
MOSFET to ground as close to the transistor pin as  
feasible. Input capacitors (especially ceramic  
decoupling) should be placed as close to the drain of  
upper and source of lower MOSFETs as possible.  
The parasitic inductances of the PCB and of the power  
devices’ packaging (both upper and lower MOSFETs) can  
cause serious ringing, exceeding absolute maximum  
rating of the devices. Careful layout can help minimize  
such unwanted stress. The following advice is meant to  
lead to an optimized layout:  
•
Keep decoupling loops (PVCC-GND and BOOT-  
PHASE) as short as possible.  
To optimize heat spreading, copper should be placed  
directly underneath the IC whether it has an exposed pad  
or not. The copper area can be extended beyond the  
bottom area of the IC and/or connected to buried copper  
plane(s) with thermal vias. This combination of vias for  
vertical heat escape, extended copper plane, and buried  
planes for heat spreading allows the IC to achieve its full  
thermal potential  
•
Minimize trace inductance, especially on low-  
impedance lines. All power traces (UGATE, PHASE,  
LGATE, GND, PVCC) should be short and wide, as  
much as possible.  
•
Minimize the inductance of the PHASE node. Ideally,  
the source of the upper and the drain of the lower  
Physical Characteristics (10-lead 3mm x 3mm DFN package)  
0.90  
±0.05  
Min 0.00  
Max 0.05  
3.00±0.10  
0.35±0.10  
2.30  
Pin #1 Corner  
0.50  
3.00  
±0.10  
2.00  
0.50  
0.23  
0.42  
0.20  
0.70  
1.60  
0.35  
TOP VIEW  
SIDE VIEW  
BOTTOM VIEW  
Figure 3. Physical dimensions.  
Suggested land pattern  
PD-3515-001A  
6
PX3515  
Ordering Information  
P X 3 5 1 5 B D D G - R 4  
Prefix  
Part Number  
Quantity per Carrier  
4 digits  
4: 4000  
Carrier Type  
R: Tape-and-Reel  
Version Control  
Temperature Range  
D: 0°C to +85°C  
Pb-free Option  
G: green (lead-free)  
Package Designator  
D: DFN  
Printed in the USA/1002/PDF/TK/PS  
This document contains characteristic data and other specifications that are subject to change without notice. Customers are advised to confirm information in this datasheet  
prior to using the information herein or placing an order. Primarion does not assume any liability arising from the application or use of any product or circuit described herein,  
neither does it convey any license under its patents or any other rights. Primarion products are not designed, intended, or authorized, or warranted to be suitable for use in life-  
support applications, devices or systems or other critical applications.  
©2008, Primarion, Inc. Primarion is a registered trademark of Primarion, Inc. The Primarion logos are trademarks of Primarion, Inc. *Other names and brands are the property  
of their respective owners.  
2780 Skypark Drive, Suite 100, Torrance, CA 90505 1-310-602-5500 Fax 1-310-602-5559  
PD-3515-001A  
7
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