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8R43002A-01PGGI8

型号：

8R43002A-01PGGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

15 页

PDF大小：

204 K

下载PDF手册
FemtoClock® Crystal - to - 3.3 V, 2.5  
LVPECL Frequencey Synthesizer  
IDT8R43002I-01  
DATA SHEET  
GENERAL DESCRIPTION  
FEATURES  
• Two 3.3V or 2.5V LVPECL outputs  
The IDT8R43002I-01 is  
a two output LVPECL  
synthesizer optimized to generate Ethernet reference  
clock frequencies. Using a 25MHz 18pF parallel  
resonant crystal, the following frequencies can be  
generated based on the two frequency select pins  
(F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The  
IDT8R43002I-01 uses IDT’s FemtoClock® low phase  
noise VCO technology and can achieve 1ps or lower  
typical RMS phase jitter, easily meeting Ethernet jitter  
requirements. The IDT8R43002I-01 is packaged in a  
small 20-pin TSSOP package.  
• Selectable crystal oscillator interface  
or LVCMOS/LVTTL single-ended input  
• Supports the following output frequencies:  
156.25MHz, 125MHz and 62.5MHz  
• VCO range: 560MHz - 680MHz  
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal  
(1.875MHz-20MHz): 0.55ps (typical)  
• Output skew: 30ps (maximum)  
• Supply Voltage Modes  
Core/Outputs  
3.3/3.3  
2.5/2.5  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free RoHS-compliant packages  
TABLE 1. FREQUENCY SELECT FUNCTION TABLE  
Inputs  
PIN ASSIGNMENT  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
nc  
VCCO  
Q0  
VCCO  
Output Frequency  
Q1  
nQ1  
VEE  
VCC  
nXTAL_SEL  
REF_CLK  
XTAL_IN  
XTAL_OUT  
F_SEL1  
M Divider N Divider  
(25MHz Ref.)  
F_SEL1 F_SEL0  
Value  
Value  
nQ0  
MR  
nPLL_SEL  
nc  
0
0
1
1
0
1
0
1
25  
4
156.25 (default)  
25  
25  
25  
5
10  
5
125  
62.5  
125  
VCCA  
F_SEL0  
VCC  
IDT8R43002I-01  
20-Lead TSSOP  
6.5mm x 4.4mm x 0.92mm  
BLOCK DIAGRAM  
package body  
2
F_SEL[1:0]  
G Package  
Top View  
Q0  
nPLL_SEL  
F_SEL[1:0]  
nQ0  
0 0 ÷4 (default)  
0 1 ÷5  
1 0 ÷10  
REF_CLK  
1
0
1 1 ÷5  
1
Q1  
nQ1  
VCO  
XTAL_IN  
Phase  
Detector  
OSC  
625MHz  
0
(w/25MHz  
Reference)  
XTAL_OUT  
nXTAL_SEL  
M = 25 (fixed)  
MR  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
1
©2012Integrated DeviceTechnology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
TABLE 2. PIN DESCRIPTIONS  
Number  
1, 7  
Name  
nc  
Type  
Unused  
Description  
No connect.  
2, 20  
3, 4  
VCCO  
Power  
Ouput  
Output supply pins.  
Q0, nQ0  
Differential output pair. LVPECL interface levels.  
Active HIGH Master Reset. When logic HIGH, the internal dividers are  
reset causing the true outputs Qx to go low and the inverted outputs nQx  
to go high. When logic LOW, the internal dividers and the outputs are  
enabled. LVCMOS/LVTTL interface levels.  
Determines whether synthesizer is in PLL or bypass mode.  
LVCMOS/LVTTL interface levels.  
5
MR  
Input  
Pulldown  
Pulldown  
6
nPLL_SEL  
VCCA  
Input  
Power  
Input  
8
Analog supply pin.  
F_SEL0,  
F_SEL1  
9, 11  
10, 16  
12, 13  
14  
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.  
VCC  
Power  
Input  
Core supply pin.  
XTAL_OUT,  
XTAL_IN  
Parallel resonant crystal interface. XTAL_OUT is the output,  
XTAL_IN is the input.  
REF_CLK  
Input  
Pulldown LVCMOS/LVTTL reference clock input.  
Selects between crystal or REF_CLK inputs as the the PLL Reference  
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.  
LVCMOS/LVTTL interface levels.  
15  
nXTAL_SEL  
Input  
17  
VEE  
Power  
Output  
Negative supply pins.  
18, 19  
nQ1, Q1  
Differential output pair. LVPECL interface levels.  
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 3. PIN CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
CIN  
Input Capacitance  
4
pF  
RPULLDOWN Input Pulldown Resistor  
51  
kΩ  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
2
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device. These ratings are stress specifications only. Func-  
tional operation of product at these conditions or any condi-  
tions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maxi-  
mum rating conditions for extended periods may affect prod-  
uct reliability.  
CC  
Inputs, V  
-0.5V to VCC + 0.5V  
I
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)  
Storage Temperature, T -65°C to 150°C  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA= VCCO = 3.3V±10%, TA = -40°C TO 85°C  
Symbol Parameter Test Conditions Minimum Typical  
Maximum Units  
VCC  
VCCA  
VCCO  
IEE  
Core Supply Voltage  
2.97  
2.97  
2.97  
3.3  
3.3  
3.3  
3.63  
3.63  
3.63  
130  
13  
V
V
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
V
mA  
mA  
ICCA  
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA= VCCO = 2.5V±5%, TA = -40°C TO 85°C  
Symbol Parameter Test Conditions Minimum Typical  
Maximum Units  
VCC  
VCCA  
VCCO  
IEE  
Core Supply Voltage  
2.375  
2.375  
2.375  
2.5  
2.5  
2.5  
2.625  
2.625  
2.625  
115  
V
V
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
V
mA  
mA  
ICCA  
12  
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA= VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
VCC = 3.3V  
Minimum Typical Maximum Units  
2
VCC + 0.3  
VCC + 0.3  
0.8  
V
V
V
V
VIH  
VIL  
IIH  
Input High Voltage  
Input Low Voltage  
VCC = 2.5V  
1.7  
-0.3  
-0.3  
VCC = 3.3V  
VCC = 2.5V  
0.7  
Input  
REF_CLK, MR,  
VCC = VIN = 3.63V or 2.625V  
150  
μA  
μA  
High Current nPLL_SEL, nXTAL_SEL  
Input  
REF_CLK, MR,  
IIL  
V
CC = VIN = 3.63V or 2.625V  
-5  
Low Current nPLL_SEL, nXTAL_SEL  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
3
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA= VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C  
Symbol Parameter Test Conditions Minimum Typical Maximum Units  
VOH  
Output High Voltage; NOTE 1  
VCCO - 1.4  
VCCO - 2.0  
0.6  
VCCO - 0.9  
VCCO - 1.7  
1.0  
V
V
V
VOL  
Output Low Voltage; NOTE 1  
VSWING  
Peak-to-Peak Output Voltage Swing  
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.  
TABLE 5. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Mode of Oscillation  
Frequency  
Fundamental  
22.4  
25  
27.2  
50  
7
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
Drive Level  
pF  
1
mW  
NOTE: Characterized using an 18pF parallel resonant crystal.  
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
F_SEL[1:0] = 00  
F_SEL[1:0] = 01  
F_SEL[1:0] = 10  
Minimum Typical Maximum Units  
140  
112  
56  
170  
136  
68  
MHz  
MHz  
MHz  
ps  
fOUT  
Output Frequency  
tsk(o)  
tjit(Ø)  
Output Skew; NOTE 1, 2  
30  
156.25MHz, (1.875MHz - 20MHz)  
125MHz, (1.875MHz - 20MHz)  
62.5MHz, (1.875MHz - 20MHz)  
20% to 80%  
0.55  
0.60  
0.70  
ps  
RMS Phase Jitter; NOTE 2, 3  
ps  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
350  
48  
650  
52  
ps  
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.  
Measured at the output differential cross points.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 3: Measured using crystal input.  
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
F_SEL[1:0] = 00  
F_SEL[1:0] = 01  
F_SEL[1:0] = 10  
Minimum Typical Maximum Units  
140  
112  
56  
170  
136  
68  
MHz  
MHz  
MHz  
ps  
fOUT  
Output Frequency  
tsk(o)  
tjit(Ø)  
Output Skew; NOTE 1, 2  
30  
156.25MHz, (1.875MHz - 20MHz)  
125MHz, (1.875MHz - 20MHz)  
62.5MHz, (1.875MHz - 20MHz)  
20% to 80%  
0.55  
0.60  
0.74  
ps  
RMS Phase Jitter; NOTE 2, 3  
ps  
ps  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
350  
48  
650  
52  
ps  
%
For Notes, see Table 5A above.  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
4
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V  
10 Gigabit Ethernet Filter  
156.25MHz  
RMS Phase Noise Jitter  
1.875MHz to 20MHz = 0.55ps (typical)  
Raw Phase Noise Data  
Phase Noise Result by adding  
10 Gigabit Ethernet Filter to raw data  
OFFSET FREQUENCY (HZ)  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
5
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
PARAMETER MEASUREMENT INFORMATION  
2V  
2V  
SCOPE  
SCOPE  
Qx  
VCC  
,
Qx  
VCC  
VCCA, VCCO  
,
VCCA, VCCO  
LVPECL  
LVPECL  
nQx  
nQx  
VEE  
VEE  
-1.3V ± 0.33V  
-0.5V ± 0.125V  
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT  
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT  
nQ0, nQ1  
nQx  
Qx  
Q0,Q1  
tPW  
tPERIOD  
nQy  
tPW  
Qy  
odc =  
x 100%  
tPERIOD  
tsk(o)  
OUTPUT SKEW  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
Phase Noise Plot  
80%  
80%  
tR  
Phase Noise Mask  
VSWING  
20%  
20%  
tF  
Offset Frequency  
f1  
f2  
RMS Jitter = Area Under the Masked Phase Noise Plot  
RMS PHASE JITTER  
OUTPUT RISE/FALL TIME  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
6
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
APPLICATIONS INFORMATION  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
OUTPUTS:  
LVPECL OUTPUT  
INPUTS:  
CRYSTAL INPUT:  
All unused LVPECL outputs can be left floating. We  
recommend that there is no trace attached. Both sides of  
the differential output pair should either be left floating or  
terminated.  
For applications not requiring the use of the crystal oscillator  
input, both XTAL_IN and XTAL_OUT can be left floating.  
Though not required, but for additional protection, a 1kΩ  
resistor can be tied from XTAL_IN to ground.  
REF_CLK INPUT:  
For applications not requiring the use of the reference clock,  
it can be left floating. Though not required, but for additional  
protection, a 1kΩ resistor can be tied from the REF_CLK to  
ground.  
LVCMOS CONTROL PINS:  
All control pins have internal pull-ups or pull-downs; additional  
resistance is not required but can be added for additional  
protection. A 1kΩ resistor can be used.  
TERMINATION FOR 3.3V LVPECL OUTPUT  
The clock layout topology shown below is a typical ter-  
mination for LVPECL outputs. The two different layouts  
mentioned are recommended only as guidelines.  
ality. These outputs are designed to drive 50Ω trans-  
mission lines. Matched impedance techniques should  
be used to maximize operating frequency and minimize  
signal distortion. Figures 1A and1B show two different  
layouts which are recommended only as guidelines.  
Other suitable clock layouts may exist and it would be  
recommended that the board designers simulate to  
guarantee compatibility across all printed circuit and  
clock component process variations.  
The differential output is a low impedance follower out-  
puts that generate ECL/LVPECL compatible outputs.  
Therefore, terminating resistors (DC current path to  
ground) or current sources must be used for function-  
3.3V  
Z
o = 50Ω  
125Ω  
125Ω  
FOUT  
FIN  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
FOUT  
FIN  
50Ω  
50Ω  
VCC - 2V  
1
RTT =  
Zo  
RTT  
84Ω  
84Ω  
((VOH + VOL) / (VCC – 2)) – 2  
FIGURE 1A. LVPECL OUTPUT TERMINATION  
FIGURE 1B. LVPECL OUTPUT TERMINATION  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
7
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
TERMINATION FOR 2.5V LVPECL OUTPUT  
close to ground level. The R3 in Figure 2B can be eliminated  
and the termination is shown in Figure 2C.  
Figure 2A and Figure 2B show examples of termination for  
2.5V LVPECL driver. These terminations are equivalent to  
terminating 50Ω to V - 2V. For V = 2.5V, the V - 2V is very  
CCO  
CCO  
CCO  
2.5V  
2.5V  
2.5V  
VCCO=2.5V  
VCCO=2.5V  
R1  
R3  
250  
250  
Zo = 50 Ohm  
Zo = 50 Ohm  
Zo = 50 Ohm  
+
+
-
Zo = 50 Ohm  
-
2,5V LVPECL  
Driver  
2,5V LVPECL  
Driv er  
R1  
50  
R2  
50  
R2  
62.5  
R4  
62.5  
R3  
18  
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE  
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE  
2.5V  
VCCO=2.5V  
Zo = 50 Ohm  
+
Zo = 50 Ohm  
-
2,5V LVPECL  
Driver  
R1  
50  
R2  
50  
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
8
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
APPLICATION SCHEMATIC EXAMPLE  
impedance to the transmission line driving REF_CLK. Load  
caps C7 and C8 are required for frequency accuracy, but  
these may be adjusted for different board layouts. If different  
crystal types are used, please consult IDT for  
recommendations.  
Figure 3 shows an example IDT8R43002I-01 application  
schematic. Input and output terminations shown are intended  
as examples only and may not represent the exact user  
configuration. Resistor R10 represents an external padding  
resistor so that the LVCMOS driver presents a 50 ohm source  
3.3V  
0.1uF  
C4  
10uF  
C6  
0.1uF  
C3  
3. 3V  
FB2  
2
1
VC CO  
C11  
10uF  
FB1  
1
2
VCC  
R1  
10  
BLM18BB221SN 1  
C5  
C10  
0.1uF  
BLM18BB221SN1  
C2  
C1  
U1  
0.1uF  
0.1uF  
10uF  
5
2
20  
MR  
VC CO  
VC CO  
3.3V  
15  
6
9
nXTAL_SEL  
nPLL_SEL  
FSEL_0  
C9  
C12  
nXTAL_SEL  
nPLL_SEL  
F_SEL0  
F_SEL1  
1
7
0.1uF  
0.1uF  
nc  
nc  
11  
FSEL_1  
R3  
133  
R4  
133  
13  
12  
Zo = 50 Ohm  
XTAL_IN  
25MHz (18pf)  
X1  
XTAL_OUT  
+
3
4
C7  
C8  
Q0  
27 pF  
Zo = 50 Ohm  
33pF  
-
nQ0  
3.3V  
14  
PECL Receiv er  
REF_CLK  
R 5  
82.5  
R6  
82.5  
R 10  
Zo = 50 Ohm  
19  
18  
Zo  
Q1  
LVCMOS  
nQ1  
Optional Four Resistor Thevinin Termination  
Zo = 50 Ohm  
+
Zo = 50 Ohm  
-
Logi c Control Input Examples  
PE CL R ecei v e r  
R7  
50  
R8  
50  
Set Logic  
Input to'1'  
Set Logic  
Input to '0'  
VCC  
VCC  
R9  
50  
R U1  
1K  
RU2  
Not Install  
To Logic  
Input  
pins  
ToLogic  
Input  
pins  
For ACtermination options consult the IDTApplicationsNote  
"Termination - 3.3V LVPECL"  
R D1  
N ot Install  
RD2  
1K  
FIGURE 3. IDT8R43002I-01 SCHEMATIC EXAMPLE  
As with any high speed analog circuitry, the power supply  
pins are vulnerable to random noise. To achieve optimum  
jitter performance, power supply isolation is required. The  
IDT8R43002i-01 provides separate V , V and V power  
designed for a wide range of noise frequencies. This low-  
pass filter starts to attenuate noise at approximately 10  
kHz. If a specific frequency noise component is known,  
such as switching power supplies frequencies, it is  
recommended that component values be adjusted and if  
required, additional filtering be added. Additionally, good  
general design practices for power plane voltage stability  
suggests adding bulk capacitance in the local area of all  
devices.  
CC  
CCO  
supplies to isolate any high switching noise fromCcCAoupling  
into the internal PLL.  
In order to achieve the best possible filtering, it is highly  
recommended that the 0.1uF capacitors be placed on the  
device side of the PCB as close to the power pins as  
possible. This is represented by the placement of these  
capacitors in the schematic. If space is limited, the ferrite  
bead, 10uf and 0.1uF capacitors connected to 3.3V can be  
placed on the opposite side of the PCB. If space permits,  
place all filter components on the device side of the board.  
The schematic example focuses on functional connections  
and is not configuration specific. Refer to the pin description  
and functional tables in the datasheet to ensure the logic  
control inputs are properly set. If AC coupling for PECL levels  
is required to the CLK/nCLK and/or Q0 and Q1 outputs, please  
refer to the IDT application note, “Termination – 3.3V PECL”  
Power supply filter recommendations are a general  
guideline to be used for reducing external noise from  
coupling into the devices. The filter performance is  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
9
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the IDT8R43002I-01.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8R43002I-01 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for V = 3.3V + 10% = 3.63V, which gives worst case results.  
CC  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core) = V  
* I  
= 3.63V * 130mA = 471.9mW  
MAX  
CC_MAX  
EE_MAX  
Power (outputs) = 30mW/Loaded Output pair  
MAX  
If all outputs are loaded, the total power is 2 * 30mW = 60mW  
Total Power  
(3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW  
_MAX  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability  
of the device. The maximum recommended junction temperature for the devices is 125°C.  
The equation for Tj is as follows: Tj = θ * Pd_total + TA  
JA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.  
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per  
Table 7 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.532W * 66.6°C/W = 120.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air  
flow and the type of board (multi-layer).  
θ by Velocity (Linear Feet per Minute)  
JA  
TABLE 7. THERMAL RESISTANCE θ FOR 20-PIN TSSOP, FORCED CONVECTION  
JA  
0
200  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
73.2°C/W  
98.0°C/W  
66.6°C/W  
88.0°C/W  
63.5°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
10  
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
3. Calculations and Equations.  
The purpose of this section is to derive the power dissipated into the load.  
LVPECL output driver circuit and termination are shown in Figure 4.  
VCCO  
Q1  
VOUT  
R L  
50  
VCCO - 2V  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination  
voltage of V - 2V.  
CCO  
•
•
For logic high, V = V  
= V  
– 0.9V  
OUT  
OH_MAX  
CCO_MAX  
)
- V = 0.9V  
OH_MAX  
(V  
CCO_MAX  
For logic low, V = V  
= V  
– 1.7V  
OUT  
OL_MAX  
CCO_MAX  
)
- V = 1.7V  
OL_MAX  
(V  
CCO_MAX  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
))  
/R ] * (V  
Pd_H = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
- V  
) =  
OH_MAX  
CCO_MAX  
CCO_MAX  
OH_MAX  
CCO_MAX  
OH_MAX  
CCO_MAX  
OH_MAX  
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW  
))  
/R ] * (V  
Pd_L = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
- V  
) =  
OL_MAX  
CCO_MAX  
CCO_MAX  
OL_MAX  
CCO_MAX  
OL_MAX  
CCO_MAX  
OL_MAX  
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
11  
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
RELIABILITY INFORMATION  
TABLE 8. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP  
JA  
θ by Velocity (Linear Feet per Minute)  
JA  
0
200  
500  
Single-Layer PCB, JEDEC Standard Test Boards  
Multi-Layer PCB, JEDEC Standard Test Boards  
114.5°C/W  
73.2°C/W  
98.0°C/W  
66.6°C/W  
88.0°C/W  
63.5°C/W  
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most  
designs.  
TRANSISTOR COUNT  
The transistor count for ICS8R43002I-01 is: 2955  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
12  
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP  
TABLE 9. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
MIN  
MAX  
N
A
20  
--  
1.20  
0.15  
1.05  
0.30  
0.20  
6.60  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
6.40  
c
D
E
6.40 BASIC  
0.65 BASIC  
E1  
e
4.30  
4.50  
L
0.45  
0°  
0.75  
8°  
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
13  
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClock® Crystal - to- 3.3V, 2.5 LVPECL Frequency Synthesizer  
TABLE 9. ORDERING INFORMATION  
Part/Order Number  
8R43002A-01PGGI  
8R43002A-01PGGI8  
Marking  
Package  
Shipping Packaging  
tube  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
IDT8R43002A01PGGI 20 Lead "Lead-Free" TSSOP  
IDT8R43002A01PGGI 20 Lead "Lead-Free" TSSOP  
2500 tape & reel  
NOTE: Parts that are ordered with a "G" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any  
patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications.  
Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to  
change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT8R43002A-01PGGI REVISION A MARCH 29, 2012  
14  
©2012 Integrated Device Technology, Inc.  
IDT8R43002I-01 Data Sheet  
FemtoClocks Crystal - to- 3.3 v, 2.5 LVPECL Frequency Synthesizer  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Techical Support  
netcom@idt.com  
+480-763-2056  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information  
in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are  
determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any  
kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property  
rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.  
Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDTor  
their respective third party owners.  
Copyright 2012. All rights reserved.  
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