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LY61L102516AML-10T

型号：

LY61L102516AML-10T

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

17 页

PDF大小：

980 K

下载PDF手册
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Rev. 1.2  
Description  
Initial Issued  
Added LY61L102516AGL  
Revised IOH/IOL = -8mA/4mA to IOH/IOL = -4mA/8mA in  
AC TEST CONDITIONS  
Added VCC=1.8V specifications  
Issue Date  
Feb.05. 2014  
Mar.26. 2014  
Sep.04. 2014  
Rev. 1.3  
Aug.16.2017  
PIN DESCRIPTION  
Revised  
Deleted WRITE CYCLE  
in page 1  
Notes :  
in page 10  
1. WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
FEATURES  
GENERAL DESCRIPTION  
Fast access time : 10ns (VCC=3.3V)  
15ns (VCC=1.8V)  
Low power consumption:  
Operating current:  
The LY61L102516A is a 16M-bit high speed CMOS  
static random access memory organized as 1024K  
words by 16 bits. It is fabricated using very high  
performance, high reliability CMOS technology. Its  
standby current is stable within the range of operating  
temperature.  
70mA (3.3V TYP.)  
50mA (1.8V TYP.)  
Standby current : 4mA(TYP.)  
Power supply: 1.8 or 3.3V  
All inputs and outputs TTL compatible  
Fully static operation  
The LY61L102516A operates power supply either  
1.8V or 3.3V, and all inputs and outputs are fully TTL  
compatible.  
Tri-state output  
Data byte control : LB# (DQ0 ~ DQ7)  
UB# (DQ8 ~ DQ15)  
Data retention voltage : 1.5V (MIN.)  
Green package available  
Package : 54-pin 400mil TSOP II  
48-ball 6mm x 8mm TFBGA  
PRODUCT FAMILY  
Speed  
Power Dissipation  
Product  
Family  
Operating  
Temperature  
Standby (ISB1, TYP.)  
Operating (ICC1, TYP.)  
VCC=1.65~2.4V VCC=2.7 ~3.6V  
VCC=1.65~2.4V  
VCC=2.7 ~3.6V VCC=1.65~2.4V  
VCC=2.7 ~3.6V  
0 ~ 70℃  
LY61L102516A  
15ns  
15ns  
10ns  
10ns  
4mA  
4mA  
4mA  
4mA  
50mA  
50mA  
70mA  
-40 ~ 85℃  
LY61L102516A(I)  
70mA  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
Vcc  
Vss  
A0 - A19  
DQ0 - DQ15 Data Inputs/Outputs  
1024Kx16  
A0-A19  
DECODER  
CE#, CE2  
WE#  
OE#  
LB#  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Lower Byte Control  
Upper Byte Control  
Power Supply  
MEMORY ARRAY  
UB#  
VCC  
DQ0-DQ7  
Lower Byte  
I/O DATA  
CIRCUIT  
VSS  
Ground  
COLUMN I/O  
DQ8-DQ15  
Upper Byte  
NC  
No Connection  
CE#  
CE2  
WE#  
OE#  
LB#  
CONTROL  
CIRCUIT  
UB#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
PIN CONFIGURATION  
DQ12  
Vcc  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
DQ11  
Vss  
DQ10  
DQ9  
Vcc  
DQ8  
A5  
2
DQ13  
DQ14  
Vss  
3
4
5
DQ15  
A4  
6
7
A3  
8
A6  
A2  
9
A7  
A1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
A8  
A0  
A9  
UB#  
CE#  
Vcc  
NC  
OE#  
Vss  
NC  
WE#  
CE2  
A19  
A18  
A17  
A16  
A15  
DQ0  
Vcc  
LB#  
A10  
A11  
A12  
A13  
A14  
DQ7  
Vss  
DQ6  
DQ5  
Vcc  
DQ4  
DQ1  
DQ2  
Vss  
DQ3  
TSOP II(Top View)  
LB# OE# A0  
DQ8 UB# A3  
DQ9 DQ10 A5  
A1  
A2 CE2  
A
B
C
D
E
F
A4 CE# DQ0  
A6 DQ1 DQ2  
Vss DQ11 A17 A7 DQ3 Vcc  
Vcc DQ12 NC A16 DQ4 Vss  
DQ14 DQ13 A14 A15 DQ5 DQ6  
DQ15 A19 A12 A13 WE# DQ7  
G
H
A18 A8  
A9 A10 A11 NC  
1
2
3
4
5
6
TFBGA(See through with Top View)  
TFBGA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 4.6  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-40 to 85(I grade)  
-65 to 150  
1
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is  
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
I/O OPERATION  
MODE  
Standby  
CE# CE2 OE# WE# LB#  
UB#  
SUPPLY CURRENT  
DQ0 - DQ7 DQ8 - DQ15  
H
X
X
L
X
X
X
X
X
X
X
X
High-Z  
High-Z  
High-Z  
High-Z  
ISB1  
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
X
H
H
H
H
H
L
L
X
L
H
L
L
H
L
X
L
H
L
L
H
L
High-Z  
High-Z  
DOUT  
High-Z  
DOUT  
DIN  
High-Z  
DIN  
High-Z  
High-Z  
High-Z  
DOUT  
DOUT  
High-Z  
DIN  
Output Disable  
Read  
ICC,ICC1  
ICC,ICC1  
Write  
L
L
ICC,ICC1  
L
DIN  
Note: H = VIH, L = VIL, X = Don't care.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
DC ELECTRICAL CHARACTERISTICS (VCC=2.7V~3.6V)  
SYM.  
VCC  
TEST CONDITION  
MIN.  
2.7  
2.2  
- 0.3  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
3.3  
3.6  
VCC+0.3  
0.8  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
VCC ≧ VIN ≧ VSS  
VCC ≧ VOUT ≧ VSS,  
Output Disabled  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -4mA  
2.4  
-
-
-
-
V
V
VOL  
IOL = 8mA  
0.4  
Average Operating  
Power supply  
Current  
CE# ≤0.2V and CE2≧ VCC-0.2V,  
-10  
-12  
-
-
70  
65  
120  
110  
mA  
ICC1 other pins at 0.2V or VCC-0.2V,  
II/O = 0mA; f=MAX.  
mA  
mA  
Standby Power  
Supply Current  
Notes:  
CE# ≧ VCC - 0.2V;  
Other pins at 0.2V or VCC-0.2V.  
ISB1  
-
4
40  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
DC ELECTRICAL CHARACTERISTICS (VCC=1.65V~2.4V)  
SYMBOL  
TEST CONDITION  
MIN. TYP. *4  
MAX.  
2.4  
VCC+0.3  
0.4  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
1.65  
1.4  
- 0.3  
- 1  
1.8  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
Output High Voltage  
Output Low Voltage  
VIH  
VIL  
-
-
-
*2  
ILI  
VCC ≧ VIN ≧ VSS  
1
A
µ
VCC ≧ VOUT ≧ VSS,  
Output Disabled  
IOH = -0.5mA  
ILO  
- 1  
-
1
A
µ
VOH  
VOL  
1.4  
-
-
-
-
V
V
IOL =1mA  
0.4  
Average Operating  
Power supply  
Current  
Standby Power  
Supply Current  
Notes:  
CE# ≦ 0.2,  
ICC1  
ISB1  
Other pin is at 0.2V or VCC-0.2V -15  
II/O = 0mA; f=MAX.  
-
-
50  
4
90  
40  
mA  
CE# ≧ VCC - 0.2V;  
Other pin is at 0.2V or VCC-0.2V  
mA  
1. VIH(max) = VCC + 2.0V for pulse width less than 6ns.  
2. VIL(min) = VSS - 2.0V for pulse width less than 6ns.  
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
CIN  
MIN.  
-
-
MAX  
8
10  
UNIT  
pF  
pF  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Speed  
10ns(VCC=3.3V), 15ns(VCC=1.8V)  
Input Pulse Levels  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
0.2V to VCC-0.2V  
3ns  
VCC/2  
CL = 30pF + 1TTL,  
Output Load  
IOH/IOL = -4mA/8mA(VCC=3.3V)  
IOH/IOL = -0.5mA/1mA(VCC=1.8V)  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
AC ELECTRICAL CHARACTERISTICS (VCC=2.7V~3.6V)  
(1) READ CYCLE  
LY61L102516A-10  
LY61L102516A-12  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
MIN.  
MAX.  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
tRC  
tAA  
10  
-
-
-
10  
10  
4.5  
-
12  
-
-
-
12  
12  
5
-
Address Access Time  
Chip Enable Access Time  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
tBA  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
-
-
*
*
2
0
-
-
2
-
3
0
-
-
2
-
-
-
*
*
4
4
-
4.5  
4
5
5
-
5
5
-
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
tBLZ  
*
-
-
*
0
-
0
(2) WRITE CYCLE  
PARAMETER  
LY61L102516A-10  
LY61L102516A-12  
SYM.  
tWC  
tAW  
tCW  
tAS  
UNIT  
MIN.  
10  
8
MAX.  
MIN.  
12  
10  
10  
0
MAX.  
Write Cycle Time  
-
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
5
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
8
0
8
0
6
0
2
-
Write Pulse Width  
tWP  
tWR  
tDW  
tDH  
tOW  
10  
0
7
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
0
2
-
*
tWHZ  
tBW  
*
8
10  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
AC ELECTRICAL CHARACTERISTICS (VCC=1.65V~2.4V)  
(1) READ CYCLE  
LY61L102516A-10  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read Cycle Time  
tRC  
tAA  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
15  
-
-
15  
15  
8
-
Address Access Time  
Chip Enable Access Time  
-
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
LB#, UB# Access Time  
-
*
3
0
-
*
-
*
5
5
-
tOHZ  
tOH  
tBA  
*
-
2
-
8
5
-
LB#, UB# to High-Z Output  
LB#, UB# to Low-Z Output  
tBHZ  
tBLZ  
*
-
*
0
(2) WRITE CYCLE  
PARAMETER  
LY61L102516A-10  
SYM.  
UNIT  
MIN.  
15  
12  
12  
0
MAX.  
tWC  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
tDH  
Write Cycle Time  
-
-
-
-
-
-
-
-
-
9
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
12  
0
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
LB#, UB# Valid to End of Write  
9
0
2
tOW  
tWHZ  
tBW  
*
*
-
12  
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
LB#,UB#  
tBA  
OE#  
tOE  
tOH  
tOHZ  
tBHZ  
tCHZ  
tOLZ  
tBLZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting  
parameter.  
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
WRITE CYCLE 1 (WE# Controlled) (1,2,4,5)  
tWC  
Address  
tAW  
CE#  
CE2  
tCW  
tBW  
tWP  
LB#,UB#  
WE#  
tAS  
tWR  
tOW  
tWHZ  
High-Z  
Dout  
(4)  
(4)  
tDW  
tDH  
Din  
Data Valid  
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5)  
tWC  
Address  
tAW  
CE#  
CE2  
tAS  
tWR  
tCW  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5)  
tWC  
Address  
tAW  
tWR  
CE#  
tAS  
tCW  
CE2  
tBW  
LB#,UB#  
tWP  
WE#  
Dout  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Din  
Data Valid  
Notes :  
1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.  
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed  
on the bus.  
3.During this period, I/O pins are in the output state, and input signals must not be applied.  
4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in  
a high impedance state.  
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data Retention  
SYMBOL  
TEST CONDITION  
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V  
VCC = 1.5V  
MIN. TYP. MAX. UNIT  
VDR  
1.5  
-
3.6  
V
Data Retention Current  
IDR  
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V  
Other pins at 0.2V or VCC-0.2V  
-
4
40  
mA  
Chip Disable to Data  
Retention Time  
Recovery Time  
tCDR  
tR  
See Data Retention Waveforms (below)  
0
-
-
-
-
ns  
ns  
tRC*  
tRC* = Read Cycle Time  
DATA RETENTION WAVEFORM  
Low VCC Data Retention Waveform (1) (CE# controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Low VCC Data Retention Waveform (2) (CE2 controlled)  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
CE2 ≦ 0.2V  
CE2  
VIL  
VIL  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
PACKAGE OUTLINE DIMENSION  
54-pin 400 mil TSOP II Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
48-ball 6mm × 8mm TFBGA Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
13  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
ORDERING INFORMATION  
Package Type  
Access Time  
Temperature  
Packing  
Type  
Lyontek Item No.  
(Speed/ns)  
10  
Range(℃)  
54-pin (400mil)  
TSOP II  
Tray  
LY61L102516AML-10  
LY61L102516AML-10T  
LY61L102516AML-10I  
LY61L102516AML-10IT  
0℃~70℃  
Tape Reel  
Tray  
-40℃~85℃  
Tape Reel  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
14  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
ORDERING INFORMATION  
Package Type  
Access Time  
Temperature  
Packing  
Type  
Lyontek Item No.  
(Speed/ns)  
10  
Range(℃)  
48-ball  
Tray  
LY61L102516AGL-10  
LY61L102516AGL-10T  
LY61L102516AGL-10I  
LY61L102516AGL-10IT  
0℃~70℃  
Tape Reel  
Tray  
(6mm x 8mm)  
TFBGA  
-40℃~85℃  
Tape Reel  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
15  
LY61L102516A  
1024K X 16 BIT HIGH SPEED CMOS SRAM  
Rev. 1.3  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
16  
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